CN107431487A - FPGA based on compact ReRAM - Google Patents
FPGA based on compact ReRAM Download PDFInfo
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- CN107431487A CN107431487A CN201680015229.XA CN201680015229A CN107431487A CN 107431487 A CN107431487 A CN 107431487A CN 201680015229 A CN201680015229 A CN 201680015229A CN 107431487 A CN107431487 A CN 107431487A
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- transistor
- reram
- programming
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- output node
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17748—Structural details of configuration resources
- H03K19/1776—Structural details of configuration resources for memories
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0069—Writing or programming circuits or methods
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- Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Semiconductor Memories (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
One kind recommends resistive ram element circuit, including output node, wordline and the first and second bit lines.First resistor random access memory device is connected between the first bit line and output node, and second resistance random access memory device is connected between output node and the second bit line.First programming transistor has grid, the drain electrode for being connected to output node and the source electrode for being connected to wordline.Drain electrode and source electrode of second programming transistor with the grid, the source electrode for being connected to the first programming transistor for being connected to wordline.First and second programming transistors have identical spacing, identical channel length and identical gate dielectric thickness, and the gate dielectric thickness is selected to the programmed and erased potential that tolerance is met with during the operation of ReRAM element circuits is recommended.
Description
The cross reference of association request
It is U.S. Patent application No.15/010,222 that the International Application claim was submitted on January 29th, 2016, entitled
The priority of " Compact ReRAM Based FPGA (FPGA based on compact ReRAM) "；The patent application is required in 2015
U.S. Provisional Patent Application No.62/132,333, entitled " the Compact ReRAM Based FPGA that on March 12, in submits
(FPGA based on compact ReRAM) " rights and interests, entire contents are incorporated by reference in this in the disclosure.
Background
Resistive ram (ReRAM) unit is recommended (disclosed in such as United States Patent (USP) No.8,415,650
Those ReRAM units) in the configuration for configurable logic integrated circuit (such as field programmable gate array (FPGA))
Using being attractive in memory.
When using deep-submicron (14nM and more than) transistor to design circuit, any change of crystal tube pitch promotes
Designer is using big transition region to allow the photoetching of pattern to produce.The scope of the transition region can be from 0.2 μm to 1 μm or bigger,
And configurable logic collection be laid out in design with compact efficient, that configuration memory units circuit is recommended using all ReRAM
Into can be one notable during circuit the shortcomings that.
FPGA requires mixed logic, routing switch and programming transistor.In order to eliminate the required mistake of photoetching process requirement
Area is crossed, all devices listed above must have identical spacing, including channel length spacing.Generally, the requirement with difference
The device of voltage operation is incompatible.
For ReRAM memory cells, compared with the other transistors used in integrated circuit, for these
The transistor device that ReRAM memory cells are programmed biases higher drain and gate is subjected to, and is programming and grasping
It will be switched during work at higher gate bias.
Accordingly, there exist the needs of the design to ReRAM configuration memory units not associated with these shortcomings.The present invention
Target be to provide for eliminating the ReRAM of the transition region and recommend configuration memory units circuit.
The content of the invention
According to the present invention, ReRAM element circuits are recommended using being cascaded in series for and with identical spacing and channel length
Two programming transistors.Recommending the switching transistor used in ReRAM element circuits has and two programming transistor identicals
Spacing and channel length, both to be tieed up to programming device and for the switching transistor of configuration and/or interconnection logic unit
Hold identical spacing and channel length.
According to the present invention, its state is used in the phase used in programming transistor by the ReRAM switching transistors configured
Stack pile dielectric is to mitigate the elevated gate stress during programming.The grid for also allowing configuration to switch using thicker dielectric
Pole is during operation in higher VCCPlace's hypervelocity, thus allows by full VCCLogical signal.
According to an aspect of the present invention, recommend resistive ram element circuit include output node, wordline,
First bit line and the second bit line.First resistor random access memory device is connected between the first bit line and output node, and
Second resistance random access memory device is connected between output node and the second bit line.First programming transistor has connection
Grid to wordline, the drain electrode for being connected to output node and source electrode.Second programming transistor has the grid for being connected to wordline
Pole, be connected to the first programming transistor source electrode drain electrode and source electrode.First and second programming transistors have between identical
Away from, identical channel length and identical gate dielectric thickness, the gate dielectric thickness is selected to tolerance and recommended
The programmed and erased potential met with during the operation of ReRAM element circuits.
According to another aspect of the present invention, at least one switching transistor has the grid for being connected to output node, connection
To the first logical network node drain electrode and be connected to the source electrode of the second logical network node.Switching transistor has and the
One and the second programming transistor identical spacing, channel length and gate dielectric thickness.
Accompanying drawing
These and other spies of the present invention will be better understood when with reference to following description, appended claims and accompanying drawing
Sign, aspect and advantage, in the accompanying drawings：
Fig. 1 is the schematic diagram for recommending ReRAM units according to one aspect of the invention；
Fig. 2 is the sectional view of the exemplary layout for recommending ReRAM units of the present invention；
Fig. 3 is the top view of the exemplary layout for recommending ReRAM units of the present invention.
Description
It would be recognized by those skilled in the art that the following description of the present invention be only illustrative and not in any way
It is limited.Other embodiments of the invention are readily able to imply oneself to such those skilled in the art.
With reference first to Fig. 1, schematic diagram is shown recommends ReRAM element circuits according to the illustrative of one aspect of the invention
10.First ReRAM devices 12 and the series coupled of the 2nd ReRAM devices 14 are to form ReRAM units 16.The ReRAM being connected in series
First end of the device 12,14 at a terminal of ReRAM devices 12 is coupled to the first bit line (BL) 18, and is connected in series
Second end of the ReRAM devices 12,14 at a terminal of ReRAM devices 14 is coupled to the second bit line (BL_bar) 20.In Fig. 1
The ReRAM units 16 of description are front and rear ReRAM units, are useful, but ability particularly with biased witch as shown in figure
Field technique personnel will be appreciated that back-to-back ReRAM units can also be used in the present invention.
As described above, ReRAM devices 12 and 14 include recommending ReRAM units 16 together.Between ReRAM devices 12 and 14
Share the grid that output node 22 is connected to one or more switching transistors.Fig. 1, which is shown, is connected to two switching transistors
The shared output node 22 of 24a and 24b grid.Switching transistor 24a be illustrated as being connected to two logical network node 26a and
Between 28a.Similarly, switching transistor 24b is illustrated as being connected between two logical network nodes 26b and 28b.This area skill
Art personnel will be appreciated that logical network node 26a, 26b, 28a and 28b can be represented to be connected to by switching transistor 24a and 24b respectively
The logic gates or other devices in programmable integrated circuit together, and can also represent single in such a integrated circuit
The circuit network of the function of the logical device defined in logical device, or the wiring interconnection in programmable integrated circuit can be represented.
Although fig 1 illustrate that multiple switch transistor 24a and 24b can be recommended so as to more than one logic circuit net by single
ReRAM units 16 activate, but skilled artisans will appreciate that, single switch transistor, which may be connected to, shares output node 22.
According to an aspect of the present invention, using a pair of the n-channel programming transistors 30 and 32 being cascaded in series for come to recommending
ReRAM units 16 are programmed.N-channel programming transistor 30 makes its drain electrode be connected to the shared output for recommending ReRAM units 16
Node 22, and its source electrode is connected to the drain electrode of n-channel programming transistor 32.In an actual embodiment, single n+ areas use
Make the drain electrode of the source electrode and n-channel programming transistor 32 of n-channel programming transistor 30.The source electrode of n-channel programming transistor 32 connects
It is connected to wordline WLS.By being connected in series two n-channel programming transistors 30 and 32, n-channel programming transistor 30 and 32 is both
It is designed to have and n-channel switching transistor 24a and 24b identical spacing and channel length.For switching transistor 24a
The logical device being used for 24b identical spacing and channel length in integrated circuit.
According to another aspect of the present invention, manufacture has identical grid electricity by Ei to thickness n-channel programming transistor 30
With 32 and n-channel switching transistor 24a and 24b.N-channel programming transistor 30 and 32 pushes away with tolerance ReRAM is selected to
Memory cell is drawn by the gate dielectric thickness for the programmed and erased potential being subjected to during its operation.Most of integrated circuits
Including input/output (I/O) transistor for the integrated circuit to be docked with external module.Because below these transistor AND gates
Component is docked, and these components are often operated with the voltage higher than the voltage generally found in IC interior, I/O transistors
It is generally manufactured to the gate dielectric thickness bigger than other transistors that inside uses in the integrated circuit.Therefore,
It is probably convenient using with the n-channel programming transistor 30 and 32 with I/O transistor identical gate dielectric thickness.
For transistor 24a and 24b using the larger gate dielectric thickness of identical will mitigate switching transistor 24a and
The elevated gate stress that 24b will be subjected to during programming originally, because its grid, which is connected to, recommends ReRAM memory cells 16
Common points 22, and the node will undergo program voltage during the erasing and programming of memory cell 16.For switch
Transistor 24a and 24b also allow switching transistor 24a and 24b grid during operation higher using thicker dielectric
Value VCCPlace's hypervelocity, thus allows switching transistor 24a and 24b to pass through full VCCLogical signal.As replacement, thin gate oxidation
Thing can be used for switching transistor 24a and 24b, it should be noted that avoiding the stress during programming and erasing operation.This can lead to
Cross source/drain bias boost to V during programmingCCLogic is carried out.
During the normal operating of programmable integrated circuit, bit line BL 18 is connected to voltage source VCCAnd BL_bar 20 is connected
To the potential being such as grounded.WLS lines are grounded or connected to slightly positive potential (such as 0.9V) to limit n-channel programming
Sewing in transistor 30 and 32.ReRAM units 16 are recommended to be programmed so that in any one the time only He of ReRAM devices 12
One of 14 open, and the voltage that thus or by common points 22 is pulled up on bit line BL 18 or are pulled low to common points 22
Voltage (normally grounded) on bit line BL_bar.Show wherein ReRAM devices 12 to open in Fig. 1 and what ReRAM devices 14 were closed
Recommend ReRAM units 16.Thus common points 22 are pulled up to the voltage (V on bit line BL 18CC), thus conducting switchs crystal
Pipe 24a and 24b (being illustrated as n-channel transistor in Fig. 1).
Referring now to both Fig. 2 and Fig. 3, the exemplary layout for recommending ReRAM units of the invention is shown.Fig. 2 is this
The sectional view of the exemplary layout 40 for recommending ReRAM element circuits 10 of invention.Fig. 3 be the present invention recommend ReRAM units electricity
The top view of the exemplary layout 40 on road 10.Those skilled in the art will be observed that the layout shown in Fig. 2 and 3 is only to explain
Property, and be infinite.
Recommend in p-type substrate or trap 42 that ReRAM element circuits 10 (Fig. 1) are formed in integrated place's circuit.N+ areas 44
The drain electrode of n-channel programming transistor 30 is formed, and n+ areas 46 form its source electrode, and serve as the leakage of n-channel programming transistor 32
Pole.Polysilicon or metal wire 48 form the grid of n-channel programming transistor 30.N+ areas 50 form n-channel programming transistor 32
Source electrode, and polysilicon or metal wire 52 form its grid.As shown in being formed from the first metal interconnecting layer (M1), contact 54 is by n
The polysilicon gate 48 and 52 of raceway groove programming transistor 30 and 32 is connected to wordline 34.Skilled artisans will appreciate that p-channel
Transistor may be alternatively used in other embodiments of the invention.
The switching transistor shown in Fig. 3 includes source area 56 and drain region 58, and they are separated by grid 60.It is noted that
Fig. 2 sectional view is that part is made by one of switching transistor 24a and 24b source area.Switching transistor can be n ditches
Road or p-channel device.ReRAM devices 12 are formed between each metal interconnecting layer on the integrated (for example, first and second
Between metal level M1 and M2).In figs 2 and 3, ReRAM devices 12 be illustrated as being formed M1 metal segments 62 and M2 metal segments 64 it
Between.ReRAM devices 12 are formed in metal segments 62, and are connected to M2 metal segments 64 by contact 66.ReRAM devices 12 pass through
Contact 68 is connected to bit line BL 18.
Contact with common points 22 is made by contact 72 from M2 sections 64 to M1 metal segments 70.Contact 74 is golden by M1
Category section 70 is connected to the polysilicon gate 60 of switching transistor.ReRAM devices 14 are illustrated as being formed in M1 metal segments 70 with being formed
Between second bit line Bl_bar 20 M2 metal segments.M1ReRAM devices 14 are connected to the second bit line Bl_bar 20 by contact 76.
M1 metal segments 70 are connected to the n+ areas 44 for the drain electrode to form n-channel programming transistor 30 by contact 78.Metal segments 80 form wordline
WLS and the n+ areas 50 that the source electrode to form programming transistor 32 is connected to by contact 82.
Recommend ReRAM units 16 by open in ReRAM devices 12 and 14 it is desired that so as to or cut-off, or conducting open
Transistor 24a and 24b is closed to program.First, both ReRAM devices 12 and 14 are wiped free of.Erasing ReRAM devices mean it
Cut-off no longer passes through electric current so as to it.In order to wipe ReRAM devices 12, bit line BL 18 is connect high voltage (for example, 1.8V) and is total to
It is grounded with node 22.In order to avoid to ReRAM devices 14 plus stress, the second bit line Bl_bar 20 be also grounded from without across
The additional potential of ReRAM devices 14.In order to wipe ReRAM devices 14, common points 22 connect high voltage (for example, 1.8V) and
Two bit line Bl_bar 20 are grounded.In order to avoid to ReRAM devices 12 plus stress, bit line BL 18 also connect high voltage from without
The additional potential of across ReRAM device 12.
When both ReRAM units 12 and 14 are wiped free of, the selected device quilt in two ReRAM devices 12 and 14
Programming.In order to be programmed to ReRAM devices 12, bit line BL 18 be grounded and common points 22 connect high voltage (for example,
1.8V).In order to avoid being programmed to ReRAM devices 14 plus stress to ReRAM devices 12 simultaneously, the second bit line Bl_bar 20
Also high voltage is connect, from without the additional potential of across ReRAM device 14.In order to be programmed to ReRAM devices 14, common section
Point 22 is grounded and the second bit line Bl_bar 20 is connect high voltage.In order to avoid to ReRAM devices 12 plus stress, bit line BL 18
Ground connection is from without the additional potential of across ReRAM device 12.
According to another aspect of the present invention, two n-channel programming transistors 30 and 32 being connected in series are coupling in common section
Between point 22 and wordline WLS.The grid of n-channel transistor 30 and 32 is connected to wordline WL 34 together.
Although this disclosure relates to the application of ReRAM memory devices, wherein in first voltage switch logic, and in the second electricity
Pressure is programmed and wiped to ReRAM units, but skilled artisans will appreciate that, it is equally applicable to it is expected in different operating mould
Switch the miscellaneous equipment of two different voltages in formula.
Although discussing the present invention in considerable detail with reference to some preferred embodiments, other embodiments are also possible
's.Therefore, scope of the following claims and it should not be limited to the description of preferred embodiment included in the disclosure.
Claims (5)
1. one kind recommends resistive ram element circuit, including：
Output node；
Wordline；
First bit line；
Second bit line；
First resistor random access memory device, it is connected between first bit line and the output node；
Second resistance random access memory device, it is connected between the output node and second bit line；
First programming transistor, it, which has, is connected to the grid of the wordline, the drain electrode for being connected to the output node, Yi Jiyuan
Pole；And
Second programming transistor, it, which has, is connected to the grid of the wordline, is connected to the described of first programming transistor
The drain electrode of source electrode and source electrode,
Wherein described first and second programming transistor has identical spacing, identical channel length and identical grid
Dielectric thickness, the gate dielectric thickness of first and second programming transistor are selected to tolerance and recommended described
The programmed and erased potential met with during the operation of ReRAM element circuits.
2. recommend resistive ram element circuit as claimed in claim 1, it is characterised in that：
The resistive ram element circuit of recommending is fabricated in the integrated circuit with input/output transistors
On；And
The thickness of the gate-dielectric of first and second programming transistor is described with the input/output transistors
The thickness of gate-dielectric is identical.
3. recommend resistive ram element circuit as claimed in claim 2, it is characterised in that further comprise：
At least one switching transistor, it, which has, is connected to the grid of the output node, is connected to the first logical network node
Drain electrode and be connected to the source electrode of the second logical network node；And
Wherein described switching transistor has and the first and second programming transistors identical spacing, channel length and the grid
Dielectric thickness.
4. recommend resistive ram element circuit as claimed in claim 1, it is characterised in that：
The resistive ram element circuit of recommending is fabricated on the integrated circuit with logic transistor；And
The thickness of the gate-dielectric of first and second programming transistor is more than the grid of the logic transistor
Extremely dielectric thickness.
5. recommend resistive ram element circuit as claimed in claim 4, it is characterised in that further comprise：
At least one switching transistor, it, which has, is connected to the grid of the output node, is connected to the first logical network node
Drain electrode and be connected to the source electrode of the second logical network node；And
Wherein described switching transistor has and the first and second programming transistors identical spacing, channel length and the grid
Dielectric thickness.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201562132333P | 2015-03-12 | 2015-03-12 | |
| US62/132,333 | 2015-03-12 | ||
| PCT/US2016/015756 WO2016144434A1 (en) | 2015-03-12 | 2016-01-29 | COMPACT ReRAM BASED FPGA |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107431487A true CN107431487A (en) | 2017-12-01 |
| CN107431487B CN107431487B (en) | 2019-12-24 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201680015229.XA Active CN107431487B (en) | 2015-03-12 | 2016-01-29 | FPGA based on compact ReRAM |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107431487B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108427829A (en) * | 2018-02-09 | 2018-08-21 | 京微齐力(北京)科技有限公司 | A kind of FPGA with public cable architecture |
| CN112292728A (en) * | 2018-06-28 | 2021-01-29 | 美高森美SoC公司 | Circuit and layout for resistive random access memory array with two bit lines per column |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040125643A1 (en) * | 2002-12-30 | 2004-07-01 | Kang Hee Bok | Nonvolatile memory device |
| US20070146012A1 (en) * | 2005-11-03 | 2007-06-28 | Cswitch Corp. A California Corporation | Reconfigurable logic structures |
| US20100110767A1 (en) * | 2007-03-13 | 2010-05-06 | Yoshikazu Katoh | Resistance variable memory apparatus |
-
2016
- 2016-01-29 CN CN201680015229.XA patent/CN107431487B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040125643A1 (en) * | 2002-12-30 | 2004-07-01 | Kang Hee Bok | Nonvolatile memory device |
| US20070146012A1 (en) * | 2005-11-03 | 2007-06-28 | Cswitch Corp. A California Corporation | Reconfigurable logic structures |
| US20100110767A1 (en) * | 2007-03-13 | 2010-05-06 | Yoshikazu Katoh | Resistance variable memory apparatus |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108427829A (en) * | 2018-02-09 | 2018-08-21 | 京微齐力(北京)科技有限公司 | A kind of FPGA with public cable architecture |
| CN112292728A (en) * | 2018-06-28 | 2021-01-29 | 美高森美SoC公司 | Circuit and layout for resistive random access memory array with two bit lines per column |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107431487B (en) | 2019-12-24 |
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