JPH0766710A - Input/output buffer ciircuit - Google Patents

Abstract

PURPOSE:To exclude a leakage current in an I/O buffer circuit for executing I/O operation to/from a device with a power supply voltage level higher than its own power supply voltage. CONSTITUTION:In the case of outputting an 'L' level signal to an I/O terminal 7, an I/O control circuit 11 respectively impresses 'H' level voltage and Vcc1 level voltage to the gate terminal of a PMOS P1 and the gate terminal of NMOS NO2. Since the PMOS P1 is turned off and the NMOS NO2 is turned on as the result of the voltage impression, an I/O terminal 7 goes to an 'L' level. Simultaneously a PMOS P3 is turned on and the gate terminal of the PMOS P1 is raised up to the VCC1 level, so that the PMOS P1 is completely turned off and no leakage current flows. Even when an 'H' level signal is inputted to the I/O terminal 7, the PMOS P1 is completely turned off and a leakage pass from the terminal 7 to power supply Vcc1 through the PMOS P1 is interrupted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output buffer circuit used for inputting / outputting a signal in a semiconductor integrated circuit device, and more particularly to inputting / outputting a signal to / from a semiconductor integrated circuit device operating at different power supply voltages. The present invention relates to an input / output buffer circuit that can be used.

[0002]

2. Description of the Related Art As a conventional input / output buffer circuit for inputting / outputting a signal to / from a device which inputs / outputs a signal at a power supply voltage level (for example, 5V) higher than its own power supply voltage (for example, 3.3V). , For example, JP-A-4-32902
The circuit described in Japanese Patent No. 4 is known.

FIG. 12 shows the configuration of the input / output buffer circuit described in Japanese Patent Laid-Open No. 4-329024.

The input / output buffer circuit will be described below.

In the following description, a PMOS transistor (hereinafter simply referred to as "PMOS") is represented by QP,
The NMOS transistor (hereinafter, simply referred to as “NMOS”) will be described and represented by QN. All PMOS and NMOS transistors are of the enhanced type.

A power supply voltage Vcc1 of 3.3 V, for example, is applied to the integrated circuit including the input / output buffer circuit as an operating main power supply. Further, the input / output buffer circuit is supplied with the operating power supply Vcc2 of another device for input / output. Vcc2 is a voltage higher than 3.3 V, and is, for example, 5 V, which is an input / output terminal pad PAD.
The output circuit connected to is PMOS QP3 and NMOS Q
The N well, which is composed of N3 and QN4 and is the substrate of the PMOS QP3, is connected to the level potential of the operating power supply voltage Vcc2 of the device to be interfaced. Also, P
Between the gate terminal of the MOS QP3 and the pad PAD, the gate voltage is Vcc1 and the substrate N well is Vcc2.
The PMOS QP2 connected to is inserted. on the other hand,
The input circuit connected to the pad PAD, which is an input / output terminal,
The input buffer circuit 2 is composed of an NMOS QN5 whose gate is connected to Vcc and an input buffer circuit 2. The input buffer circuit 2 is composed of a two-stage inverter.

On the other hand, the output node N1 of the input / output control circuit 1 to which the output data signal Dout and the output activation signal EN are input is input to the inverter composed of the PMOS QP1 and the NMOS QN1. The output of the inverter is connected to the NMOS Q whose gate voltage is connected to Vcc1.
It is connected to one end of N2. Also, this NMOS QN2
The other end of is connected to the gate terminal of the PMOS QP3.

A PMOS QP2 having a gate voltage connected to Vcc1 and a substrate N well connected to Vcc2 is inserted between the gate terminal of the PMOS QP3 and the pad PAD.

The gate terminal of the NMOS QN3 is Vcc1
The gate terminal of the NMOS QN4 is connected to the output node N2 of the input / output control circuit 1.

As a circuit related to the input side, a pad PAD is connected to one end of an NMOS QN5 whose gate terminal is connected to Vcc1 and the other end is connected to the input buffer circuit 2.

The operation of this input / output buffer circuit will be described below.

First, the case of operating as an output buffer will be described.

When outputting the "H" level to the pad PAD, the input / output control circuit 1 outputs the Vcc1 level to the node N1 and the GND level to the node N2. This enables PMOS QP3 and NMOS
Since the GND level is applied to the gate of QN4, the PMOS QP3 is turned on and the NMOS QN4 is turned off. Accordingly, the pad PAD becomes "H" level.

On the other hand, when outputting the "L" level to the pad PAD, the input / output control circuit 1 outputs the GND level to the node N1 and the Vcc1 level to the node N2. As a result, the Vcc1-Vtn level is applied to the gate of the PMOS QP3 and the Vcc1 level is applied to the gate of the NMOS QN4. Note that Vtn is NM
It is the threshold voltage of OS QN2. Therefore, PMO
Since S QP3 is turned off and NMOS QN4 is turned on, the pad PAD becomes "L" level.

Now, the voltage applied to the gate of the PMOS QP3 is not Vcc but Vcc1-Vt.
Since it is n, it is not normally completely turned off. Therefore, in order to completely turn it off, a process ingenuity is made to reduce the threshold voltage of the NMOS QN2 or increase the absolute value of the threshold voltage of the PMOS QP3.

Next, a case where this input / output buffer circuit operates as an input buffer will be described.

In this case, the input / output control circuit 1
Thus, the GND level is output to the nodes N1 and N2.

When the "L" level is input to the pad PAD, the gate voltage of the PMOS QP3 is Vcc1-V.
It is tn, and due to the process ingenuity,
PMOS QP3 is completely off. Also, NMO
Since the gate voltage of S QN4 is at the GND level, the NMOS QN4 is off. Therefore, the output of the output circuit is in a high impedance state.

Then, it is input from the pad PAD.
Depending on the L "level, the NMOS Q of the input buffer circuit 2
After passing through N5, the GND level is transmitted to the node N3. In response to this, the input buffer circuit 2 receives the GND "
The L ″ level is transmitted as an input data signal Din inside the chip.

On the other hand, when the "H" level is input to the pad PAD and the level exceeds Vcc1 + | Vtp |, the level is turned on to the gate of the PMOS QP3 via the PMOS QP2 which is turned on. It is transmitted. Therefore, the PMOS QP3 is completely turned off. Therefore, from the pad PAD through the PMOS QP3, the power source Vcc1
The leak path flowing to is cut off. At that time, PMOS
The gate potential of QP3 becomes higher than the output potential Vcc1 of the inverter composed of QP1 and QN1, but the NMOS Q
Since it is separated by N2, no problem occurs. Since the gate voltage of the NMOS QN4 is at the GND level, the NMOS QN4 is turned off. Therefore, the output of the output circuit is in a high impedance state.
Further, since the N well which is the substrate of the PMOS QP3 and QP2 is connected to the power supply Vcc2, even if a signal having the same potential as the power supply Vcc2 is input to the pad PAD, the drain and the N well are not forward-biased. No leak current flows.

When the "H" level is input from the pad PAD, the node N after passing through the NMOS QN5.
Vcc1-Vtn5 level is transmitted to 3. However,
Vtn5 is the threshold voltage of the NMOS QN5. In response to this, the input buffer circuit 2 transmits the "H" level of Vcc1 inside the chip. However, at this time, since the Vcc1-Vtn5 level, not Vcc1, is transmitted to the PMOS gate of the first-stage inverter of the input buffer circuit 2, it is not completely turned off, and a leak current flows.

[0022]

As described above, in the input / output buffer circuit described in Japanese Patent Laid-Open No. 4-329024, first, when the level of the pad PAD is "L",
In order to prevent the leak current of the PMOS QP3 of the output part,
It was necessary to reduce the threshold voltage of the NMOS QN2 or increase the absolute value of the threshold voltage of the PMOS QP3. Moreover, a leak current is generated in the input buffer circuit 2.

Therefore, the present invention is an input / output buffer circuit capable of inputting / outputting a signal to / from a device which inputs / outputs a signal at a power supply voltage level higher than its own power supply voltage, and increases the number of process steps. It is an object of the present invention to provide an input / output buffer circuit in which the leak current is eliminated without the need.

Further, the present invention is an input / output buffer circuit capable of inputting / outputting a signal to / from a device which inputs / outputs a signal at a power supply voltage level higher than its own power supply voltage. It is an object of the present invention to provide an input / output buffer circuit capable of eliminating the leak current by the above device.

[0025]

In order to achieve the above object, the present invention provides, for example, as shown in FIG. 2, an input / output terminal 7 for inputting / outputting a signal outside the circuit, and an electrostatic breakdown protection element 12.
, An input buffer circuit 10 for inputting a signal from the input / output terminal 7, and a 2-input NA driven by the first power supply Vcc1.
An input / output control circuit 11 composed of an ND3, a two-input NOR 4 and an inverter 5, and a substrate inserted between the first power supply Vcc1 and the input / output terminal 7 and a second power supply Vcc2.
The first PMOS P1 connected to the first PMOS P1 and one end of the first PMOS P1 to the gate terminal of the first PMOS P1 and the other end of the first input to the output terminal of the 2-input NAND3 of the input / output control circuit 11. First NM connected to power supply Vcc1
OS N01, one end of which is connected to the gate terminal of the first PMOS P1, the other end is connected to the input / output terminal 7, the gate terminal is connected to the first power supply Vcc1, and the substrate N well is connected to the second power supply Vcc2. A second PMOS P2 and a second NMOS whose one end is connected to the ground potential terminal and whose gate terminal is connected to the output terminal of the two-input NOR 4 of the input / output control circuit 11.
N02, a third NMOS N03 having one end connected to the input / output terminal 7, the other end connected to the second NMOS N02, and a gate terminal connected to the first power supply Vcc1, respectively, and one end connected to the input / output control circuit. The other end is connected to the output terminal of the 2-input NAND 3 of the circuit 11, the gate is connected to the gate terminal of the first PMOS P1, the gate is connected to the input / output terminal 7, and the substrate is connected to the second power source Vc.
An output buffer circuit 13 comprising a third PMOS P3 connected to c2 is provided.

Further, as shown in FIG. 2, the output buffer circuit 13 further includes an inverter having one end at the input / output terminal 7 and the other end at PMOS P5 and NMOS N05.
A fourth NMOS N04 whose gate is connected to the first power supply Vcc1 at its input terminal, and one end of which is the first power supply Vcc1
And an input buffer circuit 10 including a gate connected to the other input terminal of the inverter, a gate connected to the output terminal of the inverter, and a fourth PMOS P4 having the substrate connected to the first power supply Vcc1.
Provided is an input / output buffer circuit to which is added.

[0027]

According to the input / output buffer circuit shown in FIG. 2, the input / output terminal 7 becomes the "L" level, and the first power supply Vc
c2 and the input / output terminal 7 are connected to the second power source V
When turning off the first PMOS P1 connected to cc2,
One end is a 2-input NAN of the input / output control circuit 11.
The other end is connected to the output terminal of D3, the gate terminal is connected to the gate terminal of the first PMOS P1, the gate terminal is connected to the input / output terminal 7, and the substrate is connected to the second terminal.
The third PMOS P3 connected to the power source Vcc2 is turned on, and the gate terminal of the PMOS P1 becomes the Vcc1 potential. Therefore, PM is not required for process
Since the OS P1 can be completely turned off, a leak current from the power supply Vcc1 to the input / output terminal 7 can be prevented. Since the substrate of the PMOS P3 is connected to the second power source Vcc2, the gate terminal of the first PMOS P1 is V
It is not forward biased even if it reaches the cc2 potential. As a result, it is possible to interface with a device that operates at a power supply voltage (Vcc2) higher than the power supply voltage (Vcc1) at which it operates.

When the "H" level is input to the input / output terminal 7, if the fourth PMOS P4 is not installed, the level of the input terminal of the inverter composed of the PMOS P5 and the NMOS N05 becomes Vcc1. -It rises only up to Vtn5. However, the level of the input terminal of the inverter is pulled up to Vcc1 by the fourth PMOS P4 which receives the output of the output terminal of the inverter at its gate. Therefore, PMOS P5 and NMOS N0
It is possible to prevent the leak current flowing through the inverter composed of five.

[0029]

Embodiments of the input / output buffer circuit according to the present invention will be described below.

First, FIG. 1 shows the configuration of a semiconductor integrated circuit device having an input / output buffer circuit according to this embodiment.

In the figure, reference numeral 1000 denotes a semiconductor integrated circuit device including the input / output buffer circuit according to this embodiment, and 200
Reference numeral 0 denotes another semiconductor integrated circuit which inputs and outputs with the semiconductor integrated circuit device 1000. Semiconductor integrated circuit 1000
Is a logic circuit unit 200 that operates at the power supply voltage Vcc1,
A plurality of input / output buffer circuits 10 used by the logic circuit unit 200 to input / output signals to / from another semiconductor integrated circuit 2000.
It has 0. Here, the semiconductor integrated circuit device 2000
Is a device that operates at a power supply voltage Vcc2 higher than Vcc1, and the input / output buffer circuit 100 of the semiconductor integrated circuit 1000 has a power supply voltage Vcc1 or a power supply voltage Vc.
c1 and the power supply voltage Vcc2 are supplied. Power supply voltage Vcc
1 is 3.3 V or 2.5 V, for example, and the power supply voltage V
cc2 is a power supply voltage higher than Vcc1, for example, 5V or 3.3V.

In the semiconductor integrated circuit 1000, the "H (High)" level is higher than the voltage Vc by the input / output buffer circuit 100.
c1 or Vcc2, "L (Low)" level is GN
D signal is output and "H" is set in the input / output buffer circuit 100.
A signal whose level is voltage Vcc2 and whose "L" level is GND is input. Here, “GND” represents a ground voltage (ground voltage).

Details of the input / output buffer circuit 100 will be described below.

First, a first embodiment of the input / output buffer circuit will be described.

FIG. 2 shows the configuration of the input / output buffer circuit according to the first embodiment.

As described above, power supply voltage Vcc1 and power supply voltage Vcc2 higher than Vcc1 are applied to the input / output buffer circuit shown in FIG.

As shown in the figure, the input / output buffer circuit according to the first embodiment has an input / output terminal 7 for inputting / outputting an external signal, an electrostatic breakdown protection element 12, and an input / output terminal 7.
An input circuit 10 for inputting a signal from the input / output terminal 7, an input circuit 10 for inputting a signal from the input / output terminal 7, a 2-input NAND 3, a 2-input NOR 4 and an inverter 5 driven by the first power supply Vcc1. It is composed of an input / output control circuit 11.

Further, the output circuit 13 has a first power source Vcc.
1 and a first PMOS P1 inserted between the input / output terminal 7 and the N-type substrate well connected to the second power source Vcc2;
One end is connected to the gate terminal of the first PMOS P1 and the other end is connected to the output terminal of the 2-input NAND3 of the input / output control circuit 11, and the gate terminal is connected to the first power supply Vcc1. An NMOS N01, one end of which is the gate terminal of the first PMOS P1 and the other end of which is the input / output terminal 7
A second PMOS having a gate terminal connected to the first power supply Vcc1 and a substrate N well connected to the second power supply Vcc2.
P2, a second NMOS N02 having one end connected to the ground potential terminal and a gate terminal connected to the output terminal of the two-input NOR circuit 4 of the input / output control circuit 11, and one end connected to the input / output terminal 7 An end is connected to the other end of the second NMOS N02, and a gate terminal is connected to the first power supply Vcc1, and a third NMOS N03 is connected, and one end is connected to the input / output controller.
The other end is connected to the output terminal of the two-input NAND3 of the rule circuit 11, the gate terminal is connected to the gate terminal of the first PMOS P1, the gate terminal is connected to the input / output terminal 7, and the substrate N well is connected to the second power source Vcc2. It is composed of a third PMOS P3.

Further, the electrostatic breakdown protection element 12 is an anode.
Is connected to the input / output terminal 7 and the cathode is connected to the second power source Vcc2.
Connected to a first unidirectional conductive element (eg, diode
D) and a second unidirectional conductive element (for example, diode) D2 having an anode connected to the ground potential terminal and a cathode connected to the input / output terminal 7.

The input circuit 10 has one end connected to the input / output terminal 7 and the other end connected to an input terminal of an inverter composed of a PMOS P5 and an NMOS N05, and a gate terminal connected to the first power supply V1.
a fourth NMOS N04 connected to cc1, and
A fourth power source having one end connected to the first power source Vcc1 and the other end connected to the input terminal of the inverter, the gate terminal connected to the output terminal of the inverter, and the substrate N well connected to the first power source Vcc1.
Of the PMOS P4.

The type of each PMOS and NMOS is
There is an enhanced type.

The operation of the input / output buffer circuit according to the first embodiment will be described below.

First, the case where the input / output buffer circuit operates as an output buffer will be described.

First, when outputting the "H" level to the input / output terminal 7, the logic circuit section 200 shown in FIG. 1 sets the data signal D and the enable signal EN to the "H" level. As a result, the input / output control circuit 11 causes a 2-input N
The output terminals of AND3 and 2-input NOR4 become the GND level. Therefore, in the output circuit 13, the PMOSP1
Since the GND level is applied to the gate terminal of the NMOS N02 and the NMOS N02, the PMOS P1 is turned on and the NMOS N02 is turned on.
02 turns off. As a result, the input / output terminal 7 becomes "H" level. At this time, the PMOSs P2 and P3 are in an off state, and thus are irrelevant to the operation.

Next, when outputting the "L" level to the input / output terminal 7, the logic circuit section 200 outputs the data signal D to the "L" level.
Then, the enable signal EN is set to "H" level. As a result, the input / output control circuit 11
Output terminals of 2-input NAND3 and 2-input NOR4 are Vcc
1 level. Therefore, the PMOSP of the output circuit 13
"H" level is applied to the gate terminal of No. 1 and NMO
The Vcc1 level is applied to the gate terminal of SN02. As a result, the PMOS P1 turns off and the NMOS N
Since 02 is turned on, the input / output terminal 7 becomes "L" level. At the same time, the PMOS P3 is turned on, and the gate terminal of the PMOS P1 rises to the Vcc1 level.
OS P1 is completely off. Therefore, as in the conventional circuit shown above, the NMO is used to prevent the leak current.
To reduce the threshold voltage of S N01,
It is not necessary to devise a process such as increasing the absolute value of the threshold voltage of P1. At this time, the PMOS
P2 is in the off state and is irrelevant to operation.

Next, a case where the input / output buffer circuit operates as an input buffer will be described.

In this case, the logic circuit section 200 sets the enable signal EN to the "L" level. As a result, the input / output control circuit 11 sets the output terminal of the 2-input NAND3 to the Vcc1 level and the output terminal of the 2-input NOR4 to the GND level.

When the "L" level is input to the input / output terminal 7, in the output circuit 13, the gate terminal of the PMOS P1 becomes the Vcc1 level by the action of the PMOS P3, and the PMOS P1 is completely turned off. Also, NMOS
Since the gate terminal of N02 is at the GND level, the NMOS N02 is off. Therefore, the output of the output circuit 13 is in a high impedance state.

When the "H" level is input to the input / output terminal 7, the output circuit 13 changes the level to Vcc1.
PM exceeds + | Vtp | and the level turns on
It is transmitted to the gate terminal of PMOS P1 via OSP2. Here, Vtp is the threshold voltage of the PMOS P2. As a result, the PMOS P1 is completely turned off, and the power supply Vcc1 is supplied from the input / output terminal 7 via the PMOS P1.
The leak path to is cut off. At this time, the PMOS
The gate potential of P1 is the output potential V of the 2-input NAND3.
Although it is higher than cc1, there is no problem because it is separated by the NMOS N01. Also, NMOS N0
The gate potential of 2 is at the GND level, and the NMOS N0
2 is off. Therefore, the output is in the high impedance state. In addition, PMOS P1, P2, P
Since the N well, which is the substrate of No. 3, is connected to the power supply Vcc2, the drain and N well are not forward biased even if a signal having the same potential as the power supply Vcc2 is input to the input / output terminal 7, and the leak is prevented. No current flows.

On the other hand, in the input circuit 10, when the "H" level is input from the input / output terminal 7, the level of the input terminal of the inverter composed of the PMOS P5 and the NMOS N05 is Vcc1-Vtn4 by the NMOS N04.
Rise to. Here, Vtn4 is the threshold voltage of the NMOS N04. In response to this, the output terminal level of the inverter composed of the PMOS P5 and the NMOS N05 is lowered to "L" level, and the "H" level of the inverter 6 is reached.
The level output is transmitted inside the chip. At that time, PMO
PMOS P4 which receives the output terminal level of the inverter composed of SP5 and NMOS N05 at its gate terminal
The level of the input terminal of the inverter composed of PMOS P5 and NMOS N05 becomes Vcc1.
And PMOS P5 is completely turned off. Therefore, no leak current flows through the inverter composed of PMOS P5 and NMOS N05.

Next, when the "L" level is input from the input / output terminal 7, in the input circuit 10, the level of the input terminal of the inverter composed of the PMOS P5 and the NMOS N05 is changed to the GND level by the NMOS N04. become. In response to this, the output terminal level of the inverter composed of the PMOS P5 and the NMOS N05 becomes "H" level, and the "L" level output of the inverter 6 is transmitted inside the chip.

Incidentally, the diode of the protection element 12 for electrostatic breakdown is
Since the cathode of the terminal D1 is connected to the power source Vcc2,
Even if a signal having the same potential as the power supply Vcc2 is input to the input / output terminal 7, the diode D1 does not become conductive.

As described above, according to the input / output buffer circuit of the first embodiment, the power source voltage (Vcc1) higher than the power source voltage (Vcc1) of itself is added without increasing the number of process steps.
It is possible to obtain a CMOS type input / output buffer circuit that can perform input / output with a device that inputs / outputs a signal at the cc2) level.

A second embodiment of the input / output buffer circuit 100 will be described below.

The input / output buffer circuit according to the second embodiment is different from the input / output buffer circuit according to the first embodiment described above only in the input / output control circuit 11 and the output circuit 13, and therefore the other components are the same. The description of the part will be omitted, and only this part will be described.

FIG. 3 shows an extracted configuration of the input / output control circuit 11 and the output circuit 13 of the input / output buffer circuit according to the second embodiment.

As shown in the figure, in the second embodiment, the input / output control circuit 11 is composed of only the inverter 8 driven by the first power source Vcc1 which inverts the enable signal EN. . In addition, the output circuit 13 uses the first power source Vc.
a first PMOS P1 and a sixth PMOS P6, each of which has an N-type substrate well connected to the second power supply Vcc2 and is inserted between the c1 and the input / output terminal 7, and one end of which is the first PMOS P1.
A first NMOS N01 having the gate terminal of P1 connected at the other end to the output terminal of the inverter 8 and the gate terminal connected to the first power source Vcc1, respectively, and one end of the first PMOS N01.
A second PMOS P2 having the gate terminal of P1 connected at the other end to the input / output terminal 7, the gate terminal connected to the first power supply Vcc1, and the substrate N well connected to the second power supply Vcc2;
One end is the ground potential terminal and the gate terminal is the enable signal EN
A second NMOS N02 connected to the above, one end to the input / output terminal 7, the other end to the second NMOS N02, and a gate terminal to the gate terminal of the sixth PMOS P6 and a data signal D. A third NMOS N03 connected to each other, one end of which is the output terminal of the inverter 8 and the other end of which is the first PM.
The gate terminal of the OS P1 is composed of a gate terminal, the input / output terminal 7 is connected to the substrate N well, and the third PMOS P3 is connected to the second power source Vcc2.

The operation of the output circuit 13 according to the second embodiment will be described below.

First, the case where the input / output buffer circuit operates as an output buffer will be described.

When outputting the "H" level to the input / output terminal 7, the data signal D is set to the "L" level and the enable signal EN is set to the "H" level. As a result, PMOS P1
Since the GND level is applied to the gate terminal of the PMOS P6, the PMOS P1 and the PMOS P6 are turned on. Also, the NMOS N02 turns on, but the NMOS N0
3 turns off. As a result, the input / output terminal 7 becomes "H" level. Incidentally. At this time, the PMOSs P2 and P3 are turned off and have nothing to do with the operation.

On the other hand, when outputting "L" level to the input / output terminal 7, the data signal D is set to "H" level and the enable signal EN is set to "H" level. As a result, NMOS
Since the Vcc1 level is applied to the gate terminals of N02 and N03, the NMOS N02 and N03 are turned on.
Further, the PMOS P1 turns on, but the PMOS P6 turns off. As a result, the input / output terminal 7 becomes "L" level. At this time, the PMOS P2 is in the off state and has nothing to do with the operation.

Next, the case where the input / output buffer circuit operates as an input buffer will be described. At this time, rice
The bull signal EN is set to "L" level. As a result, the output terminal of the inverter 8 becomes Vcc1 level.

When the "L" level is input to the input / output terminal 7, the action of the PMOS P3 causes the PMOS P1 to operate.
Gate terminal becomes Vcc1 level, and PMOS P1
Turn off completely. Further, since the gate terminal of the NMOS N02 is at the GND level, the NMOS N02
Is off. Therefore, the output is in the high impedance state.

On the other hand, when the "H" level is input to the input / output terminal 7, when the level exceeds Vcc1 + │Vtp│, the level is turned on to the gate terminal of the PMOS P1 via the PMOS P2. It is transmitted. Where Vtp
Is the threshold voltage of PMOS P2. Therefore, P
MOS P1 is completely off. Therefore, the power supply Vcc1 is input from the input / output terminal 7 via the PMOSs P6 and P1.
The leak path to is cut off. At that time, PMOS P1
Gate potential becomes higher than the inverter output potential Vcc1, but there is no problem because it is separated by the NMOS N01. The gate potential of the NMOS N02 is G
At the ND level, the NMOS N02 is off.
Therefore, the output circuit is in a high impedance state.
Further, since the N well which is the substrate of the PMOSs P1, P2 and P3 is connected to the power supply Vcc2, even if a signal having the same potential as the power supply Vcc2 is input to the input / output terminal 7, the drain and N
Wells are not forward biased.

As described above, according to the second embodiment as well,
Power supply voltage (V
It is possible to provide a CMOS type input / output buffer circuit capable of inputting / outputting a signal to / from a device which inputs / outputs a signal at a power supply voltage (Vcc2) level higher than cc1).

The third embodiment of the input / output buffer circuit 100 will be described below.

The input / output buffer circuit according to the third embodiment also differs from the input / output buffer circuit according to the first embodiment described above only in the input / output control circuit 11 and the output circuit 13, and therefore the other parts are not included. The description of the part will be omitted, and only this part will be described.

FIG. 4 shows an extracted configuration of the input / output control circuit 11 and the output circuit 13 of the input / output buffer circuit according to the third embodiment.

As shown in the figure, in the third embodiment, the input / output control circuit 11 has an enable signal EN and a data signal EN.
It comprises a two-input NAND 9 which receives the input signal D and is driven by the first power supply Vcc1 and an inverter 8 which inverts the enable signal EN. The output circuit 13 is a first PMOS in which the N-type substrate well is inserted between the first power source Vcc1 and the input / output terminal 7 and connected to the second power source Vcc2.
P1 and a sixth PMOS P6, and one end of the first PMO
A first NMOS N01 having the other end connected to the gate terminal of SP1 and the output terminal of the inverter 8 connected to the first power source Vcc1 respectively, and one end of the first PM N01.
A second PMOS P2 in which the other end of the OS P1 is connected to the input / output terminal 7, the gate terminal is connected to the first power source Vcc1, and the substrate N well is connected to the second power source Vcc2.
A second NMOS N02 having one end connected to the ground potential terminal and a gate terminal connected to the enable signal EN, one end connected to the input / output terminal 7 and the other end connected to the other end of the second NMOS N02. -The output terminal of the 2-input NAND 9 and P terminal
The third N connected to the gate terminals of the MOS P6.
It is composed of a MOS N03.

The operation of the output circuit according to the third embodiment will be described below.

First, the case where the input / output buffer circuit operates as an output buffer will be described.

When outputting the "H" level to the input / output terminal 7, the data signal D and the enable signal EN are set to the "H" level. As a result, the output terminals of the inverter 8 and the 2-input NAND 9 become the GND level. Therefore, PMOS
GND is connected to the gate terminals of P1, P6 and NMOS N03.
Since the level is applied, the PMOSs P1 and P6 are turned on and the NMOS N03 is turned off. As a result, the input / output terminal 7 becomes "H" level. At this time, the PMOS P2 is in the off state and has nothing to do with the operation.

On the other hand, when outputting "L" level to the input / output terminal 7, the data signal D is set to "L" level and the enable signal EN is set to "H" level. As a result, 2 inputs N
The output terminal of AND9 becomes Vcc1 level. Therefore, the Vcc1 level is applied to the gate terminals of the PMOS P6, NMOS N02 and N03. As a result, P
Since the MOS P6 is turned off and the NMOSs N02 and N03 are turned on, the input / output terminal 7 becomes "L" level. PM
Since the OS P6 is completely turned off, the leak current does not need to be improved in the process such as decreasing the threshold voltage of the NMOS N01 or increasing the absolute value of the threshold voltage of the PMOS P1. Can be prevented. At this time, the PMOS P2 is in the off state and has nothing to do with the operation. Next, a case where the input / output buffer circuit operates as an input buffer will be described.

In this case, the enable signal EN is set to "L" level. As a result, the inverter 8 and the 2-input NAND
The output terminal of 9 becomes Vcc1 level.

When the "L" level is input to the input / output terminal 7, the gate terminal of the PMOS P6 is Vcc1.
Level, PMOS P6 is completely off.
Further, since the gate terminal of the NMOS N02 is at the GND level, the NMOS N02 is off. Therefore, the output circuit is in a high impedance state.

On the other hand, when the "H" level is input to the input / output terminal 7, when the level exceeds Vcc1 + | Vtp |, the level is turned on to the gate terminal of the PMOS P1 via the PMOS P2. It is transmitted. Where Vtp
Is the threshold voltage of PMOS P2. Therefore, P
MOS P1 is completely off. Therefore, the power supply Vcc1 is input from the input / output terminal 7 via the PMOSs P6 and P1.
The leak path to is cut off. At that time, PMOS P1
Gate potential becomes higher than the output potential Vcc1 of the inverter 8, but there is no problem because it is separated by the NMOS N01. The gate potential of the NMOS N02 is at the GND level, and the NMOS N02 is off. Therefore, the output circuit is in a high impedance state. In addition, N which is a substrate of the PMOSs P1, P2 and P6
Since the well is connected to the power source Vcc2, the drain and the N well are not forward biased even if a signal having the same potential as the power source Vcc2 is input to the input / output terminal 7.

As described above, according to the third embodiment as well, the power supply voltage (Vc) of itself is increased without increasing the number of process steps.
c1) Input / output can be performed with a device that inputs / outputs a signal at a power supply voltage (Vcc2) level higher than C1).
A MOS type input / output buffer circuit can be provided.

The fourth embodiment of the input / output buffer circuit 100 will be described below.

The fourth embodiment is a bi-CM in which a bipolar transistor and a MOS transistor are formed on the same substrate.
The present invention relates to an input / output buffer of an OS type semiconductor integrated circuit device. Further, unlike the first to third embodiments, only the Vcc1 is supplied as the power supply voltage to the input / output buffer circuit according to the fourth embodiment.

The input / output buffer circuit according to the fourth embodiment also differs from the input / output buffer circuit according to the first embodiment described above only in the output circuit 13. Therefore, description of the other parts will be omitted, and the description will be omitted. Only the part will be explained.

FIG. 5 shows an extracted configuration of the input / output control circuit 11 and the output circuit 13 of the input / output buffer circuit according to the fourth embodiment.

As shown in the figure, in the fourth embodiment, the input / output control circuit 11 is composed of a two-input NAND3, a two-input NOR4 and an inverter 5 driven by the first power supply Vcc1. The output circuit 13 includes an NPN bipolar transistor (hereinafter simply referred to as "NPN") Q1 inserted between the first power supply Vcc1 and the input / output terminal 7.
And one end to the first power supply Vcc1 and the other end to the NPN Q
A seventh PMO in which a gate terminal is connected to the first base terminal and a substrate N well is connected to the first power supply Vcc1 to the output terminal of the 2-input NAND3 of the input / output control circuit 11.
SP7 and a sixth NMOS N06 whose one end is connected to the base terminal of NPN Q1, the other end is connected to the ground potential terminal and the gate terminal is connected to the output terminal of the 2-input NAND3 of the input / output control circuit 11. And one end to the ground potential terminal and the gate terminal to the two-input N of the input / output control circuit 11.
The second NMOS N0 connected to the output terminal of the OR circuit 4
2 and one end to the input / output terminal 7 and the other end to the second NM
It is composed of an OS N02 and a third NMOS N03 whose gate terminals are connected to the first power supply Vcc1.

The operation of the input / output circuit according to the fourth embodiment will be described below.

First, the case where the input / output buffer circuit operates as an output buffer will be described.

When outputting the "H" level to the input / output terminal 7, the data signal D and the enable signal EN are set to the "H" level. As a result, the input / output control circuit 11 causes the output terminals of the 2-input NAND 3 and the 2-input NOR 4 to become G.
It becomes ND level. Therefore, PMOS P7 and NMO
Since the GND level is applied to the gate terminals of S N06 and N02, the PMOS P2 turns on and the NMOS N
06 turns off and NPN Q1 turns on. Also, NMOS
N02 turns off. As a result, the input / output terminal 7 is "H".
Become a level.

On the other hand, when outputting "L" level to the input / output terminal 7, the data signal D is set to "L" level and the enable signal EN is set to "H" level. As a result, the input / output control circuit 11 brings the output terminals of the 2-input NAND 3 and the 2-input NOR 4 to the Vcc1 level. Therefore, the gates of PMOS P7 and NMOS N06, N02
Since the Vcc1 level is applied to the
P7 turns off, NMOS N06 turns on, NPN
Q1 turns off. Further, the NMOS N02 is turned on.
As a result, the input / output terminal 7 becomes "L" level.

Next, the case where the input / output buffer circuit operates as an input buffer will be described.

In this case, the enable signal EN is set to "L".
To level. As a result, the input / output control circuit 11
Thus, the output terminal of the 2-input NAND3 becomes the Vcc1 level and the output terminal of the 2-input NOR4 becomes the GND level.

When the "L" level is input to the input / output terminal 7, the PM of the PM is generated by the operation of the 2-input NAND3.
The gate terminals of OS P7 and NMOS N06 are Vcc1
Level and NPN Q1 is completely off. Also,
Since the gate terminal of the NMOS N02 is at the GND level, the NMOS N02 is off. Therefore, the output of the output circuit 13 is in a high impedance state.

On the other hand, even when the "H" level is input to the input / output terminal 7, the base potential is the GND potential N.
PN Q1 is completely off. Also, NMOS N
The gate potential of 02 is GND level, and the NMOS N
02 is off. Therefore, the output of the output circuit 13 is in a high impedance state.

As described above, according to the fourth embodiment, N
By using a PN bipolar transistor,
A bipolar CMOS composite that can perform input / output with a device that inputs / outputs a signal at a power supply voltage (Vcc2) level higher than its own power supply voltage (Vcc1) without generating a negative current. Can be obtained. Further, when the N type is used as the semiconductor substrate, the N type substrate can be used as the collector, the P well can be the base, and the N diffusion layer region can be the emitter for forming the bipolar transistor. No need to increase.

The fifth embodiment of the input / output buffer circuit will be described below.

Also in the fifth embodiment, the bipolar CM in which the bipolar transistor and the MOS transistor are formed on the same substrate.
The present invention relates to an input / output buffer of an OS type semiconductor integrated circuit device, and is supplied with only Vcc1 as a power supply voltage.

The input / output buffer circuit according to the fifth embodiment also differs from the input / output buffer circuit according to the first embodiment described above only in the input / output control circuit 11 and the output circuit 13. Description of other parts will be omitted, and only this part will be described.

FIG. 6 shows an extracted configuration of the input / output control circuit 11 and the output circuit 13 of the input / output buffer circuit according to the fifth embodiment.

As shown in the figure, in the fifth embodiment, the input / output control circuit 11 is composed of only the inverter 8 driven by the first power source Vcc1 which inverts the enable signal EN. . In addition, the output circuit 13 uses the first power source Vc.
NPN Q1 inserted between c1 and the input / output terminal 7,
One end is connected to the first power supply Vcc1 and the other end is connected to the ninth PMOSP9.
, An eighth PMOS P8 having a gate terminal at one end thereof and an output terminal of the inverter 8 connected to the substrate N-well at the first power source Vcc1, respectively, and one end of the eighth PMOS P8.
The other end of the NPN Q1 is connected to the base terminal of the NPN Q1.
To the data signal D and the substrate N well to the first power source Vc.
A ninth PMOS P9 connected to each of c1, a second NMOS N02 having one end connected to the ground potential terminal and a gate terminal connected to the enable signal EN, one end to the input / output terminal 7 and the other end to the A third NMOS in which a gate terminal is connected to the second NMOS N02 and the data signal D, respectively.
N03, a seventh NMOS N07 having one end connected to the base terminal of the NPN Q1, the other end connected to a ground potential terminal and a gate terminal connected to the data signal D, and one end connected to the NN.
The base terminal of PN Q1 is composed of an eighth NMOS N08 having the other end connected to the ground potential terminal and the gate terminal connected to the output terminal of the inverter 8.

The operation of the output circuit according to the fifth embodiment will be described below.

First, the case where the input / output buffer circuit operates as an output buffer will be described.

First, when outputting "H" level to the input / output terminal 7, the data signal D is set to "L" level and the enable signal EN is set to "H" level. As a result, the PMOS
Since the GND level is applied to the gate terminals of P8 and P9 and the NMOSs N07 and N08, the PMOSs P8 and P9 are turned on and the NMOSs N07 and N08 are turned off. Accordingly, NPN Q1 turns on. Also,
The NMOS N02 is turned on, but the NMOS N03 is turned off. As a result, the input / output terminal 7 becomes "H" level.

Next, when outputting "L" level to the input / output terminal 7, the data signal D is set to "H" level and the enable signal EN is set to "H" level. As a result, NMOS
Since the Vcc1 level is applied to the gate terminals of N02 and N03, the NMOS N02 and N03 are turned on.
Further, the PMOS P8 is turned on, the PMOS P9 is turned off, and the NMOS N07 is turned on. Therefore, NP
N Q1 turns off. As a result, the input / output terminal 7 becomes "L" level.

Next, the case where the input / output buffer circuit operates as an input buffer will be described.

In this case, the enable signal EN is set to "L".
To level. As a result, PMOS P8 and NMOS N
08 gate terminal goes to Vcc1 level, NMOS
The gate terminal of N02 becomes GND level.

When the "L" level is input to the input / output terminal 7, the base potential of the NPN Q1 is at the GND level, so the NPN Q1 is completely off. Also, NM
Since the gate terminal of OSN02 is at the GND level, the NMOS N02 is off. Therefore, the output of the output circuit 13 is in a high impedance state.

On the other hand, when the "H" level is input to the input / output terminal 7, the NPN Q1 is completely off. The gate potential of the NMOS N02 is at the GND level, and the NMOS N02 is off. Therefore, the output of the output circuit 13 is in a high impedance state.

As described above, according to the fifth embodiment as well,
As in the fourth embodiment, by using the NPN bipolar transistor, it is possible to interface with a device that inputs / outputs a signal at a power supply voltage (Vcc2) level higher than its own power supply voltage (Vcc1). -A CMOS integrated input / output buffer circuit can be obtained and can be operated with a single power supply. At this time, when an N type is used as the semiconductor substrate, the N type substrate is used as the collector and the P well is used as the base for forming the bipolar transistor.
In addition, since the N diffusion layer region can be used as the emitter, it is not necessary to increase the number of process steps.

The sixth embodiment of the input / output buffer circuit will be described below.

Also in the sixth embodiment, the bipolar CM in which the bipolar transistor and the MOS transistor are formed on the same substrate.
The present invention relates to an input / output buffer of an OS type semiconductor integrated circuit device. However, Vcc1 and Vcc2 are supplied as power supply voltages to the input / output buffer circuit according to the sixth embodiment.

The input / output buffer circuit according to the sixth embodiment also differs from the input / output buffer circuit according to the first embodiment described above only in the input / output control circuit 11 and the output circuit 13. Description of other parts will be omitted, and only this part will be described.

FIG. 7 shows an extracted configuration of the input / output control circuit 11 and the output circuit 13 of the input / output buffer circuit according to the sixth embodiment.

As shown in the figure, in the sixth embodiment, the input / output circuit 11 is composed of only the inverter 8 driven by the first power supply Vcc1 which inverts the enable signal EN. Further, the output circuit 13 has an NPN Q1 inserted between the first power supply Vcc1 and the input / output terminal 7, and one end of which is the first
Power source Vcc1 and an eighth PMOS P8 whose substrate N well is connected to a second power source Vcc2, and one end of which is connected to the eighth P8.
The other end of the MOS P8 is connected to the other end of the NPN Q1 at the base terminal thereof, the gate terminal thereof at the data signal D, and the second substrate N well thereof.
Of the ninth PMOS P connected to the respective power supply Vcc2 of
9, a second NMOS N02 having one end connected to the ground potential terminal and a gate terminal connected to the enable signal EN, one end to the input / output terminal 7 and the other end to the second NMOS N02. A third N whose terminals are connected to the data signal D, respectively.
MOS N03, one end of which is connected to the gate terminal of the eighth PMOS P8 and the other end of which is connected to the output terminal of the inverter 8.
And a first NMOS N01 whose respective terminals are connected to the first power supply Vcc1 and one end of which is connected to the eighth PMOS P8.
Of the gate terminal to the input / output terminal 7, the gate terminal to the first power source Vcc1, the substrate N well to the second power source Vcc.
Second PMOS P2 connected to each of the two, one end to the output terminal of the inverter and the other end to the PMOS P8.
Of the gate terminal to the input / output terminal 7 of the substrate N
A third PMOS P3 having wells connected to the second power supply Vcc2, and a tenth NMOS N1 having one end connected to the ground potential terminal and the gate terminal connected to the enable signal EN.
0, one end is the base terminal of the NPN Q1 and the other end is the gate terminal of the other end of the tenth NMOS N10.
9th NMOS N09 connected to the respective signal D
And an eleventh NMOS N11 inserted between the base terminal and the emitter terminal of the NPN Q1 and having its gate terminal connected to the output terminal of the inverter 8, and between the base terminal and the emitter terminal of the NPN Q1. And a gate terminal connected to the enable signal EN and a substrate N well connected to the second power source Vcc2, respectively, and a tenth PMOS P10.

The operation of the output circuit 13 according to the sixth embodiment will be described below.

First, the case where the input / output buffer circuit operates as an output buffer will be described.

When outputting the "H" level to the input / output terminal 7, the data signal D is set to the "L" level and the enable signal EN is set to the "H" level. As a result, the output terminal of the inverter 8 becomes GND level. Therefore, PMOS
Since the GND level is applied to the gate terminals of P8, P9 and the NMOS N09, N11, the PMOS P8, P9
9 is turned on, and NMOS N09 and N11 are turned off. P
Since the Vcc1 level is applied to the gate terminal of the MOS P10, the PMOS P10 is turned off. This result NP
N Q1 turns on. Further, since the GND level is applied to the gate terminal of the NMOS N03, the NMOS N03 is
03 is off. Therefore, the input / output terminal 7 becomes "H" level. At this time, the PMOSs P2 and P3 are in the off state and have no relation to the operation.

On the other hand, when outputting the "L" level to the input / output terminal 7, the data signal D is set to the "H" level and the enable signal EN is set to the "H" level. As a result,
The output terminal of the switch 8 becomes the GND level. Therefore, PM
The Vcc1 level is applied to the gate terminals of the OS P9, the NMOS N09, and N10. As a result, PMOSP
9 is turned off, and NMOS N09 and N10 are turned on, so that NPN Q1 is turned off. Also, NMOS N0
Since the Vcc1 level is applied to the gate terminals of 2 and N03, the NMOS N02 and N03 are turned on. Therefore, the input / output terminal 7 becomes "L" level. At this time, PM
The OSs P2, P3, P10, and the NMOS N11 are in the off state and have nothing to do with the operation.

Next, the case where the input / output buffer circuit operates as an input buffer will be described.

In this case, the enable signal EN is set to "L".
To level. As a result, the output terminal of the inverter 8 is V
It becomes cc1 level.

When the "L" level is input to the input / output terminal 7, the action of the PMOS P3 causes the PMOS P8
Has its gate terminal at the Vcc1 level, and the PMOS P8
Is completely off. Also, the base of NPN Q1,
NMOS N11 and PMOS inserted between the emitters
Since P10 turns on and the base and the emitter are short-circuited, NPN Q1 turns off. Also, NMOS N0
Since the gate terminals of 2 and N10 are at the GND level, the NMOS N02 and N10 are off. Therefore, the output of the output circuit 13 is in a high impedance state.

On the other hand, when the "H" level is input to the input / output terminal 7, when the level exceeds Vcc1 + | Vtp |, the level is turned on to the gate terminal of the PMOS P8 via the PMOS P2. It is transmitted. Where Vtp
Is the threshold voltage of PMOS P2. Therefore, P
MOS P8 is completely off. Therefore, the input / output terminal 7
To PMOS P10, NMOS N11, PMOS
The leak path to the power supply Vcc1 is cut off via P9 and P8. At that time, the gate potential of the PMOS P8 becomes higher than the output potential Vcc1 of the inverter 8, but NMO
There is no problem because it is separated by S N01. The gate potentials of the NMOS N02 and N10 are at the GND level, and the NMOS N02 and N10 are off. In addition, NPN Q1 is off. Therefore, the output of the output circuit 13 is in a high impedance state. Further, since the N well which is the substrate of the PMOS P8, P2, P3, P9, P10 is connected to the power supply Vcc2, even if a signal having the same potential as the power supply Vcc2 is input to the input / output terminal 7, the drain and the N well are It is never forward biased.

As described above, according to the sixth embodiment, as in the fourth and fifth embodiments, by using the NPN bipolar transistor, the power supply voltage (Vcc1) of its own can be obtained.
It is possible to obtain a bipolar CMOS composite input / output buffer circuit capable of inputting / outputting a signal to / from a device which inputs / outputs a signal at a higher power supply voltage (Vcc2) level. Further, when an N type is used as the semiconductor substrate,
In forming the bipolar transistor, it is possible to use the N-type substrate as the collector, the P-well as the base, and the N-diffusion layer region as the emitter, so that it is not necessary to increase the number of process steps.

Further, according to the sixth embodiment, when the output of the output circuit 13 is set to the high impedance state,
Since a reverse bias is not applied between the base and the emitter of NPN Q1, the reverse breakdown voltage between the base and the emitter can be reduced.

The seventh embodiment of the input / output buffer circuit 100 will be described below.

Input / output buffer circuit 1 according to the seventh embodiment.
The power supply voltage Vcc2 is supplied to the output circuit 13 of 00. Further, unlike the first to sixth embodiments, the voltage Vcc2 is output as the "H" level.

The input / output buffer circuit according to the seventh embodiment also differs from the input / output buffer circuit according to the first embodiment shown above only in the input / output control circuit 11 and the output circuit 13, and therefore the other components are the same. The description of the part will be omitted, and only this part will be described.

FIG. 8 shows an extracted configuration of the input / output control circuit 11 and the output circuit 13 of the input / output buffer circuit according to the seventh embodiment.

As shown in the figure, in the seventh embodiment, the input / output control circuit 11 has a two-input NAND3, a two-input NOR4, an inverter 5 and two input terminals driven by the first power source Vcc1. It comprises an inverter 20 driven by a first power supply Vcc1 connected to the output terminal of the input NAND3. In addition, the output circuit 13 uses the second power source Vcc.
2 and the input / output terminal 7 and an N-type substrate well connected to the second power source Vcc2, the PMOS P20, one end of which is connected to the input / output terminal 7 and the other end of which is connected to the ground potential terminal and the gate terminal. An NMOS N20 connected to the output terminal of the 2-input NOR4 of the output control circuit 11, a resistor R1 having one end connected to the second power supply Vcc2 and the other end connected to the gate terminal of the PMOS P20, and one end connected to the PMOS It is composed of a gate terminal of P20, an NMOS N21 having the other end connected to the ground potential terminal and a gate terminal connected to the output terminal of the inverter 20.

Here, PMOS P20 and NMOS N
Reference numerals 20 and N21 are MOS transistors in which the gate oxide film is thicker than the MOS transistor used in the logic unit 200 so that it can be used under the second power supply Vcc2. FIG. 9 shows that the gate oxide film is thickened.

In the figure, 901 and 902 represent the gate oxide film, and the broken line in the figure shows the thickness of the conventional gate oxide film.

The operation of the output circuit 13 according to the seventh embodiment will be described below.

First, the case where input / output buffer circuit 100 operates as an output buffer will be described.

When outputting the "H" level to the input / output terminal 7, the data signal D and the enable signal EN are set to the "H" level. As a result, the input / output control circuit 11 causes the output terminals of the 2-input NAND 3 and the 2-input NOR 4 to become G.
It becomes ND level. Therefore, the NMOS N21 game
Vcc1 level is applied to the
1 is turned on, the potential of the gate terminal of the PMOS P20 is lowered, and the PMOS P20 is turned on. Also, NMOS
GND level is applied to the gate terminal of N20,
OS N20 is turned off. As a result, input / output terminal 7
H level.

Next, when outputting "L" level to the input / output terminal 7, the data signal D is set to "L" level and the enable signal EN is set to "H" level. As a result, the input / output control circuit 11 brings the output terminals of the 2-input NAND 3 and the 2-input NOR 4 to the Vcc1 level. Therefore, the GND level is applied to the gate terminal of the NMOS N21, the NMOS N21 turns off, and the PMOS P2
0 gate terminal potential becomes Vcc2 level, and PMO
SP20 is completely off. Further, the Vcc1 level is applied to the gate terminal of the NMOS N20,
N20 turns on. As a result, the input / output terminal 7 becomes "L" level. At this time, the potential of the gate terminal of PMOS P20 is set to Vcc2 level,
Since the 20 is completely turned off, the second power source Vcc2
There is no leak current flowing from I to I / O terminal 7 through PMOS P20.

Next, the case where the input / output buffer circuit 100 operates as an input buffer will be described.

In this case, the enable signal EN is set to "L" level. As a result, the input / output control circuit 11 sets the output terminal of the 2-input NAND3 to the Vcc1 level and the output terminal of the 2-input NOR4 to the GND level. Therefore, the gate terminal of NMOS N21 is GND.
It becomes the electric potential, the NMOS N21 turns off, and the PMOSP2
0 gate terminal potential becomes Vcc2 level, and PMO
SP20 is completely off. Also, NMOS N20
Since its gate terminal is at the GND potential, the NMOS N2
0 turns off. Therefore, the output of the output circuit 13 is in the high impedance state regardless of whether "H" level is input or "L" level is input from the input / output terminal 7.

As described above, according to the seventh embodiment, by introducing a MOS transistor having a large gate oxide film thickness as shown in FIG. 9, the power supply voltage (Vcc1) of its own can be obtained.
It is possible to input / output signals to / from a device that inputs / outputs signals at a higher power supply voltage (Vcc2) level.
A MOS input / output buffer circuit can be provided.

The eighth embodiment of the input / output buffer circuit will be described below.

Input / output buffer circuit 1 according to the eighth embodiment
The power supply voltage Vcc1 and the power supply voltage Vcc2 are supplied to the output circuit 13 of 00. Further, as in the case of the seventh embodiment, the voltage Vcc2 is output as the "H" level.

The input / output buffer circuit according to the eighth embodiment is also different from the input / output buffer circuit according to the first embodiment described above only in the input / output control circuit 11 and the output circuit 13, so that other The description of the part is omitted, and only this part will be described.

FIG. 10 shows the input / output control circuit 11 and the output circuit 13 of the input / output buffer circuit according to the eighth embodiment.
The structure of is extracted and shown.

As shown in the figure, in the eighth embodiment, the input / output control circuit 11 has a two-input NAND3, a two-input NOR4, an inverter 5 and two input terminals driven by the first power source Vcc1. It comprises an inverter 20 driven by a first power supply Vcc1 connected to the output terminal of the input NAND3. In addition, the output circuit 13 uses the second power source Vcc.
2 and the input / output terminal 7 and an N-type substrate well connected to the second power source Vcc2, the PMOS P20, one end of which is connected to the input / output terminal 7 and the other end of which is connected to the ground potential terminal and the gate terminal. The NMOS N20 connected to the output terminal of the two-input NOR4 of the output control circuit 11 and one end of the PMO
An NMOS N21 whose other end is connected to the ground potential terminal at the gate terminal of SP20, one end of which is a second power supply Vcc2 and the other end of which is a gate terminal of the PMOS P20 which is a substrate N well and a second power supply Vcc2. A PMOS P21 connected to
One end is the output terminal of the inverter 20 and the other end is the PMOS.
The gate terminals of the P21 and the NMOS N21 are connected to the first power supply Vcc1 and the gate terminal of the NMOS N22 is connected to the second power supply Vcc2 at one end and the PMOS P21 and NMOS N21 are connected to the gate terminals of the PMOS P21 and the NMOS N21. -To the above-mentioned PM
The gate terminal of the OS P20 is composed of a PMOS P22 in which the substrate N well is connected to the second power source Vcc2. Here, PMOS P20, P21, P22 and NM
OSs N20 and N21 are MOS transistors having a thick gate oxide film so that they can be used under the second power supply Vcc2.

The operation of the output circuit according to the eighth embodiment will be described below.

First, the case where the input / output buffer circuit operates as an output buffer will be described.

When outputting the "H" level to the input / output terminal 7, the data signal D and the enable signal EN are set to the "H" level. As a result, the input / output control circuit 11 causes the output terminals of the 2-input NAND 3 and the 2-input NOR 4 to become G.
It becomes ND level. Therefore, PMOS P21 and NM
To the input terminal of the inverter composed of OS N21, first, the level of Vcc1-Vtn is applied, and the NMOS
N21 is strongly turned on, and the potentials of the gate terminals of PMOS P20 and P22 are lowered. Where Vtn is NMOS
This is the threshold voltage of N22. And the PMOS P2
The input terminal of the inverter composed of 1 and the NMOS N21 is pulled up to the Vcc2 level by the PMOS P22. As a result, the PMOS P21 is completely turned off and the PMOS P20 is turned on. Also, NMOS
The GND level is applied to the gate terminal of N20,
The MOS N20 turns off. As a result, the input / output terminal 7
Becomes "H" level. In this operation, the PMOS
Since the input terminal of the inverter composed of P21 and NMOS N21 is at the Vcc2 level, the power from the Vcc2 power source to the PM
No leak current flows to the ground potential terminal via the OS P21 and the NMOS N21. In addition, PMOS P
The input terminal of the inverter composed of 21 and the NMOS N21 is at Vcc2 level and higher than the output terminal potential of the inverter 20, but since it is separated by the NMOS N22, there is no problem.

On the other hand, when outputting "L" level to the input / output terminal 7, the data signal D is set to "L" level and the enable signal EN is set to "H" level. As a result, the input / output control circuit 11 brings the output terminals of the 2-input NAND 3 and the 2-input NOR 4 to the Vcc1 level. Therefore, the GND level is applied to the input terminal of the inverter composed of the PMOS P21 and the NMOS N21, and PM
The potential of the gate terminal of OS P20 becomes Vcc2 level. As a result, PMOS P20 is completely turned off. Further, the Vcc1 level is applied to the gate terminal of the NMOS N20, and the NMOS N20 is turned on. As a result,
The input / output terminal 7 becomes "L" level. At this time, the PMOS
The potential of the gate terminal of P20 is set to Vcc2 level, and P
Since the MOSP20 is completely off, the second power source V
There is no leak current flowing from cc2 to the input / output terminal 7 via the PMOS P20.

Next, the case where the input / output buffer circuit operates as an input buffer will be described.

In this case, the enable signal EN is set to "L" level. As a result, the input / output control circuit 11 sets the output terminal of the 2-input NAND3 to the Vcc1 level and the output terminal of the 2-input NOR4 to the GND level. Therefore, the GND level is applied to the input terminal of the inverter composed of the PMOS P21 and the NMOS N21, and the potential of the gate terminal of the PMOS P20 becomes Vcc2.
Become a level. As a result, PMOS P20 is completely turned off. Also, the gate terminal of the NMOS N20 is GND
Since it is a potential, the NMOS N20 is also turned off. Therefore, even if "H" level is input from the input / output terminal 7,
Even if the L ″ level is input, the output of the output circuit 13 is in the high impedance state.

As described above, according to the eighth embodiment, by introducing a MOS transistor having a thick gate oxide film, a power supply voltage (Vcc1) higher than its own power supply voltage (Vcc1) is introduced.
2) CM that does not generate a leak current that can input / output signals to / from a device that inputs / outputs signals at level
An OS type input / output buffer circuit can be obtained.

The ninth embodiment of the input / output buffer circuit 100 will be described below.

Input / output buffer circuit 1 according to the ninth embodiment
00 output circuit 13 has power supply voltages Vcc1 and Vcc2.
Is supplied. Further, as in the case of the seventh embodiment, the voltage Vcc2 is output as the "H" level.

The input / output buffer circuit according to the ninth embodiment also differs from the input / output buffer circuit according to the first embodiment described above only in the output circuit 13. Therefore, the description of the other parts will be omitted. Only this part will be described.

FIG. 11 shows the input / output control circuit 11 and the output circuit 13 of the input / output buffer circuit according to the ninth embodiment.
The structure of is extracted and shown.

As shown in the figure, in the eighth embodiment, the input / output control circuit 11 is composed of a two-input NAND3, a two-input NOR4 and an inverter 5 driven by the first power supply Vcc1. Further, the output circuit 13 is a PMOS P20 in which the N-type substrate well is inserted between the second power source Vcc2 and the input / output terminal 7 and connected to the second power source Vcc2.
And one end of the input / output terminal 7 and the other end thereof to the ground potential terminal and the gate terminal to the two-input NOR of the input / output control circuit 11.
4, an NMOS N20 connected to the output terminal of No. 4, one end of which is an output terminal of the 2-input NAND3 of the input / output control circuit 11, and the other end of which is a gate terminal of the PMOS P20 and a first power source. NMOS N connected to Vcc1
22 and one end of the second power source Vcc2 and the other end of the PMO.
A PM having a gate terminal connected to the SP20, a gate terminal connected to the input / output terminal 7, and a substrate N well connected to the second power source Vcc2.
And OS P22. Where PMOS P
20, P22 and NMOS N20 are the second power source Vcc2
It is a MOS transistor in which the thickness of the gate oxide film is increased so that it can be used under.

The operation of the output circuit 13 according to the ninth embodiment will be described below.

First, the case where the input / output buffer circuit 100 operates as an output buffer will be described.

When outputting the "H" level to the input / output terminal 7, the data signal D and the enable signal EN are set to the "H" level. As a result, the input / output control circuit 11 causes the output terminals of the 2-input NAND 3 and the 2-input NOR 4 to become G.
It becomes ND level. Therefore, PMOS P20 and NM
The GND level is applied to the gate terminal of the OS N20, turning on the PMOS P20 and turning off the NMOS N20. As a result, the input / output terminal 7 becomes "H" level.

On the other hand, when outputting "L" level to the input / output terminal 7, the data signal D is set to "L" level and the enable signal EN is set to "H" level. As a result, the input / output control circuit 11 brings the output terminals of the 2-input NAND 3 and the 2-input NOR 4 to the Vcc1 level. Therefore, at the gate terminal of the PMOS P20, first, Vcc
A level of 1-Vtn is applied. Here, Vtn is the threshold voltage of the NMOS N22. NMOS N
Since 20 is turned on, the potentials of the input / output terminal 7 and the gate terminal of the PMOS P22 are lowered. And the PMOS P20
The gate terminal of is pulled up to the Vcc2 level by the PMOS P22. As a result, the PMOS P20
Turn off completely. As a result, the input / output terminal 7 becomes "L" level. At this time, the potential of the gate terminal of the PMOS P20 is set to the Vcc2 level and the PMOS P20 is completely turned off.
No leak current flows to the input / output terminal 7 via 20.

Next, the case where the input / output buffer circuit 100 operates as an input buffer will be described.

In this case, the enable signal EN is set to "L".
To level. As a result, the input / output control circuit 11
Thus, the output terminal of the 2-input NAND3 becomes the Vcc1 level and the output terminal of the 2-input NOR4 becomes the GND level. Therefore, first, a level of Vcc1-Vtn is applied to the gate terminal of the PMOS P20. Here, Vtn is the threshold voltage of the NMOS N22.
Since the gate terminal of the NMOS N20 is at the GND potential, the NMOS N20 is turned off.

When the "L" level is input from the input / output terminal 7, the PMOS P22 causes the PMOS
Since the gate terminal of P20 is pulled up to the Vcc2 level, the PMOS P20 is turned off. Also, NMOS
N20 is off. Therefore, the output of the output circuit 13 is in a high impedance state.

On the other hand, when the "H" level is input from the input / output terminal 7, the gate terminal of the PMOS P20 is pulled up to the Vcc2 level until the level becomes Vcc2- | Vtp |. PMOS P20 is off. When it exceeds it, the source and the drain of the PMOS P20 have the same potential of Vcc2, so that no leak current flows. Also, the NMOS N20 is off. Therefore, the output of the output circuit 13 becomes equivalent to the high impedance state. Here, Vtp is PMOS P
22 threshold voltage.

As described above, according to the ninth embodiment, by introducing a MOS transistor having a thick gate oxide film, a power supply voltage (Vcc1) higher than its own power supply voltage (Vcc1) is introduced.
2) A CM capable of inputting / outputting a signal to / from a device for inputting / outputting a signal at a level and in which no leak current is generated
An OS type input / output buffer circuit can be obtained.

In each of the above embodiments, the input circuit 10
Although the case where both the output circuit 13 and the output circuit 13 are provided has been described, in each embodiment, the input circuit 10 is omitted, and “
It may be used as a 3-state output buffer circuit that supports an H "level output state, an" L "level output state, and a high impedance state.

[0162]

As described above, according to the present invention, an input / output buffer circuit capable of inputting / outputting a signal to / from a device which inputs / outputs a signal at a power supply voltage level higher than its own power supply voltage. Therefore, it is possible to provide the input / output buffer circuit in which the leak current is eliminated without increasing the number of process steps.

Further, the input / output buffer circuit is capable of inputting / outputting a signal to / from a device which inputs / outputs a signal at a power supply voltage level higher than its own power supply voltage. It is possible to provide an input / output buffer circuit capable of eliminating the peak current.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of an input / output buffer circuit according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of an input / output buffer circuit according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of an input / output buffer circuit according to a third embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of an input / output buffer circuit according to a fourth embodiment of the present invention.

FIG. 6 is a circuit diagram showing a configuration of an input / output buffer circuit according to a fifth embodiment of the present invention.

FIG. 7 is a circuit diagram showing a configuration of an input / output buffer circuit according to a sixth embodiment of the present invention.

FIG. 8 is a circuit diagram showing a configuration of an input / output buffer circuit according to a seventh embodiment of the present invention.

FIG. 9 is an explanatory diagram showing the structure of a MOS transistor having a thick gate oxide film used in the input / output buffer circuit according to the seventh embodiment of the present invention.

FIG. 10 is a circuit diagram showing a configuration of an input / output buffer circuit according to an eighth embodiment of the present invention.

FIG. 11 is a circuit diagram showing a configuration of an input / output buffer circuit according to a ninth embodiment of the present invention.

FIG. 12 is a circuit diagram showing a configuration of an input / output buffer circuit according to a conventional technique.

[Explanation of symbols]

P1, P2, P3, P4 PMOS transistor P5, P20, P21 PMOS transistor N01, N02, N03, N04 NMOS transistor N05, N20, N21, N22 NMOS transistor D1, D2 Diode Q1 NPN transistor 10 Input circuit 11 Input / output controller 11 -Circuit 12 Electrostatic discharge protection element 13 Output circuit 100 Input / output buffer circuit 200 Logic circuit section 1000, 2000 Semiconductor integrated circuit device

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Reference number within the agency FI Technical indication location H01L 27/092 H03K 19/003 Z (72) Inventor Hideo Hara 5-chome, Kamimizumoto-cho, Kodaira-shi, Tokyo No. 20 No. 1 Hitachi Ltd. Semiconductor Design Development Center

Claims (14)

[Claims] 1. A first power supply, a second power supply having a voltage higher than the first power supply voltage, an external terminal, and a ground potential voltage only when a high-level signal is output to the external terminal. In some cases, the first node serves as the first power supply voltage, and in other cases, the first power supply voltage serves as the first power supply voltage only when a low-level signal is output to the external terminal. 2 node, wherein the source terminal and the drain terminal are respectively the ends of the MOS transistor, one end of which is connected to the first power supply and the other end of which is connected to the external terminal. A first substrate well of the mold connected to a second power source
And a first PMOS transistor having one end connected to the gate terminal of the first PMOS transistor, the other end connected to the external terminal, the gate terminal connected to the first power source, and an N-type substrate well A second PMOS transistor connected to a second power source, one end connected to the gate terminal of the first PMOS transistor, the other end connected to the first node, and a gate terminal Is connected to the external terminal, an N-type substrate well is connected to a second power supply, and a third PMOS transistor is connected, one end of which is connected to the gate terminal of the first PMOS transistor and the other end of which is connected to the first PMOS transistor. A first NMOS transistor connected to the first node and having its gate terminal connected to the first power supply; one end connected to ground potential; and the gate terminal connected to the second node.
A second NMOS transistor connected to the external terminal, and one end connected to the external terminal and the other end connected to the second NMO.
A third NMOS which is connected to one end of the S transistor which is not connected to the ground potential and whose gate terminal is connected to the first power supply.
An output buffer circuit having a transistor. 2. A first power supply, a second power supply having a voltage higher than the first power supply voltage, an external terminal, and a ground potential voltage only when outputting to the external terminal. First
To the external terminal and the second node to be the first power source voltage only when outputting to the external terminal and to the ground potential voltage otherwise. A third node serving as the ground potential voltage or the first power supply voltage according to the value of the signal to be output is provided, and when one of the source terminal and the drain terminal is the end of the MOS transistor, one end is A first PMOS transistor connected to a first power supply and an N-type substrate well connected to a second power supply; one end connected to the gate terminal of the first PMOS transistor and the other end connected to the outside A second PMOS transistor connected to a terminal, a gate terminal connected to a first power supply, and an N-type substrate well connected to a second power supply; and one end of which is a gate of the first PMOS transistor. Connected to the first terminal, and the other end is connected to the first node. A third PMOS transistor having a gate terminal connected to the external terminal and an N-type substrate well connected to a second power supply; and one end connected to a first power supply voltage of the first PMOS. A fourth terminal in which one end is not connected, the other terminal is connected to an external terminal, a gate terminal is connected to the third node, and an N-type substrate well is connected to a second power source. A PMOS transistor and a first terminal having one end connected to the gate terminal of the first PMOS transistor, the other end connected to the first node, and the gate terminal connected to a first power supply. An NMOS transistor, one end of which is connected to the ground potential, and a gate terminal of which is connected to the second node.
A second NMOS transistor connected to the external terminal, and one end connected to the external terminal and the other end connected to the second NMO.
A third transistor which is connected to one end of the S transistor which is not connected to the ground potential voltage and whose gate terminal is connected to the third node.
And an NMOS transistor of the output buffer circuit. 3. A first power supply, a second power supply having a voltage higher than the first power supply voltage, an external terminal, and a ground potential voltage only when outputting to the external terminal. First
A first node serving as a power supply voltage of the second terminal, and a second node serving as a first power supply voltage only when outputting to an external terminal and a ground potential voltage in other cases, and the external terminal. And a third node which becomes the ground potential voltage only when a high level signal is output to the other and becomes the first power supply voltage in other cases. The source terminal and the drain terminal are respectively provided with MOS transistors. A first PMOS transistor having one end connected to the first power source and an N-type substrate well connected to the second power source, and one end of the first PMOS transistor gate. A second PMOS transistor connected to the terminal, the other end connected to the external terminal, the gate terminal connected to the first power supply, and the N-type substrate well connected to the second power supply; Connect to the first power supply of the first PMOS transistor A third terminal in which one end is not connected, the other terminal is connected to an external terminal, a gate terminal is connected to the third node, and an N-type substrate well is connected to a second power source. A PMOS transistor and a first terminal having one end connected to the gate terminal of the first PMOS transistor, the other end connected to the first node, and the gate terminal connected to a first power supply. An NMOS transistor, a second NMOS transistor having one end connected to the ground potential and a gate terminal connected to the second node, one end of the second NMOS transistor and the other end of the second NMOS transistor A third NMOS which is connected to one end not connected to the ground potential and whose gate terminal is connected to the third node
An output buffer circuit having a transistor. 4. A first power supply, a second power supply having a voltage higher than the first power supply voltage, an external terminal, and a ground potential voltage only when a high-level signal is output to the external terminal. In some cases, a first node serving as the first power supply voltage,
A second node which becomes the first power supply voltage only when a low level signal is output to the external terminal and which becomes the ground potential voltage in other cases, and a source terminal and a drain terminal are respectively provided. If it is the end of a MOS transistor, an NPN bipolar transistor having a collector terminal connected to a first power supply and an emitter terminal connected to an external terminal, and one end connected to a first power supply and the other end connected to the NPN Bypo
A PMOS transistor connected to the base terminal of a transistor, a gate terminal connected to the first node, and an N-type substrate well connected to a first power source; and one end of the NPN bipolar transistor. A first NMOS transistor connected to the base terminal of the transistor, the other end of which is connected to the ground potential and the gate terminal of which is connected to the first node, and one end of which is connected to the ground potential, The gate terminal is connected to the second node.
A second NMOS transistor connected to the external terminal, and one end connected to the external terminal and the other end connected to the second NMO.
A third NMOS which is connected to one end of the S transistor which is not connected to the ground potential and whose gate terminal is connected to the first power supply.
An output buffer circuit having a transistor. 5. A first power supply, an external terminal, and a first node which becomes a ground potential voltage only when outputting to the external terminal and which becomes the first power supply voltage in other cases. The second node, which becomes the first power supply voltage only when outputting to the external terminal and becomes the ground potential voltage in other cases, and the ground potential voltage or the second node depending on the value of the signal output to the external terminal. When the source terminal and the drain terminal are respectively the ends of the MOS transistors, the collector terminal is connected to the first power source and the emitter terminal is external. An NPN bipolar transistor connected to a terminal, one end connected to a first power supply, a gate terminal connected to the first node, and an N-type substrate well connected to the first power supply. A first PMOS transistor, one end of which is the first PMOS transistor The transistor is connected to one end not connected to the first power source, the other end is connected to the base terminal of the NPN bipolar transistor, and the gate terminal is connected to the third node. A second PMOS transistor having an N-type substrate well connected to the first power source, one end connected to the base terminal of the NPN bipolar transistor, the other end connected to the ground potential, and a gate terminal A first NMOS transistor connected to the third node, one end connected to the ground potential, and a gate terminal connected to the second node.
A second NMOS transistor connected to the external terminal, and one end connected to the external terminal and the other end connected to the second NMO.
A third N-type transistor which is connected to one end of the S-transistor which is not connected to the ground potential and whose gate terminal is connected to the third node.
A MOS transistor and a fourth NMOS transistor having one end connected to the base terminal of the NPN bipolar transistor, the other end connected to ground potential, and the gate terminal connected to the first node. An output buffer circuit having: 6. A first power supply, a second power supply having a voltage higher than the first power supply voltage, an external terminal, and a ground potential voltage only when performing output to the external terminal, and in other cases, the above-mentioned First
To the external terminal and the second node to be the first power source voltage only when outputting to the external terminal and to the ground potential voltage otherwise. A third node which becomes the ground potential voltage or the first power supply voltage according to the value of the output signal, and the collector terminal when the source terminal and the drain terminal are respectively the ends of the MOS transistor. Connected to a first power supply, and an NPN bipolar transistor having an emitter terminal connected to an external terminal, and a first PMOS transistor having one end connected to the first power supply and an N-type substrate well connected to the second power supply. , One end is connected to the gate terminal of the first PMOS transistor, the other end is connected to the external terminal, the gate terminal is connected to the first power supply, and the N-type substrate well is connected to the second Second PMOS transistor connected to power supply An N-type substrate having one end connected to the gate terminal of the first PMOS transistor, the other end connected to the first node, and the gate terminal connected to the external terminal. A third PMOS transistor having a well connected to a second power supply, one end connected to one end of the first PMOS transistor not connected to the first power supply, and the other end connected to the base of the NPN bipolar transistor. A fourth PMOS transistor having a gate terminal connected to the third node, a gate terminal connected to the third node, and an N-type substrate well connected to a second power source; and one end of the NPN bipolar transistor. A fifth terminal connected to the base terminal of the transistor, one end connected to an external terminal, a gate terminal connected to the second node, and an N-type substrate well connected to a second power source. The PMOS transistor and one end of the first PMOS transistor A first NMOS transistor connected to the gate terminal of the data terminal, the other end of which is connected to the first node and the gate terminal of which is connected to the first power source, and one end of which is connected to the ground potential. A second NMOS transistor having a gate terminal connected to the second node, one end connected to the external terminal, and the other end connected to the second NMO.
A third NMO which is connected to one end of the S transistor which is not connected to the ground potential and whose gate terminal is connected to the third node.
S-transistor, one end of which is connected to the base terminal of the NPN transistor,
A fourth NMO in which the gate terminal is connected to the third node.
The S transistor and one end thereof are connected to the ground potential, the other end thereof is connected to one end of the fourth NMOS transistor which is not connected to the base terminal of the NPN transistor, and the gate terminal is connected to the second node. A fifth NMOS transistor connected to, and one end connected to the base terminal of the NPN transistor,
The other end is connected to the external terminal and the gate terminal is connected to the first node.
And a sixth NMOS transistor connected to the output buffer circuit. 7. A first power supply, a second power supply having a voltage higher than the first power supply voltage, an external terminal, and the first power supply voltage only when a high-level signal is output to the external terminal. And the first node which is otherwise the ground potential voltage,
A second node that becomes the first power supply voltage only when a low level signal is output to the external terminal and becomes a ground potential voltage in other cases, and a source terminal and a drain terminal are respectively provided with MOS transistors. , One end is connected to the second power supply, the other end is connected to the external terminal,
A PMOS transistor having an N-type substrate well connected to a second power source, one end connected to the external terminal, the other end connected to the ground potential, and a gate terminal connected to the second node. First N
A MOS transistor, a resistor having one end connected to the second power supply and the other end connected to the gate terminal of the PMOS transistor, and one end connected to the gate terminal of the PMOS transistor and the other end grounded. An output buffer circuit having a second NMOS transistor having a gate terminal connected to the first node. 8. A first power supply, a second power supply having a voltage higher than the first power supply voltage, an external terminal, and the first power supply voltage only when outputting a high-level signal to the external terminal. And the first node which is otherwise the ground potential voltage,
A second node that becomes the first power supply voltage only when a low level signal is output to the external terminal and becomes a ground potential voltage in other cases, and a source terminal and a drain terminal are respectively provided with MOS transistors. , One end is connected to the second power source and the other end is connected to the external terminal,
First PMO with N-type substrate well connected to second power supply
An S transistor, one end of which is connected to a second power supply and the other end of which is connected to the first PMOS
A second PMOS transistor connected to the gate terminal of the transistor and having an N-type substrate well connected to a second power supply; and one end connected to the second power supply and the other end connected to the second PM.
A third P transistor connected to the gate terminal of the OS transistor, the gate terminal connected to the gate terminal of the first PMOS transistor, and the N-type substrate well connected to the second power source.
A MOS transistor and a first N-type transistor having one end connected to the external terminal, the other end connected to ground potential, and the gate terminal connected to the second node.
A second N-channel transistor having a MOS transistor and one end connected to the gate terminal of the PMOS transistor, the other end connected to ground potential, and the gate terminal connected to the gate terminal of the second PMOS transistor.
A MOS transistor, one end of which is connected to the first node and the other end of which is connected to the second P node.
An output buffer circuit comprising: a third NMOS transistor connected to the gate terminal of a MOS transistor, the gate terminal of which is connected to the first power supply. 9. A first power source, a second power source having a voltage higher than the first power source voltage, an external terminal, and a ground potential voltage only when a high-level signal is output to the external terminal. In some cases, a first node serving as the first power supply voltage,
A second node that becomes the first power supply voltage only when a low level signal is output to the external terminal and becomes a ground potential voltage in other cases, and a source terminal and a drain terminal are respectively provided with MOS transistors. , One end is connected to the second power supply, the other end is connected to the external terminal,
First PMO with N-type substrate well connected to second power supply
An S transistor, one end of which is connected to the second power source and the other end of which is connected to the first PM
A second PMOS transistor connected to the gate terminal of the OS transistor, the gate terminal connected to the external terminal, and the N-type substrate well connected to the second power source; and one end connected to the external terminal And the other end is connected to the ground potential and the gate terminal is connected to the second node.
A MOS transistor, one end of which is connected to the first node and the other end of which is connected to the first P node.
An output buffer circuit comprising: a second NMOS transistor connected to the gate terminal of a MOS transistor, the gate terminal of which is connected to the first power supply. 10. Claims 1, 2, 3, 4, 5, 6, 7, 8
Or the output buffer circuit according to 9, further comprising an electrostatic discharge protection device connected to the external terminal, wherein the electrostatic discharge protection device has an anode connected to the external terminal and a cathode connected to the external terminal. It has a first unidirectional conductive element connected to a second power source and a second unidirectional conductive element having an anode connected to ground potential and a cathode connected to the external terminal. Output buffer circuit. 11. The output buffer circuit according to claim 1, 4, 7, 8 or 9, wherein an enable signal for controlling whether to output to said external terminal and said output signal to said external terminal. And a data signal for controlling the level of the signal to be input, and controlling the voltages of the first node and the second node in accordance with the input enable signal and data signal. An output buffer circuit further comprising: 12. The output buffer circuit according to claim 2, 3, 5 or 6, wherein an enable signal for controlling whether to output to the external terminal and a signal to be output to the external terminal. And a data signal for controlling the level of the first node, the voltage of the first node, the second node and the voltage of the third node are controlled in accordance with the input enable signal and data signal. An output buffer circuit further comprising an output control circuit. 13. A first power supply, an external terminal, an inverter composed of a PMOS transistor and an NMOS transistor driven by the first power supply, an NMOS transistor, and a PMOS transistor. -When the source terminal and the drain terminal are respectively the ends of the MOS transistor, the NMOS transistor has one end connected to the external terminal and the other end connected to the input terminal of the inverter,
A first terminal is connected to the first power source, one end of the PMOS transistor is connected to the first power source, the other end is connected to an input terminal of the inverter, and a gate terminal is connected to the gate terminal. An input buffer circuit connected to an output terminal of an inverter and an N-type substrate well connected to a first power supply. 14. Claims 1, 2, 3, 4, 5, 6, 7,
When the output buffer circuit according to 8, 9, 10, 11 or 12 and an input buffer circuit are provided, and the source terminal and the drain terminal are respectively ends of a MOS transistor, the input buffer circuit is the first An inverter composed of a PMOS transistor and an NMOS transistor driven by a power source, one end of which is connected to the external terminal, the other end of which is connected to the input terminal of the inverter, and the gate terminal of which is connected to the input terminal of the inverter. An NMOS transistor connected to a first power supply, one end connected to the first power supply, the other end connected to the input terminal of the inverter, and a gate terminal connected to the output terminal of the inverter. And a PMOS transistor having an N-type substrate well connected to the first power supply.