KR100511906B1 - Cmos inverter circuit with variable output signal transition level using floating gate transistor - Google Patents

Cmos inverter circuit with variable output signal transition level using floating gate transistor Download PDF

Info

Publication number
KR100511906B1
KR100511906B1 KR10-1999-0059671A KR19990059671A KR100511906B1 KR 100511906 B1 KR100511906 B1 KR 100511906B1 KR 19990059671 A KR19990059671 A KR 19990059671A KR 100511906 B1 KR100511906 B1 KR 100511906B1
Authority
KR
South Korea
Prior art keywords
floating gate
transistor
gate transistor
nmos
pmos
Prior art date
Application number
KR10-1999-0059671A
Other languages
Korean (ko)
Other versions
KR20010062920A (en
Inventor
김민규
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR10-1999-0059671A priority Critical patent/KR100511906B1/en
Publication of KR20010062920A publication Critical patent/KR20010062920A/en
Application granted granted Critical
Publication of KR100511906B1 publication Critical patent/KR100511906B1/en

Links

Classifications

    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175Coupling arrangements; Interface arrangements
    • H03K19/0185Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507Interface arrangements
    • H03K19/018521Interface arrangements of complementary type, e.g. CMOS
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008Arrangements for reducing power consumption
    • H03K19/0016Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inverter circuit in which a floating gate transistor is used in a CMOS inverter to adjust a transition level of an output signal to an input signal.
The CMOS inverter circuit of the present invention includes a CMOS inverter unit in which a PMOS floating gate transistor and an NMOS floating gate transistor are connected in a CMOS form, a first controller connected to the PMOS floating gate transistor to adjust a threshold voltage, and the NMOS floating gate transistor. It is connected to the second control unit for adjusting the threshold voltage.

Description

CMOS INVERTER CIRCUIT WITH VARIABLE OUTPUT SIGNAL TRANSITION LEVEL USING FLOATING GATE TRANSISTOR

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a CMOS inverter circuit, and more specifically, to a level of a transition level of an output voltage with respect to an input voltage by using a floating gate transistor (FGT). It relates to an inverter circuit.

CMOS transistors in which P-channel MOS transistors and N-channel MOS transistors are connected in series are inverter circuits that are fundamental in fields such as Very Large Scale Integration (VLSI). to be.

1 shows a circuit diagram of such a CMOS transistor. Referring to FIG. 1, a CMOS inverter has a gate terminal and a drain of a PMOS transistor P1 having a source voltage Vcc connected to a source terminal, and a NMOS transistor N1 having a ground power source connected to a source terminal. ) Terminals are connected to each other, and the input voltage Vin applied through the gate terminal is inverted and output to the output terminal Vout.

The waveform of the output voltage Vout according to the input voltage Vin of the CMOS inverter having the above structure is shown in FIG. 2. Referring to FIG. 2, when the input voltage Vin of the CMOS inverter is applied in a low state, the output voltage Vin is output in a high state, and when the input voltage Vin is applied in a high state, the output voltage Vout is applied. ) Is shown inverted to the low state.

However, in the case where the input voltage Vin is located in the middle of the transition from the low state to the high state, a section in which the output voltage also transitions from the high state to the low state appears. That is, the maximum allowable Logic-0 value (ViL) and the input voltage Vin are set to a high state to recognize the input voltage Vin as a low state and to generate a high output voltage Vout. The interval between the minimum allowable Logic-1 value (ViH) exists to generate a low output voltage.

The voltage change characteristic as shown in FIG. 2 is determined by the operation characteristics of the PMOS transistor P1, which is a pull-up transistor, and the NMOS transistor N1, which is a pull-down transistor. The input level Vin *, which is an intermediate value for the low level ViL and the high level ViH for this transition, is expressed by Equation 1 below.

In the above, Vtp and Vtn are threshold voltages of the PMOS transistor and the NMOS transistor, respectively. and Is expressed as

At this time, Wow Denotes the mobility of holes and electrons, and Tox denotes the gate oxide thickness of the transistor. Wn and Ln represent the width and length of the NMOS transistor, and Wp and Lp represent the width and length of the PMOS transistor, respectively. Denotes permittivity.

The input level Vin * expressed as described above needs to be moved to a high or low state according to the use of the semiconductor device. As shown in Equations 1 to 3, the semiconductor After the design of the device is over, the process can no longer be artificially changed.

Therefore, PMOS transistors or NMOS transistors having different sizes should be used according to the corresponding applications. If the input level is not suitable for the intended use or a defect occurs, a problem arises in that the design must be changed from the beginning.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a CMOS inverter circuit which can freely change an input level by using a floating gate transistor.

In order to achieve the above object, the CMOS inverter circuit of the present invention includes a CMOS inverter unit in which a PMOS transistor and an NMOS floating gate transistor are connected in a CMOS form, an input signal is applied to a gate terminal, and an output signal is generated from a drain terminal; And a control unit connected to the NMOS floating gate transistor to adjust a threshold voltage.

The controller may include an NMOS transistor having a drain terminal connected to a floating gate terminal of the NMOS floating gate transistor.

The controller controls the threshold voltage by turning on the NMOS transistor, applying a predetermined voltage to the floating gate terminal of the NMOS floating gate transistor through a source terminal, and then turning off the NMOS transistor.

In still another embodiment, a CMOS inverter circuit of the present invention includes a CMOS inverter unit in which a PMOS floating gate transistor and an NMOS transistor are connected in a CMOS form, an input signal is applied to a gate terminal, and an output signal is generated from a drain terminal. And a control unit connected to the PMOS floating gate transistor to adjust the threshold voltage.

The controller may include a PMOS transistor having a drain terminal connected to a floating gate terminal of the PMOS floating gate transistor.

The controller controls the threshold voltage by turning on the PMOS transistor, applying a predetermined voltage to the floating gate terminal of the PMOS floating gate transistor through a source terminal, and then turning off the PMOS transistor.

In still another embodiment of the present invention, the CMOS inverter circuit includes a CMOS inverter unit having a PMOS floating gate transistor and an NMOS floating gate transistor in a CMOS form, a first controller connected to the PMOS floating gate transistor to adjust a threshold voltage, and And a second controller connected to the NMOS floating gate transistor to adjust the threshold voltage.

The first controller may include a PMOS transistor having a drain terminal connected to a floating gate terminal of the PMOS floating gate transistor.

The first control unit turns on the PMOS transistor, applies a predetermined voltage to the floating gate terminal of the PMOS floating gate transistor through a source terminal, and then adjusts the threshold voltage by turning off the PMOS transistor. do.

The second controller may include an NMOS transistor having a drain terminal connected to a floating gate terminal of the NMOS floating gate transistor.

The second controller turns on the NMOS transistor, applies a predetermined voltage to the floating gate terminal of the NMOS floating gate transistor through a source terminal, and then adjusts the threshold voltage by turning off the NMOS transistor. .

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The CMOS inverter circuit of the present invention uses a threshold voltage adjustable PMOS floating gate transistor or NMOS floating gate transistor instead of the conventional PMOS transistor or NMOS transistor.

3A shows a cross-sectional view of an n-channel floating gate transistor. Referring to FIG. 3A, the NMOS floating gate transistor is formed of two gate terminals of which the gate electrode is made of metal. The floating gate 4 at the bottom is electrically isolated from other parts of the transistor, and the control gate (above the top) 5) performs the same operation as the gate terminal of the conventional MOS transistor. An oxide film 6 is formed around the floating gate 4 and the control gate 5.

A circuit diagram of the NMOS floating gate transistor is shown in FIG. 3B. Referring to FIG. 3B, it can be seen that the gate electrode is represented by two lines. The part connected to the gate terminal is the control gate C-G, and the part not connected to the other part in the middle is the floating gate.

4 illustrates the current-voltage characteristics according to the floating gate voltage in the floating gate transistor. Referring to FIG. 4, it can be seen that as the floating gate voltage is increased (Vfg1> Vfg2), the current-voltage curve shifts to the left, that is, the threshold voltage of the floating gate transistor decreases. As a result, the floating gate transistor can adjust the threshold voltage by adjusting the floating gate voltage, thereby making it possible to change the input level at which the transistor is turned on.

In the floating gate transistor, the floating gate voltage Vfg is expressed as follows.

g × Vg

In the above, Vfg (initial value) is a starting voltage given to the floating gate terminal, and Vg is a gate voltage, g is the ratio of the capacitance (Cipo) present between the floating gate and the control gate and the floating gate total capacitance (Ctotal), i.e. g = Cipo / Ctotal.

As a result, the floating gate voltage is changed as the initial voltage applied to the floating gate terminal is changed, and thus the threshold voltage is changed.

In other words, when the initial voltage of the floating gate is increased, the floating gate voltage is increased to lower the threshold voltage. When the initial voltage of the floating gate is lowered, the floating gate voltage is decreased and the threshold voltage is increased.

By changing the threshold voltage using the characteristics of the floating gate transistor as described above, a CMOS inverter circuit capable of adjusting the level at which the output signal transitions in accordance with the input signal is implemented.

5 shows a CMOS inverter circuit diagram according to an embodiment of the present invention. Referring to FIG. 5, the CMOS inverter circuit of the present invention includes a CMOS inverter unit 510 having a PMOS transistor P51 and an NMOS floating gate transistor NFGT connected in series to form a CMOS, and the NMOS floating gate transistor ( NFGT) is configured to control the threshold voltage.

The CMOS inverter unit 510 has the same configuration as a conventional CMOS inverter, and has a form in which an NMOS floating gate transistor NFGT is replaced with an NMOS transistor.

The controller 520 adjusts the threshold voltage by applying an initial voltage to the floating gate of the NMOS floating gate transistor NFGT. The controller 520 includes an NMOS transistor N51 having a drain terminal connected to the floating gate terminal.

In order to apply the initial voltage to the floating gate, a voltage (Vnfg + Vtn) higher than the threshold voltage Vtn is applied to the gate terminal Vng of the NMOS transistor N51 to turn on the NMOS transistor N51. In a state, a source voltage Vnref having a predetermined magnitude is applied to the source terminal to provide a voltage to the floating gate terminal. Thereafter, the gate voltage Vng is made low and the NMOS transistor N51 is turned off, thereby making the floating gate terminal floating.

Although the controller 520 is configured using an NMOS transistor, the semiconductor device may be implemented using another semiconductor device to apply a voltage to the floating gate.

After adjusting the threshold voltage of the NMOS floating gate transistor as described above, the waveform of the change in the output voltage with respect to the input voltage is shown in FIG. Also in this case, the high floating gate voltage Vfg1 and the low floating gate voltage Vfg2 are shown in the same manner as in the case of FIG.

Referring to FIG. 6, when the floating gate voltage of the NMOS floating gate transistor NFGT is increased, the threshold voltage at which the output signal transitions from the high state to the low state is reduced so as to be halfway between the low level ViL and the high level ViH. As the value of the input level Vin1 * decreases and, conversely, when the floating gate voltage is decreased, the threshold voltage increases and the input level Vin2 * increases relatively.

Therefore, even when all the manufacturing according to the design of the semiconductor device is finished, it is possible to change the threshold voltage by adjusting the voltage applied to the floating gate terminal of the NMOS floating gate transistor, and thus, the level at which the output signal transitions to the low state. Become.

Figure 7 shows a CMOS inverter circuit diagram according to another embodiment of the present invention. Referring to FIG. 7, the CMOS inverter circuit of the present invention includes a CMOS inverter unit 710 having a PMOS floating gate transistor PFGT and an NMOS transistor N71 connected in series to form a CMOS, and the PMOS floating gate transistor PFGT. Is connected to the control unit 720 to adjust the threshold voltage.

The CMOS inverter unit 710 has a structure in which a PMOS floating gate transistor PFGT is connected to a PMOS transistor instead of a PMOS transistor in a conventional CMOS inverter including a PMOS transistor and an NMOS transistor.

The controller 720 includes a PMOS transistor P71 having a drain terminal connected to a floating gate of the PMOS floating gate transistor PFGT to adjust the threshold voltage of the PMOS floating gate transistor PFGT.

In order to control the threshold voltage, the controller 720 first applies a voltage lower than the threshold voltage of the PMOS transistor P71 to the gate terminal Vpg to turn on the PMOS transistor P71 and to supply a predetermined voltage. The threshold voltage of the PMOS floating gate transistor PFGT may be adjusted by applying the terminal Vpref to the floating gate. Thereafter, the PMOS transistor P71 is turned off to bring the floating gate of the PMOS floating gate transistor PFGT into a floating state.

As in FIG. 5, the controller 720 is configured using the PMOS transistor P71, but a voltage may be applied to the floating gate of the PMOS floating transistor PFGT using another semiconductor device.

In the case of the CMOS inverter circuit having the above structure, as shown in FIG. 6, increasing the floating gate voltage of the PMOS floating gate transistor PFGT reduces the threshold voltage at which the output signal transitions from the low state to the high state. The input level can be made smaller and the threshold voltage can be increased by decreasing the floating gate voltage to increase the input level at which the output signal transitions.

8 shows a CMOS inverter circuit diagram according to another embodiment of the present invention. Referring to FIG. 8, the CMOS inverter circuit of the present invention includes a CMOS inverter unit 810 having a PMOS floating gate transistor (PFGT) and an NMOS floating gate transistor (NFGT) connected in series to form a CMOS, and the PMOS floating gate transistor. And a second controller 820 connected to the NMOS floating gate transistor and a second controller 830 connected to the NMOS floating gate transistor to adjust the threshold voltage.

The CMOS inverter unit 810 is connected to a PMOS floating gate transistor (PFGT) and an NMOS floating gate transistor (NFGT) in a CMOS inverter including a PMOS transistor and an NMOS transistor, respectively, instead of the PMOS transistor and the NMOS transistor.

The first control unit 820 includes a PMOS transistor P81 having a drain terminal connected to a floating gate terminal of the PMOS floating gate transistor PFGT. The configuration and operation of the first control unit 820 includes the configuration of the control unit 720 shown in FIG. Same operation.

The second control unit 830 includes an NMOS transistor N81 having a drain terminal connected to a floating gate terminal of the NMOS floating gate transistor NFGT. The configuration and operation of the second control unit 830 include the configuration of the control unit 520 shown in FIG. Same operation.

In the case of the CMOS inverter having the configuration as shown in FIG. 8, since the threshold voltages of the PMOS floating gate transistor PFGT and the NMOS floating gate transistor NFGT can be adjusted, the output signal Vout is in a high state from a low state. It is possible to adjust both the input level when transitioning to the low level and the input level when transitioning from the high state to the low state.

That is, by increasing or decreasing the threshold voltage of the PMOS floating gate transistor PFGT by the first controller 820, the input level when the output signal Vout transitions from a low state to a high state can be decreased or increased. By increasing or decreasing the threshold voltage of the NMOS floating gate transistor NFGT by using the second controller 830, the input level when the output signal Vout transitions from a high state to a low state may be decreased or increased. Can be.

As described in detail above, according to the CMOS inverter circuit of the present invention, by configuring the CMOS inverter circuit using a PMOS floating gate transistor or an NMOS floating gate transistor, the input level to which the output signal transitions is changed, and according to the intended use. The device can be configured.

In addition, the input level can be changed as described above even after the semiconductor device manufacturing process is completed, thereby ensuring sufficient margin for the semiconductor device design process, facilitating failure analysis due to errors in the manufacturing process, and designing according to the defect. By preventing the modification process in advance, there is an advantage that can increase the production yield as well as the economic cost.

Hereinafter, this invention can be implemented in various changes in the range which does not deviate from the summary.

1 is a conventional CMOS inverter circuit diagram;

2 is a waveform diagram of an output voltage with respect to an input voltage of a conventional CMOS inverter circuit;

3A is a cross-sectional view of a floating gate transistor,

3b is a circuit diagram of a floating gate transistor,

4 is a waveform diagram of variation in gate current-voltage of a floating gate transistor;

5 is a circuit diagram of a case where an NMOS floating gate transistor is used in a CMOS inverter circuit according to an embodiment of the present invention;

6 is a waveform diagram of an output voltage according to the input voltage of FIG. 5;

7 is a circuit diagram of a case where a PMOS floating gate transistor is used in a CMOS inverter circuit according to an embodiment of the present invention;

8 is a circuit diagram when a PMOS floating gate transistor and an NMOS floating gate transistor are used in a CMOS inverter circuit according to an embodiment of the present invention.

(Name of the code for the main part of the drawing)

510, 710, 810: CMOS inverter unit 520, 720, 820, 830: control unit

1: semiconductor substrate 2: drain region

3: source region 4: floating gate

5: control gate 6: oxide film

PFGT: PMOS Floating Gate Transistor

NFGT: NMOS Floating Gate Transistor]

P1, ..., P81: PMOS transistor

N1, ..., N81: NMOS transistor

Claims (11)

  1. A CMOS inverter unit in which a PMOS transistor and an NMOS floating gate transistor are connected in a CMOS form, an input signal is applied to a gate terminal, and an output signal is generated through a drain terminal;
    And a control unit connected to the NMOS floating gate transistor to adjust a threshold voltage.
  2. The method of claim 1, wherein the control unit
    And a drain terminal comprising an NMOS transistor connected to a floating gate terminal of the NMOS floating gate transistor.
  3. The method of claim 2, wherein the control unit
    Turn on the NMOS transistor,
    A predetermined voltage is applied to the floating gate terminal of the NMOS floating gate transistor through a source terminal,
    And then adjust the threshold voltage of the NMOS floating gate transistor by turning off the NMOS transistor.
  4. A CMOS inverter unit in which a PMOS floating gate transistor and an NMOS transistor are connected in a CMOS form, an input signal is applied to a gate terminal, and an output signal is generated from a drain terminal;
    And a control unit connected to the PMOS floating gate transistor to adjust a threshold voltage.
  5. The method of claim 4, wherein the control unit
    And a drain terminal comprising a PMOS transistor connected to a floating gate terminal of the PMOS floating gate transistor.
  6. The method of claim 5, wherein the control unit
    Turn on the PMOS transistor,
    Applying a predetermined voltage to a floating gate terminal of the PMOS floating gate transistor through a source terminal,
    Then turn off the PMOS transistor to adjust the threshold voltage of the PMOS floating gate transistor.
  7. A CMOS inverter unit in which a PMOS floating gate transistor and an NMOS floating gate transistor are connected in a CMOS form, an input signal is applied to a gate terminal, and an output signal is output through a drain terminal;
    A first controller connected to the PMOS floating gate transistor to adjust a threshold voltage;
    And a second controller connected to the NMOS floating gate transistor to adjust a threshold voltage.
  8. The method of claim 7, wherein the first control unit
    And a drain terminal comprising a PMOS transistor connected to a floating gate terminal of the PMOS floating gate transistor.
  9. The method of claim 8, wherein the first control unit
    Turn on the PMOS transistor,
    Applying a predetermined voltage to a floating gate terminal of the PMOS floating gate transistor through a source terminal,
    Thereafter, configured to adjust the threshold voltage of the PMOS floating gate transistor by turning off the PMOS transistor.
  10. The method of claim 7, wherein the second control unit
    And a drain terminal comprising an NMOS transistor connected to a floating gate terminal of the NMOS floating gate transistor.
  11. The method of claim 10, wherein the second control unit
    Turn on the NMOS transistor,
    A predetermined voltage is applied to the floating gate terminal of the NMOS floating gate transistor through a source terminal,
    Then turn off the NMOS transistor to adjust the threshold voltage of the NMOS floating gate transistor.
KR10-1999-0059671A 1999-12-21 1999-12-21 Cmos inverter circuit with variable output signal transition level using floating gate transistor KR100511906B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR10-1999-0059671A KR100511906B1 (en) 1999-12-21 1999-12-21 Cmos inverter circuit with variable output signal transition level using floating gate transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR10-1999-0059671A KR100511906B1 (en) 1999-12-21 1999-12-21 Cmos inverter circuit with variable output signal transition level using floating gate transistor

Publications (2)

Publication Number Publication Date
KR20010062920A KR20010062920A (en) 2001-07-09
KR100511906B1 true KR100511906B1 (en) 2005-09-02

Family

ID=19627510

Family Applications (1)

Application Number Title Priority Date Filing Date
KR10-1999-0059671A KR100511906B1 (en) 1999-12-21 1999-12-21 Cmos inverter circuit with variable output signal transition level using floating gate transistor

Country Status (1)

Country Link
KR (1) KR100511906B1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4010229B2 (en) * 2002-11-22 2007-11-21 ソニー株式会社 Bidirectional signal transmission circuit
US20120162121A1 (en) 2010-12-22 2012-06-28 Shih Chang Chang Slew rate and shunting control separation
US9319036B2 (en) 2011-05-20 2016-04-19 Apple Inc. Gate signal adjustment circuit

Also Published As

Publication number Publication date
KR20010062920A (en) 2001-07-09

Similar Documents

Publication Publication Date Title
US9013212B2 (en) Stress reduced cascoded CMOS output driver circuit
US7176740B2 (en) Level conversion circuit
EP0717334B1 (en) Circuit for providing a compensated bias voltage
US4959563A (en) Adjustable low noise output circuit
US7196547B2 (en) Level shifter and buffer circuit
US6455901B2 (en) Semiconductor integrated circuit
US7538597B2 (en) Fuse cell and method for programming the same
US6870413B1 (en) Schmitt trigger circuit with adjustable trip point voltages
JP4043683B2 (en) Integrated circuit design techniques for process tolerance
US7495471B2 (en) Adjustable transistor body bias circuitry
US6525574B1 (en) Gate bootstrapped CMOS sample-and-hold circuit
US6424206B2 (en) Input circuit and output circuit
US6674116B1 (en) Variable capacitor using MOS gated diode with multiple segments to limit DC current
US6980194B2 (en) Amplitude conversion circuit for converting signal amplitude
DE60127744T2 (en) Level conversion circuit and semiconductor device and display device containing this level conversion circuit
KR900003938B1 (en) Integrated circuit having fuse circuit
KR19980033134A (en) Semiconductor integrated circuit
US7468615B1 (en) Voltage level shifter
US8212545B2 (en) Reference voltage circuit and electronic device
JP4768300B2 (en) Voltage level conversion circuit and semiconductor integrated circuit device
US20030001554A1 (en) Internal power voltage generator
US6970037B2 (en) Programmable analog bias circuits using floating gate CMOS technology
US6664814B1 (en) Output driver for an integrated circuit
US7504862B2 (en) Level shifter translator
US20080204109A1 (en) High-performance level shifter

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20100726

Year of fee payment: 6

LAPS Lapse due to unpaid annual fee