CN105305989A - Rail-to-rail operational amplifier - Google Patents

Abstract

The invention relates to a rail-to-rail operational amplifier, comprising a rail-to-rail input stage circuit, an up current compensating circuit, a down current compensating circuit, an output stage circuit and a current mirror circuit, wherein the rail-to-rail input stage circuit is connected with the up current compensating circuit, the down current compensating circuit, the current mirror circuit and the output stage circuit; the current mirror circuit is also connected with the up current compensating circuit, the down current compensating circuit and the output stage circuit; the current mirror circuit provides a bias current; the rail-to-rail input stage circuit accesses a common mode level signal and outputs the common mode level signal to the output stage circuit; the output stage circuit is used for processing the common mode level signal to output an amplified signal; the up current compensating circuit and the down current compensating circuit are respectively used for compensating the working current of the rail-to-rail input stage circuit when the voltage of the common mode level signal goes up or down, so that the working current of the rail-to-rail input stage circuit keeps constant and the transconductance fluctuation of the rail-to-rail input stage circuit of the rail-to-rail operational amplifier is small.

Description

Rail-to-rail operational amplifier

Technical field

The present invention relates to circuit engineering field, particularly relate to a kind of rail-to-rail operational amplifier.

Background technology

Along with the reduction of ic manufacturing process characteristic size, its supply voltage used progressively declines, but device threshold voltage not corresponding reduction, therefore the common mode I/O increasing extent of operational amplifier is narrow, and general operational amplifier is difficult to satisfy the demands.

Rail-to-rail operational amplifier can realize, from power supply high potential to the input of the common mode of ground electronegative potential, output area, being applicable to the situation of low supply voltage.Rail-to-rail operational amplifier comprises input stage and output stage, traditional input stage circuit generally adopts MOSFET (Metal-Oxide-SemiconductorField-EffectTransistor mos field effect transistor, being called for short metal-oxide-semiconductor) the complementary differential input that forms to realize the rail-to-rail input of output stage, adopts 1:3 current mirror circuit, bulk driven circuit, floating gate circuits etc. to realize the mutual conductance of input stage constant to pipe; Traditional output-stage circuit adopts common source one-stage amplifier to realize the rail-to-rail output of output stage.But generally, the operating current of complementary differential to pipe is obtained by mirror image circuit, lower to the degree of control of electric current, the current copy precision of current mirror circuit is lower simultaneously, makes the mutual conductance change of input stage greatly.

Summary of the invention

Based on this, be necessary for the problems referred to above, provide a kind of mutual conductance to fluctuate little rail-to-rail operational amplifier.

A kind of rail-to-rail operational amplifier, comprise: rail-to-rail input stage circuit, ascending current compensating circuit, centrifugal current compensating circuit, output-stage circuit and current mirror circuit, described rail-to-rail input stage circuit connects described ascending current compensating circuit, described centrifugal current compensating circuit, described current mirror circuit and described output-stage circuit respectively, and described current mirror circuit also connects described ascending current compensating circuit, centrifugal current compensating circuit and output-stage circuit;

Described current mirror circuit provides bias current for described rail-to-rail input stage circuit, ascending current compensating circuit, centrifugal current compensating circuit and output-stage circuit, described rail-to-rail input stage circuit is for accessing common mode electrical level signal and exporting described output-stage circuit to, and described output-stage circuit is used for carrying out process to described common mode electrical level signal and exports amplifying signal; Described ascending current compensating circuit and described centrifugal current compensating circuit are respectively used to compensate the operating current of described rail-to-rail input stage circuit when the voltage of described common mode electrical level signal is up or voltage is descending, keep constant to make the operating current of described rail-to-rail input stage circuit.

Above-mentioned rail-to-rail operational amplifier, current mirror circuit is rail-to-rail input stage circuit, ascending current compensating circuit, centrifugal current compensating circuit and output-stage circuit provide bias current, rail-to-rail input stage circuit access common mode electrical level signal also exports output-stage circuit to, output-stage circuit carries out process to common mode electrical level signal and exports amplifying signal, meet the driving force to successive load, by ascending current compensating circuit and centrifugal current compensating circuit realize respectively the voltage of common mode electrical level signal up or voltage is descending time the operating current of rail-to-rail input stage circuit is compensated, the operating current of rail-to-rail input stage circuit is made to keep constant, thus the mutual conductance of the rail-to-rail input stage circuit of rail-to-rail operational amplifier fluctuation is little.

Accompanying drawing explanation

Fig. 1 is existing input stage circuit figure;

Fig. 2 is the circuit diagram of existing operational amplifier;

Fig. 3 is the circuit module figure of the rail-to-rail operational amplifier of the present invention in an embodiment;

Fig. 4 is the physical circuit figure of the rail-to-rail operational amplifier of the present invention in an embodiment;

Fig. 5 is the circuit module figure of the rail-to-rail operational amplifier of the present invention in another embodiment.

Embodiment

With reference to figure 1, it is the existing rail-to-rail input stage circuit structure chart be operated under sub-threshold status.Under sub-threshold status, the mutual conductance of metal-oxide-semiconductor is directly proportional with its electric current, when the voltage inputting common mode electrical level signal be up to PMOS complementary differential pipe is quit work time, current compensation circuit is started working, and the operating current keeping input stage circuit total is constant, thus the mutual conductance fluctuation reducing input stage circuit is little.When the voltage inputting common mode electrical level signal go downwards to NMOS complementary differential pipe is quit work time, the up similar process of voltage of its operation principle and common mode level signal.In this input stage circuit, the accuracy of repetition of current mirror circuit to electric current is lower, particularly to the metal-oxide-semiconductor of narrow channel length, because channel-length modulation impact is larger, the replica current of current mirror circuit is subject to the impact of metal-oxide-semiconductor drain voltage especially obviously, seriously reduces the accuracy of repetition of current mirror.Meanwhile, the operating current of complementary differential to pipe is obtained by current mirror circuit, and it is lower to the control of electric current, and mutual conductance change very greatly.

With reference to figure 2, in existing a kind of operational amplifier, add current comparison circuit.This circuit is by connecting component unit gain amplifier as the buffer stage of circuit or output-stage circuit using the inverting input in-of output output and operational amplifier.The shortcoming of this circuit is mainly manifested in the following aspects: one, input stage circuit cannot realize the rail-to-rail input of common mode electrical level signal; Two, along with the reduction of channel length, electric current cannot accurately copy, and current comparison circuit control precision is lower; Three, owing to adopting the differential amplifier of five pipes, this output stage open-loop gain is lower.

The invention provides a kind of rail-to-rail operational amplifier, the mutual conductance fluctuation of rail-to-rail input stage circuit can be reduced significantly, improve the stability of system works.

With reference to figure 3, rail-to-rail operational amplifier in one embodiment, comprise: rail-to-rail input stage circuit 110, ascending current compensating circuit 120, centrifugal current compensating circuit 130, current mirror circuit 140 and output-stage circuit 150, rail-to-rail input stage circuit 110 connects ascending current compensating circuit 120, centrifugal current compensating circuit 130, current mirror circuit 140 and output-stage circuit 150 respectively, and current mirror circuit 140 also connects ascending current compensating circuit 120, centrifugal current compensating circuit 130 and output-stage circuit 150.

Current mirror circuit 140 provides bias current for rail-to-rail input stage circuit 110, ascending current compensating circuit 120, centrifugal current compensating circuit 130 and output-stage circuit 150, rail-to-rail input stage circuit 110 is for accessing common mode electrical level signal and exporting output-stage circuit 150 to, and output-stage circuit 150 exports amplifying signal for carrying out process to common mode electrical level signal; Ascending current compensating circuit 120 and centrifugal current compensating circuit 130 are respectively used to compensate the operating current of rail-to-rail input stage circuit 110 when the voltage of common mode electrical level signal is up or voltage is descending, keep constant to make the operating current of rail-to-rail input stage circuit 110.In the present embodiment, under 3.3V supply voltage, when the common mode electrical level signal inputted rises to 3.3V from 0V, the mutual conductance fluctuation of rail-to-rail operational amplifier is less than 2.5%.

Above-mentioned rail-to-rail operational amplifier, current mirror circuit 140 is rail-to-rail input stage circuit 110, ascending current compensating circuit 120, centrifugal current compensating circuit 130 and output-stage circuit 150 provide bias current, rail-to-rail input stage circuit 110 accesses common mode electrical level signal and exports output-stage circuit 150 to, output-stage circuit 150 pairs of common mode electrical level signals carry out process and export amplifying signal, meet the driving force to successive load, by ascending current compensating circuit 120 and centrifugal current compensating circuit 130 realize respectively the voltage of common mode electrical level signal up or voltage is descending time the operating current of rail-to-rail input stage circuit 110 is compensated, the operating current of rail-to-rail input stage circuit 110 is made to keep constant, thus the mutual conductance of the rail-to-rail input stage circuit 110 of rail-to-rail operational amplifier fluctuation is little.

Wherein in an embodiment, with reference to figure 4, rail-to-rail input stage circuit 110 comprises PMOS complementary differential to pipe 111, NMOS complementary differential to pipe 112 and cascodes circuit 113, PMOS complementary differential is respectively connected cascodes circuit 113, ascending current compensating circuit 120, centrifugal current compensating circuit 130 and current mirror circuit 140 with NMOS complementary differential to pipe 112 to pipe 111, and cascodes circuit 113 connects output-stage circuit 150.

Cascodes circuit 113 1 aspect in rail-to-rail input stage circuit 110 is the gain that can improve output-stage circuit 150, also can convert the output signal of rail-to-rail input stage circuit 110 to Single-end output on the other hand; Simultaneously, the output of the higher gain of cascodes circuit 113 self forms the two poles of the earth amplifier with the output-stage circuit 150 be connected, the overall gain of rail-to-rail operational amplifier equals the gain of cascodes circuit 113 and the gain sum of output-stage circuit 150, thus improves the gain of rail-to-rail operational amplifier.In the present embodiment, adopt cascodes circuit 113 that the gain of rail-to-rail operational amplifier can be made to reach 120dB.

Wherein in an embodiment, comprise the first metal-oxide-semiconductor M1 and the second metal-oxide-semiconductor M2 with reference to figure 4, PMOS complementary differential to pipe 111, NMOS complementary differential comprises the 3rd metal-oxide-semiconductor M3 and the 4th metal-oxide-semiconductor M4 to pipe 112.First metal-oxide-semiconductor M1 and the second metal-oxide-semiconductor M2 is PMOS, and the 3rd metal-oxide-semiconductor M3 and the 4th metal-oxide-semiconductor M4 is PMOS.Cascodes circuit 113 comprises the 5th metal-oxide-semiconductor M5, the 6th metal-oxide-semiconductor M6, the 7th metal-oxide-semiconductor M7, the 8th metal-oxide-semiconductor M8, the 9th metal-oxide-semiconductor M9, the tenth metal-oxide-semiconductor M10, the 11 metal-oxide-semiconductor M11 and the 12 metal-oxide-semiconductor M12.Particularly, in the present embodiment, the 5th metal-oxide-semiconductor M5, the 6th metal-oxide-semiconductor M6, the 7th metal-oxide-semiconductor M7 and the 8th metal-oxide-semiconductor M8 are PMOS, and the 9th metal-oxide-semiconductor M9, the tenth metal-oxide-semiconductor M10, the 11 metal-oxide-semiconductor M11 and the 12 metal-oxide-semiconductor M12 are NMOS tube.Wherein, the first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2, the 3rd metal-oxide-semiconductor M3 and the 4th metal-oxide-semiconductor M4 are all operated in sub-threshold region.

The source electrode of the first metal-oxide-semiconductor M1 is connected with the source electrode of the second metal-oxide-semiconductor M2, and common port connects ascending current compensating circuit 120, centrifugal current compensating circuit 130 and current mirror circuit 140 respectively; The source electrode of the 3rd metal-oxide-semiconductor M3 is connected with the source electrode of the 4th metal-oxide-semiconductor M4, and common port connects ascending current compensating circuit 120, centrifugal current compensating circuit 130 and current mirror circuit 140 respectively, the grid of the first metal-oxide-semiconductor M1 is connected with the grid of the 3rd metal-oxide-semiconductor M3 and forms the inverting input Vin-of rail-to-rail operational amplifier, and the grid of the second metal-oxide-semiconductor M2 is connected with the grid of the 4th metal-oxide-semiconductor M4 and forms the in-phase input end Vin+ of rail-to-rail operational amplifier.

The grid of the 5th metal-oxide-semiconductor M5 is connected with the grid of the 6th metal-oxide-semiconductor M6, the grid of the 7th metal-oxide-semiconductor M7 is connected with the grid of the 8th metal-oxide-semiconductor M8, the drain electrode of the 5th metal-oxide-semiconductor M5 is connected with the source electrode of the 7th metal-oxide-semiconductor M7, and common port connects the drain electrode of the 3rd metal-oxide-semiconductor M3, the source electrode of the 5th metal-oxide-semiconductor M5 connects power end VDD, the drain electrode of the 6th metal-oxide-semiconductor M6 is connected with the source electrode of the 8th metal-oxide-semiconductor M8, and common port connects the drain electrode of the 4th metal-oxide-semiconductor M4, and the source electrode of the 6th metal-oxide-semiconductor M6 connects power end VDD.

The grid of the 9th metal-oxide-semiconductor M9 is connected with the grid of the tenth metal-oxide-semiconductor M10, the grid of the 11 metal-oxide-semiconductor M11 is connected with the grid of the 12 metal-oxide-semiconductor M12, the source electrode of the 9th metal-oxide-semiconductor M9 is connected with the drain electrode of the 11 metal-oxide-semiconductor M11, and common port connects the drain electrode of the first metal-oxide-semiconductor M1, the source electrode of the tenth metal-oxide-semiconductor M10 is connected with the drain electrode of the 12 metal-oxide-semiconductor M12, and common port connects the drain electrode of the second metal-oxide-semiconductor M2, the source electrode of the 11 metal-oxide-semiconductor M11 and the source ground of the 12 metal-oxide-semiconductor M12.The drain electrode of the 7th metal-oxide-semiconductor M7 is connected with the drain electrode of the 9th metal-oxide-semiconductor M9, and the common port that the grid that common port connects the 5th metal-oxide-semiconductor M5 is respectively connected with the grid of the 6th metal-oxide-semiconductor M6, and the common port that the grid of the 11 metal-oxide-semiconductor M11 is connected with the grid of the 12 metal-oxide-semiconductor M12.The drain electrode of the 8th metal-oxide-semiconductor M8 is connected with the drain electrode of the tenth metal-oxide-semiconductor M10, and common port connects output-stage circuit 150.

Wherein in an embodiment, ascending current compensating circuit 120 comprises the 13 metal-oxide-semiconductor M38, the 14 metal-oxide-semiconductor M39, the 15 metal-oxide-semiconductor M40, the 16 metal-oxide-semiconductor M41 and the 17 metal-oxide-semiconductor M42.Particularly, in the present embodiment, the 13 metal-oxide-semiconductor M38 is PMOS, and the 14 metal-oxide-semiconductor M39, the 15 metal-oxide-semiconductor M40, the 16 metal-oxide-semiconductor M41 and the 17 metal-oxide-semiconductor M42 are NMOS tube.

The source electrode of the 13 metal-oxide-semiconductor M38 connects rail-to-rail input stage circuit 110, in the present embodiment, is specially the source electrode of connection first metal-oxide-semiconductor M1 and the source electrode of the second metal-oxide-semiconductor M2, the external first bias voltage Vb1 of grid of the 13 metal-oxide-semiconductor M38.The drain electrode of the 14 metal-oxide-semiconductor M39 connects the drain electrode of the 13 metal-oxide-semiconductor M38, the grid of the 14 metal-oxide-semiconductor M39 is connected with the grid of the 16 metal-oxide-semiconductor M41, and the common port that the drain electrode that common port connects the 13 metal-oxide-semiconductor M38 is connected with the drain electrode of the 14 metal-oxide-semiconductor M39, the source electrode of the 14 metal-oxide-semiconductor M39 connects the drain electrode of the 15 metal-oxide-semiconductor M40.The source electrode of the 16 metal-oxide-semiconductor M41 connects the drain electrode of the 17 metal-oxide-semiconductor M42, the grid of the 15 metal-oxide-semiconductor M40 is connected with the grid of the 17 metal-oxide-semiconductor M42, and the common port that the source electrode that common port connects the 14 metal-oxide-semiconductor M39 is connected with the drain electrode of the 15 metal-oxide-semiconductor M40.The drain electrode of the 16 metal-oxide-semiconductor M41 connects rail-to-rail input stage circuit 110, in the present embodiment, is specially the source electrode of connection the 3rd metal-oxide-semiconductor M3 and the source electrode of the 4th metal-oxide-semiconductor, the source electrode of the 15 metal-oxide-semiconductor M40 and the source grounding GND of the 17 metal-oxide-semiconductor M42.

Centrifugal current compensating circuit 130 comprises the 18 metal-oxide-semiconductor M43, the 19 metal-oxide-semiconductor M44, the 20 metal-oxide-semiconductor M45, the 21 metal-oxide-semiconductor M46 and the 22 metal-oxide-semiconductor M47.Wherein, the 18 metal-oxide-semiconductor M43, the 19 metal-oxide-semiconductor M44, the 20 metal-oxide-semiconductor M45 and the 21 metal-oxide-semiconductor M46 are PMOS, and the 22 metal-oxide-semiconductor M47 is NMOS tube.

The source electrode of the 18 metal-oxide-semiconductor M43 is all connected power end VDD with the source electrode of the 20 metal-oxide-semiconductor M45, the drain electrode of the 18 metal-oxide-semiconductor M43 connects the source electrode of the 19 metal-oxide-semiconductor M44, the drain electrode of the 19 metal-oxide-semiconductor M44 connects rail-to-rail input stage circuit 110, in the present embodiment, be specially the source electrode of connection first metal-oxide-semiconductor M1 and the source electrode of the second metal-oxide-semiconductor M2.The drain electrode of the 20 metal-oxide-semiconductor M45 connects the source electrode of the 21 metal-oxide-semiconductor M46, and the drain electrode of the 21 metal-oxide-semiconductor M46 connects the drain electrode of the 22 metal-oxide-semiconductor M47.The grid of the 18 metal-oxide-semiconductor M43 connects the grid of the 20 metal-oxide-semiconductor M45, and the common port that the drain electrode that common port connects the 20 metal-oxide-semiconductor M45 is connected with the source electrode of the 21 metal-oxide-semiconductor M46, the grid of the 19 metal-oxide-semiconductor M44 connects the grid of the 21 metal-oxide-semiconductor M46, and the common port that the drain electrode that common port connects the 21 metal-oxide-semiconductor M46 is connected with the drain electrode of the 22 metal-oxide-semiconductor M47.The source electrode of the 22 metal-oxide-semiconductor M47 connects rail-to-rail input stage circuit 110, in the present embodiment, is specially the source electrode of connection the 3rd metal-oxide-semiconductor M3 and the source electrode of the 4th metal-oxide-semiconductor M4, the external second bias voltage Vb2 of grid of the 22 metal-oxide-semiconductor M47.

Wherein, the 14 metal-oxide-semiconductor M39 and the 15 metal-oxide-semiconductor M40 and the 16 metal-oxide-semiconductor M41 and the 17 metal-oxide-semiconductor M42 forms 1:1 current-mirror structure.18 metal-oxide-semiconductor M43 and the 19 metal-oxide-semiconductor M44 and the 20 metal-oxide-semiconductor M45 and the 21 metal-oxide-semiconductor M46 forms 1:1 current-mirror structure.The effect of ascending current compensating circuit 120 be when the voltage of the common mode electrical level signal of input in rail-to-rail input stage circuit 110 go upward to PMOS complementary differential pipe 111 is quit work time, the operating current 1:1 provided by current mirror circuit 140 copies to NMOS complementary differential in pipe 112, keeps the total working current constant of rail-to-rail input stage circuit 110.The effect of centrifugal current compensating circuit 130 be when the voltage of the common mode electrical level signal that rail-to-rail input stage circuit 110 inputs come downwards to NMOS complementary differential pipe 112 is quit work time, the operating current 1:1 provided by current mirror circuit 140 copies as PMOS complementary differential in pipe 111, keep the total working current constant of rail-to-rail input stage circuit 110, have low in energy consumption, output ripple is little, conversion speed is than the advantage such as very fast.

13 metal-oxide-semiconductor M38 and the 22 metal-oxide-semiconductor M47 is all for regulating transfer point: the voltage regulating the 13 metal-oxide-semiconductor M38 by the first bias voltage Vb1, can change the opening point of the current-mirror structure that the 14 metal-oxide-semiconductor M39 and the 15 metal-oxide-semiconductor M40 and the 16 metal-oxide-semiconductor M41 and the 17 metal-oxide-semiconductor M42 forms; The voltage of the 22 metal-oxide-semiconductor M47 is regulated by the second bias voltage Vb2, the opening point that the 18 metal-oxide-semiconductor M43 and the 19 metal-oxide-semiconductor M44 and the 20 metal-oxide-semiconductor M45 and the 21 metal-oxide-semiconductor M46 forms current-mirror structure can be changed, thus determine that PMOS complementary differential works to pipe 111, or NMOS complementary differential works to pipe 112, or PMOS complementary differential works to pipe 112 to pipe 111 and NMOS complementary differential simultaneously.Meanwhile, the electric current of the 14 metal-oxide-semiconductor M39 and the 15 metal-oxide-semiconductor M40 is come from current mirror circuit 140, when there being electric current in the 14 metal-oxide-semiconductor M39 and the 15 metal-oxide-semiconductor M40, does not have electric current in the first metal-oxide-semiconductor M1 and the second metal-oxide-semiconductor M2; On the contrary, when there being electric current in the first metal-oxide-semiconductor M1 and the second metal-oxide-semiconductor M2, in the 14 metal-oxide-semiconductor M39 and the 15 metal-oxide-semiconductor M40, electric current is not had.In like manner, when there being electric current in the 20 metal-oxide-semiconductor M45 and the 21 metal-oxide-semiconductor M46, then there is no electric current in the 3rd metal-oxide-semiconductor M3 and the 4th metal-oxide-semiconductor M4; When there being electric current in the 3rd metal-oxide-semiconductor M3 and the 4th metal-oxide-semiconductor M4, then there is no electric current in the 20 metal-oxide-semiconductor M45 and the 21 metal-oxide-semiconductor M46.

Wherein in an embodiment, current mirror circuit 140 comprises bias current sources, the 23 metal-oxide-semiconductor M27, the 24 metal-oxide-semiconductor M28, the 25 metal-oxide-semiconductor M30, the 26 metal-oxide-semiconductor the 29, the 27 metal-oxide-semiconductor M32, the 28 metal-oxide-semiconductor M33, the 29 metal-oxide-semiconductor M34, the 30 metal-oxide-semiconductor M35, the 31 metal-oxide-semiconductor M36 and the 32 metal-oxide-semiconductor M37.Wherein, 23 metal-oxide-semiconductor M27, the 24 metal-oxide-semiconductor M28, the 25 metal-oxide-semiconductor M30, the 26 metal-oxide-semiconductor the 29, the 31 metal-oxide-semiconductor M36 and the 32 metal-oxide-semiconductor M37 are NMOS tube, and the 27 metal-oxide-semiconductor M32, the 28 metal-oxide-semiconductor M33, the 29 metal-oxide-semiconductor M34 and the 30 metal-oxide-semiconductor M35 are PMOS.

The input of bias current sources connects power end VDD, the output of bias current sources connects the drain electrode of the 23 metal-oxide-semiconductor M27, the source electrode of the 23 metal-oxide-semiconductor M27 connects the drain electrode of the 24 metal-oxide-semiconductor M28, the source electrode of the 25 metal-oxide-semiconductor M30 connects the drain electrode of the 26 metal-oxide-semiconductor M29, the common port that the output that the grid of the 23 metal-oxide-semiconductor M27 connects bias current sources is connected with the drain electrode of the 23 metal-oxide-semiconductor M27, and connect the grid of the 25 metal-oxide-semiconductor M30, the common port that the source electrode that the grid of the 24 metal-oxide-semiconductor M28 connects the 23 metal-oxide-semiconductor M27 is connected with the drain electrode of the 24 metal-oxide-semiconductor M28, and connect the grid of the 26 metal-oxide-semiconductor M29, the source electrode of the 24 metal-oxide-semiconductor M28 and the source grounding GND of the 26 metal-oxide-semiconductor M29.

The drain electrode of the 27 metal-oxide-semiconductor M32 connects the drain electrode of the 25 metal-oxide-semiconductor M30, the source electrode of the 27 metal-oxide-semiconductor M32 connects the drain electrode of the 28 metal-oxide-semiconductor M33, the grid of the 27 metal-oxide-semiconductor M32 connects the grid of the 30 metal-oxide-semiconductor M35, and the common port that the drain electrode that common port connects the 27 metal-oxide-semiconductor M32 is connected with the drain electrode of the 25 metal-oxide-semiconductor M30.The source electrode of the 28 metal-oxide-semiconductor M33 connects power end VDD, the grid of the 28 metal-oxide-semiconductor M33 connects the grid of the 29 metal-oxide-semiconductor M34, and the common port that the drain electrode that common port connects the 28 metal-oxide-semiconductor M33 is connected with the source electrode of the 27 metal-oxide-semiconductor M32, the source electrode of the 29 metal-oxide-semiconductor M34 connects power end VDD.The drain electrode of the 29 metal-oxide-semiconductor M34 connects the source electrode of the 30 metal-oxide-semiconductor M35.The drain electrode of the 30 metal-oxide-semiconductor M35 connects rail-to-rail input stage circuit 110 and ascending current compensating circuit 120, in the present embodiment, is specially the source electrode of connection first metal-oxide-semiconductor M1, the source electrode of the second metal-oxide-semiconductor M2 and the source electrode of the 13 metal-oxide-semiconductor.

The drain electrode of the 31 metal-oxide-semiconductor M36 connects rail-to-rail input stage circuit 110 and centrifugal current compensating circuit 130, in the present embodiment, is specially the source electrode of connection the 3rd metal-oxide-semiconductor M3, the source electrode of the 4th metal-oxide-semiconductor M4 and the source electrode of the 22 metal-oxide-semiconductor M47.The source electrode of the 31 metal-oxide-semiconductor M36 connects the drain electrode of the 32 metal-oxide-semiconductor M37, the grid of the 31 metal-oxide-semiconductor M36 connects the grid of the 25 metal-oxide-semiconductor M30, the grid of the 32 metal-oxide-semiconductor M37 connects the grid of the 26 metal-oxide-semiconductor M29, the source ground GND of the 32 metal-oxide-semiconductor M37.

Wherein in an embodiment, current mirror circuit 140 also comprises the 33 metal-oxide-semiconductor M31, and in the present embodiment, the 33 metal-oxide-semiconductor M31 is PMOS.The source electrode of the 33 metal-oxide-semiconductor M31 connects the drain electrode of the 27 metal-oxide-semiconductor M32, and the drain electrode of the 33 metal-oxide-semiconductor M33 connects the drain electrode of the 25 metal-oxide-semiconductor M30, and common port connects the grid of the 33 metal-oxide-semiconductor M31.33 metal-oxide-semiconductor M31 has the dividing potential drop effect of threshold voltage, make the drain voltage of the 27 metal-oxide-semiconductor M32 and the 30 metal-oxide-semiconductor M35 more close, simultaneously, the drain voltage of the 25 metal-oxide-semiconductor M30 and the 31 metal-oxide-semiconductor M36 is close, thus reduce the channel-length modulation of metal-oxide-semiconductor, the accuracy of repetition of current mirror circuit 140 can be improved.Be appreciated that in other embodiments, the quantity of the 33 metal-oxide-semiconductor M31 can have multiple.

The bias current I of bias current sources _reffor providing the reference current of circuit.23 metal-oxide-semiconductor M27 and the 24 metal-oxide-semiconductor M28 and the 25 metal-oxide-semiconductor M30 and the 26 metal-oxide-semiconductor M29 forms 1:1 current-mirror structure, with reference to electric current I _refaccurately copy in the 27 metal-oxide-semiconductor M32 and the 28 metal-oxide-semiconductor M33, then the K be made up of the 30 metal-oxide-semiconductor M35 and the 29 metal-oxide-semiconductor M34 and the 27 metal-oxide-semiconductor M32 and the 28 metal-oxide-semiconductor M33 ₁: 1 current-mirror structure, by K ₁reference current I doubly _refcopy in the 29 metal-oxide-semiconductor M34 and the 30 metal-oxide-semiconductor M35, to be supplied to the first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2 and ascending current compensating circuit 120.K is formed by the 31 metal-oxide-semiconductor M36 and the 32 metal-oxide-semiconductor M37 and the 25 metal-oxide-semiconductor M30 and the 26 metal-oxide-semiconductor M29 ₁: 1 current-mirror structure, by K ₁reference current I doubly _refcopy in the 31 metal-oxide-semiconductor M36 and the 32 metal-oxide-semiconductor M37, to be supplied to the 3rd metal-oxide-semiconductor M3, the 4th metal-oxide-semiconductor M4 and centrifugal current compensating circuit 130.

Wherein in an embodiment, output-stage circuit 150 comprises the 34 metal-oxide-semiconductor M13, the 35 metal-oxide-semiconductor M14, the 36 metal-oxide-semiconductor M15 and the 37 metal-oxide-semiconductor M16.Wherein, the 34 metal-oxide-semiconductor M13 and the 35 metal-oxide-semiconductor M14 can be PMOS; 36 metal-oxide-semiconductor M15 and the 37 metal-oxide-semiconductor M16 can be NMOS tube.

The source electrode of the 34 metal-oxide-semiconductor M13 connects power end VDD, and the grid of the 34 metal-oxide-semiconductor M13 connects current mirror circuit 140, in the present embodiment, can be specifically the grid of connection the 28 metal-oxide-semiconductor M33.The drain electrode of the 34 metal-oxide-semiconductor M13 connects the source electrode of the 35 metal-oxide-semiconductor M14, and the grid of the 35 metal-oxide-semiconductor M15 connects current mirror circuit 140, in the present embodiment, can be specifically the grid of connection the 27 metal-oxide-semiconductor M32.The drain electrode of the 35 metal-oxide-semiconductor M14 connects the drain electrode of the 36 metal-oxide-semiconductor M15, and common port is the output of output-stage circuit 150, is the output of rail-to-rail operational amplifier.The external 3rd bias voltage Vb3 of grid of the 36 metal-oxide-semiconductor M15, the source electrode of the 36 metal-oxide-semiconductor M15 connects the drain electrode of the 37 metal-oxide-semiconductor M16, the grid of the 37 metal-oxide-semiconductor M16 connects rail-to-rail input stage circuit 110, the source ground GND of the 37 metal-oxide-semiconductor M16.Particularly, in the present embodiment, the common port that the drain electrode that the grid of the 37 metal-oxide-semiconductor M16 connects the 8th metal-oxide-semiconductor M8 is connected with the drain electrode of the tenth metal-oxide-semiconductor.

34 metal-oxide-semiconductor M13 of output-stage circuit 150 and the 35 metal-oxide-semiconductor M14 and the 28 metal-oxide-semiconductor M33 and the 27 metal-oxide-semiconductor M32 forms K ₂: 1 current-mirror structure, by K ₂reference current I doubly _refcopy in the 34 metal-oxide-semiconductor M13 and the 35 metal-oxide-semiconductor M14.Wherein K ₂reference current I doubly _reffor the current offset of output-stage circuit 150, for the work of the 36 metal-oxide-semiconductor M15 and the 37 metal-oxide-semiconductor M16 provides bias current.

Wherein in an embodiment, rail-to-rail operational amplifier also comprises ascending current comparison circuit 160 and centrifugal current comparison circuit 170, and ascending current comparison circuit 160 and centrifugal current comparison circuit 170 are connected rail-to-rail input stage circuit 110, current mirror circuit 140 and output-stage circuit 150 respectively.

Ascending current comparison circuit 160 comprises the 38 metal-oxide-semiconductor M17, the 39 metal-oxide-semiconductor M18, the 40 metal-oxide-semiconductor M19, the 41 metal-oxide-semiconductor M20 and the 42 metal-oxide-semiconductor M25.Wherein, the 38 metal-oxide-semiconductor M17 and the 39 metal-oxide-semiconductor M18 can be PMOS, and the 40 metal-oxide-semiconductor M19, the 41 metal-oxide-semiconductor M20 and the 42 metal-oxide-semiconductor M25 can be NMOS tube.

The source electrode of the 38 metal-oxide-semiconductor M17 connects power end VDD, and the grid of the 38 metal-oxide-semiconductor M17 connects current mirror circuit 140, in the present embodiment, is specially the grid of connection the 28 metal-oxide-semiconductor M33.The drain electrode of the 38 metal-oxide-semiconductor M17 connects the source electrode of the 39 metal-oxide-semiconductor M18, and the grid of the 39 metal-oxide-semiconductor M18 connects current mirror circuit 140, is specially the grid of connection the 27 metal-oxide-semiconductor M32 in the present embodiment.The drain electrode of the 39 metal-oxide-semiconductor M18 connects the drain electrode of the 40 metal-oxide-semiconductor M19, and common port connects the grid of the 42 metal-oxide-semiconductor M25.Wherein, the 38 metal-oxide-semiconductor M17 and the 39 metal-oxide-semiconductor M18 and the 28 metal-oxide-semiconductor M33 and the 27 metal-oxide-semiconductor M32 forms (K ₃-K ₁-△ K): the current-mirror structure of 1.Due to the threshold value dividing potential drop effect of the 33 metal-oxide-semiconductor M31, make the drain voltage of the 27 metal-oxide-semiconductor M32 and the 39 metal-oxide-semiconductor M18 more close, thus reduce the channel-length modulation of metal-oxide-semiconductor, the accuracy of repetition of current-mirror structure to electric current can be improved.

The grid of the 40 metal-oxide-semiconductor M19 connects rail-to-rail input stage circuit 110, is specially the grid of connection the 9th metal-oxide-semiconductor M9 in the present embodiment.That is, the grid of the 40 metal-oxide-semiconductor M19 and the grid concurrent of the 9th metal-oxide-semiconductor M9, can follow the tracks of the change of electric current in the 9th metal-oxide-semiconductor M9.The source electrode of the 40 metal-oxide-semiconductor M19 connects the drain electrode of the 41 metal-oxide-semiconductor M20, and the grid of the 41 metal-oxide-semiconductor M20 connects rail-to-rail input stage circuit 110, is specially the grid of connection the 11 metal-oxide-semiconductor in the present embodiment.The source ground GND of the 41 metal-oxide-semiconductor M20.The drain electrode of the 42 metal-oxide-semiconductor M25 connects power end VDD, the source electrode of the 42 metal-oxide-semiconductor M25 connects output-stage circuit 150, be specially the output connecting output-stage circuit 150, the common port that the drain electrode namely connecting the 35 metal-oxide-semiconductor M14 is connected with the drain electrode of the 36 metal-oxide-semiconductor M15.

Centrifugal current comparison circuit 170 comprises the 43 metal-oxide-semiconductor M21, the 44 metal-oxide-semiconductor M22, the 45 metal-oxide-semiconductor M23, the 46 metal-oxide-semiconductor M24 and the 47 metal-oxide-semiconductor M26.Wherein, the 43 metal-oxide-semiconductor M21, the 44 metal-oxide-semiconductor M22 and the 47 metal-oxide-semiconductor M26 can be PMOS, and the 45 metal-oxide-semiconductor M23, the 46 metal-oxide-semiconductor M24 can be NMOS tube.

The source electrode of the 43 metal-oxide-semiconductor M21 connects power end VDD, the grid of the 43 metal-oxide-semiconductor M21 connects rail-to-rail input stage circuit 110, be specially the grid of connection the 5th metal-oxide-semiconductor M5 in the present embodiment, the drain electrode of the 43 metal-oxide-semiconductor M21 connects the source electrode of the 44 metal-oxide-semiconductor M22.The grid of the 44 metal-oxide-semiconductor M22 connects rail-to-rail input stage circuit 110, the grid connecting described 7th metal-oxide-semiconductor M7 is specially in the present embodiment, the drain electrode of the 44 metal-oxide-semiconductor M22 connects the drain electrode of the 45 metal-oxide-semiconductor M23, and common port connects the grid of the 47 metal-oxide-semiconductor M26.

The grid of the 45 metal-oxide-semiconductor M23 connects current mirror circuit 140, is specially the grid of connection the 25 metal-oxide-semiconductor 30 in the present embodiment, and the source electrode of described 45 metal-oxide-semiconductor M23 connects the drain electrode of the 46 metal-oxide-semiconductor M24.The grid of the 46 metal-oxide-semiconductor M24 connects current mirror circuit 140, in the present embodiment, is specially the grid of connection the 26 metal-oxide-semiconductor M29, the source ground GND of the 46 metal-oxide-semiconductor M24.The grounded drain GND of the 47 metal-oxide-semiconductor M26, the source electrode of the 47 metal-oxide-semiconductor M26 connects output-stage circuit 150, be specially the output connecting output-stage circuit 150, the common port that the drain electrode being connection the 35 metal-oxide-semiconductor M14 is connected with the drain electrode of the 36 metal-oxide-semiconductor M15.

Wherein, the 45 metal-oxide-semiconductor M23 and the 46 metal-oxide-semiconductor M24 and the 25 metal-oxide-semiconductor M30 and the 26 metal-oxide-semiconductor M29 forms (K ₃-K ₁-△ K): 1 current-mirror structure.Due to the threshold value dividing potential drop effect of the 33 metal-oxide-semiconductor M31, make the drain voltage of the 25 metal-oxide-semiconductor M30 and the 45 metal-oxide-semiconductor M23 more close, thus reduce the channel-length modulation of metal-oxide-semiconductor, the accuracy of repetition of current-mirror structure to electric current can be improved.

The effect of ascending current comparison circuit 160 is electric current and (K in the 9th metal-oxide-semiconductor M9 of more rail-to-rail input stage circuit 110 ₃-K ₁-△ K) times reference current I _refsize, thus control the break-make of the 42 metal-oxide-semiconductor M25 according to the size that compares, improve operating efficiency and the bandwidth of rail-to-rail operational amplifier, and reduce its quiescent dissipation.The effect of centrifugal current comparison circuit 170 is electric current and (K in the 7th metal-oxide-semiconductor M7 of more rail-to-rail input stage circuit 110 ₃-K ₁-△ K) times reference current I _refsize, thus control the break-make of the 47 metal-oxide-semiconductor M26 according to the size that compares, improve operating efficiency and the bandwidth of rail-to-rail operational amplifier, and reduce its quiescent dissipation.In the present embodiment, by ascending current comparison circuit 160 and centrifugal current comparison circuit 170, operating efficiency specifically can be made to reach 90%, and output bandwidth is more than 15MHZ.

Wherein in an embodiment, rail-to-rail operational amplifier also comprises miller-compensated circuit 180, and rail-to-rail input stage circuit 110 connects output-stage circuit 150 by miller-compensated circuit 180.Miller-compensated circuit 180 for the capacitance compensation of rail-to-rail input stage circuit 110 with output-stage circuit 150 liang of inter-stages, thus obtains suitable Frequency Response.

Particularly, in the present embodiment, miller-compensated circuit 180 comprises resistance R1 and electric capacity C1, and resistance R1 and electric capacity C1 connects, and one end of resistance R1 connects rail-to-rail input stage circuit 110, the grid being specially connection 37 metal-oxide-semiconductor M16 connects the common port of rail-to-rail input stage circuit 110.One end of electric capacity C1 connects the output of output-stage circuit 150.The size of regulating resistance R1 and electric capacity C1, eliminates a limit with a zero point, can improve output bandwidth and the stability of rail-to-rail operational amplifier.

Under the state of sub-threshold region, the mutual conductance of metal-oxide-semiconductor can be expressed as:

$g_{m,subth}=\frac{I_{Drain}}{{\mathrm{nV}}_t};$

$n=\frac{C_{ox}+C_{dep}}{C_{ox}};$

$V_t=\frac{kT}{q};$

Wherein, I _drainfor the drain current of metal-oxide-semiconductor, n is the sub-threshold slope factor, V _tfor calorific potential voltage, C _oxfor unit area mountain oxide layer electric capacity, C _depfor unit area depletion region capacitance, k is Boltzmann constant, and T is absolute temperature, and q is electron charge.Determined by metal-oxide-semiconductor drain circuit by the metal-oxide-semiconductor mutual conductance of above-mentioned three known sub-threshold region of formula, as long as therefore ensure PMOS complementary differential to pipe 111 and NMOS complementary differential constant to the operating current that pipe 112 is total, then the mutual conductance of rail-to-rail input stage circuit 110 can keep invariable substantially.

In the present embodiment, the total mutual conductance of rail-to-rail input stage circuit 110 is:

$g_{m,RTR}=\frac{I_{P,tail}}{2{\mathrm{nV}}_t}+\frac{I_{N,tail}}{2{\mathrm{nV}}_t}=\frac{I_{P,tail}+I_{N,tail}}{2{\mathrm{nV}}_t};$

In formula, g _{m, RTR}for total mutual conductance of rail-to-rail input stage circuit 110, I _{p, tail}for PMOS complementary differential is to the tail current of pipe 111, I _{n, tail}for NMOS complementary differential is to the tail current of pipe 112, be K ₁i _ref, i.e. K ₁reference current I doubly _ref.If by I when PMOS complementary differential quits work to pipe 111 _{p, tail}compensate to I _{n, tail}, or by I when NMOS complementary differential quits work to pipe 112 _{n, tail}compensate to I _{p, tail}, just substantially can maintain the constant of rail-to-rail input stage circuit 110 mutual conductance, its total mutual conductance just can be expressed as:

$g_{m,RTR}=\frac{K_1{I}_{ref}}{{\mathrm{nV}}_t};$

In formula, K ₁ratio is copied, I for current mirror circuit 140 _reffor reference current.Therefore, the course of work of this circuit can be divided into common mode electrical level signal closely VDD/2, common mode electrical level signal uplink, common mode electrical level signal downlink three parts.

(1) when the voltage inputting common mode electrical level signal closely VDD/2 time, PMOS complementary differential all normally works to the 3rd metal-oxide-semiconductor M3 of pipe 112 and the 4th metal-oxide-semiconductor M4 to the first metal-oxide-semiconductor M1 of pipe 111 and the second metal-oxide-semiconductor M2 and NMOS complementary differential, ascending current compensating circuit 120 and centrifugal current compensating circuit 130 are all in closed condition, total mutual conductance is that PMOS complementary differential is added the mutual conductance of pipe 112 pipe 111 and NMOS complementary differential, is K ₁i _ref/ nV _t.

Now, the electric current in the 9th metal-oxide-semiconductor M9 is about (K ₃-K ₁/ 2) I _ref, the electric current in theory in the 40 metal-oxide-semiconductor M19 should be equal with the 9th metal-oxide-semiconductor M9, and the 38 metal-oxide-semiconductor M17 and the 39 metal-oxide-semiconductor M18 wants the electric current in exact mirror image the 28 metal-oxide-semiconductor M33 and the 27 metal-oxide-semiconductor M32, and its current value is (K ₃-K ₁-△ K) I _ref, be less than the electric current (K in the 40 metal-oxide-semiconductor M19 ₃-K ₁/ 2) I _ref, now the drain voltage of the 40 metal-oxide-semiconductor M19 is lower, still not enough with the 42 metal-oxide-semiconductor M25 is opened, ascending current comparison circuit 160 is in closed condition.In like manner, now centrifugal current comparison circuit 170 is also in closed condition.

(2) when the voltage inputting common mode electrical level signal go upward to PMOS complementary differential the first metal-oxide-semiconductor M1 in pipe 111 and the second metal-oxide-semiconductor M2 is quit work time, ascending current compensating circuit 120 is started working, be the operating current of NMOS complementary differential to pipe by the current compensation in the 29 metal-oxide-semiconductor M34 and the 30 metal-oxide-semiconductor M35, the operating current that now NMOS complementary differential is total to pipe 112 is 2K ₁i _ref, the total transconductance value of rail-to-rail input stage circuit 110 is K ₁i _ref/ nV _t, consistent when pipe being worked simultaneously with two complementary differential, maintain the constant of mutual conductance.

Now, the electric current in the 9th metal-oxide-semiconductor M9 is K ₃i _ref, the electric current in theory in the 40 metal-oxide-semiconductor M19 is also K ₃i _ref, be greater than the image current (K in the 38 metal-oxide-semiconductor M17 and the 39 metal-oxide-semiconductor M18 ₃-K ₁-△ K) I _refat this moment electric current can order about the 40 metal-oxide-semiconductor M19 and the 41 metal-oxide-semiconductor M20 and enter linear zone close to saturation region, due to channel-length modulation, the drain voltage being in the 39 metal-oxide-semiconductor M18 of saturation region is lower, namely the grid voltage of the 42 metal-oxide-semiconductor M25 is lower, 42 metal-oxide-semiconductor M25 is in cut-off state, and ascending current comparison circuit 160 is in buttoned-up status.Meanwhile, the electric current in the 7th metal-oxide-semiconductor M7 is (K ₃-K ₁) I _ref, the electric current of the 44 metal-oxide-semiconductor M22 is also (K ₃-K ₁) I _ref, slightly larger than the electric current (K in the 45 metal-oxide-semiconductor M23 and the 46 metal-oxide-semiconductor M24 ₃-K ₁-△ K) I _refat this moment electric current can order about the 43 metal-oxide-semiconductor M21 and the 44 metal-oxide-semiconductor M22 and enter linear zone close to saturation region, due to channel-length modulation, the drain voltage being in the 45 metal-oxide-semiconductor M23 of saturation region is higher, namely the grid voltage of the 47 metal-oxide-semiconductor M26 is higher, 47 metal-oxide-semiconductor M26 is in the closed condition close to opening, and centrifugal current comparison circuit 170 is in the closed condition close to opening.

When the output end vo ut of output-stage circuit 150 is connected with inverting input Vin-component unit gain amplifier time, the voltage of the level signal that in-phase input end Vin+ inputs reduces △ V, and the electric current in the 7th metal-oxide-semiconductor M7 can reduce g _{m, RTR}△ V, electric current in 44 metal-oxide-semiconductor M22 also can correspondingly reduce, order about the 43 metal-oxide-semiconductor M21 and the 44 metal-oxide-semiconductor M22 and enter saturation region, and order about the 45 metal-oxide-semiconductor M23 and the 46 metal-oxide-semiconductor M24 and enter linear zone, 45 metal-oxide-semiconductor M23 drain electrode level reduces, thus opens the 47 metal-oxide-semiconductor M26.△ V is larger, and the grid voltage of the 47 metal-oxide-semiconductor M26 is lower, and the electric current produced in the 47 metal-oxide-semiconductor M26 is larger, increases the leakage current to load capacitance, effectively improves operating efficiency and the operating rate of output-stage circuit 150.When the output end vo ut of output-stage circuit 150 and in-phase input end Vin+ close to time, inverting input Vin-and in-phase input end Vin+ is close, and the electric current in the 7th metal-oxide-semiconductor M7 and the 44 metal-oxide-semiconductor M22 is close to (K ₃-K ₁) I _ref, the 47 metal-oxide-semiconductor M26 closes again, and final voltage is determined by output-stage circuit 150.If the voltage of the level signal that in-phase input end Vin+ inputs slightly rises, the 7th metal-oxide-semiconductor M7 and the 44 metal-oxide-semiconductor M22 electric current slightly raise, and the 47 metal-oxide-semiconductor M26 opening further away from each other, final output voltage is determined by output-stage circuit 150.Can be found by above-mentioned analysis, ascending current comparison circuit 160 and centrifugal current comparison circuit 170 be grouped together can be not too responsive to constrained input edge response class AB output-stage circuit.

(3) when the voltage of common mode electrical level signal inputted come downwards to NMOS complementary differential pipe 112 is quit work time, centrifugal current compensating circuit 130 is started working, and is the operating current of PMOS complementary differential to pipe 111 by the current compensation in the 31 metal-oxide-semiconductor M36 and the 32 metal-oxide-semiconductor M37.The operating current that now PMOS complementary differential is total to pipe 111 is 2K ₁i _ref, its total transconductance value is K ₁i _ref/ nV _t, remain on steady state.Similar when ascending current comparison circuit 160 is up to the voltage of common mode level signal with the course of work of centrifugal current comparison circuit 170, for reducing power consumption, increase work efficiency and output speed.

Each technical characteristic of the above embodiment can combine arbitrarily, for making description succinct, the all possible combination of each technical characteristic in above-described embodiment is not all described, but, as long as the combination of these technical characteristics does not exist contradiction, be all considered to be the scope that this specification is recorded.

The above embodiment only have expressed several execution mode of the present invention, and it describes comparatively concrete and detailed, but can not therefore be construed as limiting the scope of the patent.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection range of patent of the present invention should be as the criterion with claims.

Claims (10)

1. a rail-to-rail operational amplifier, it is characterized in that, comprise: rail-to-rail input stage circuit, ascending current compensating circuit, centrifugal current compensating circuit, output-stage circuit and current mirror circuit, described rail-to-rail input stage circuit connects described ascending current compensating circuit, described centrifugal current compensating circuit, described current mirror circuit and described output-stage circuit respectively, and described current mirror circuit also connects described ascending current compensating circuit, centrifugal current compensating circuit and output-stage circuit;

Described current mirror circuit is described rail-to-rail input stage circuit, described ascending current compensating circuit, described centrifugal current compensating circuit and described output-stage circuit provide bias current, described rail-to-rail input stage circuit is for accessing common mode electrical level signal and exporting described output-stage circuit to, and described output-stage circuit is used for carrying out process to described common mode electrical level signal and exports amplifying signal; Described ascending current compensating circuit and described centrifugal current compensating circuit are respectively used to compensate the operating current of described rail-to-rail input stage circuit when the voltage of described common mode electrical level signal is up or voltage is descending, keep constant to make the operating current of described rail-to-rail input stage circuit.

2. rail-to-rail operational amplifier according to claim 1, it is characterized in that, described rail-to-rail input stage circuit comprises PMOS complementary differential to pipe, NMOS complementary differential to pipe and cascodes circuit, described PMOS complementary differential is respectively connected described current mirror circuit, described cascodes circuit, described ascending current compensating circuit and described centrifugal current compensating circuit with described NMOS complementary differential to pipe to pipe, and described cascodes circuit connects described output-stage circuit.

3. rail-to-rail operational amplifier according to claim 2, it is characterized in that, described PMOS complementary differential comprises the first metal-oxide-semiconductor and the second metal-oxide-semiconductor to pipe, described NMOS complementary differential comprises the 3rd metal-oxide-semiconductor and the 4th metal-oxide-semiconductor to pipe, and described cascodes circuit comprises the 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor, the 7th metal-oxide-semiconductor, the 8th metal-oxide-semiconductor, the 9th metal-oxide-semiconductor, the tenth metal-oxide-semiconductor, the 11 metal-oxide-semiconductor and the 12 metal-oxide-semiconductor;

The source electrode of described first metal-oxide-semiconductor is connected with the source electrode of described second metal-oxide-semiconductor, and common port connects described current mirror circuit respectively, described ascending current compensating circuit and described centrifugal current compensating circuit, the source electrode of described 3rd metal-oxide-semiconductor is connected with the source electrode of described 4th metal-oxide-semiconductor, and common port connects described current mirror circuit respectively, described ascending current compensating circuit and described centrifugal current compensating circuit, the grid of described first metal-oxide-semiconductor is connected with the grid of described 3rd metal-oxide-semiconductor and forms the inverting input of described rail-to-rail operational amplifier, the grid of described second metal-oxide-semiconductor is connected with the grid of described 4th metal-oxide-semiconductor and forms the in-phase input end of described rail-to-rail operational amplifier,

The grid of described 5th metal-oxide-semiconductor is connected with the grid of described 6th metal-oxide-semiconductor, the grid of described 7th metal-oxide-semiconductor is connected with the grid of described 8th metal-oxide-semiconductor, the drain electrode of described 5th metal-oxide-semiconductor is connected with the source electrode of described 7th metal-oxide-semiconductor, and common port connects the drain electrode of described 3rd metal-oxide-semiconductor, the source electrode of described 5th metal-oxide-semiconductor connects power end, the drain electrode of described 6th metal-oxide-semiconductor is connected with the source electrode of described 8th metal-oxide-semiconductor, and common port connects the drain electrode of described 4th metal-oxide-semiconductor, the source electrode of described 6th metal-oxide-semiconductor connects described power end;

The grid of described 9th metal-oxide-semiconductor is connected with the grid of described tenth metal-oxide-semiconductor, the grid of described 11 metal-oxide-semiconductor is connected with the grid of described 12 metal-oxide-semiconductor, the source electrode of described 9th metal-oxide-semiconductor is connected with the drain electrode of described 11 metal-oxide-semiconductor, and common port connects the drain electrode of described first metal-oxide-semiconductor, the source electrode of described tenth metal-oxide-semiconductor is connected with the drain electrode of described 12 metal-oxide-semiconductor, and common port connects the drain electrode of described second metal-oxide-semiconductor, the source electrode of described 11 metal-oxide-semiconductor and the source ground of described 12 metal-oxide-semiconductor;

The drain electrode of described 7th metal-oxide-semiconductor is connected with the drain electrode of described 9th metal-oxide-semiconductor, and the common port that the grid that common port connects described 5th metal-oxide-semiconductor is respectively connected with the grid of described 6th metal-oxide-semiconductor, and the common port that the grid of described 11 metal-oxide-semiconductor is connected with the grid of described 12 metal-oxide-semiconductor, the drain electrode of described 8th metal-oxide-semiconductor is connected with the drain electrode of described tenth metal-oxide-semiconductor, and common port connects described output-stage circuit.

4. rail-to-rail operational amplifier according to claim 1, is characterized in that, described ascending current compensating circuit comprises the 13 metal-oxide-semiconductor, the 14 metal-oxide-semiconductor, the 15 metal-oxide-semiconductor, the 16 metal-oxide-semiconductor and the 17 metal-oxide-semiconductor;

The source electrode of described 13 metal-oxide-semiconductor connects described rail-to-rail input stage circuit, external first bias voltage of grid of described 13 metal-oxide-semiconductor, the drain electrode of described 14 metal-oxide-semiconductor connects the drain electrode of described 13 metal-oxide-semiconductor, the grid of described 14 metal-oxide-semiconductor is connected with the grid of described 16 metal-oxide-semiconductor, and the common port that the drain electrode that common port connects described 13 metal-oxide-semiconductor is connected with the drain electrode of described 14 metal-oxide-semiconductor, the source electrode of described 14 metal-oxide-semiconductor connects the drain electrode of described 15 metal-oxide-semiconductor, the source electrode of described 16 metal-oxide-semiconductor connects the drain electrode of described 17 metal-oxide-semiconductor, the grid of described 15 metal-oxide-semiconductor is connected with the grid of described 17 metal-oxide-semiconductor, and the common port that the source electrode that common port connects described 14 metal-oxide-semiconductor is connected with the drain electrode of described 15 metal-oxide-semiconductor, the drain electrode of described 16 metal-oxide-semiconductor connects described rail-to-rail input stage circuit, the source electrode of described 15 metal-oxide-semiconductor and the source grounding of described 17 metal-oxide-semiconductor,

Described centrifugal current compensating circuit comprises the 18 metal-oxide-semiconductor, the 19 metal-oxide-semiconductor, the 20 metal-oxide-semiconductor, the 21 metal-oxide-semiconductor and the 22 metal-oxide-semiconductor;

The source electrode of described 18 metal-oxide-semiconductor is all connected described power end with the source electrode of described 20 metal-oxide-semiconductor, the drain electrode of described 18 metal-oxide-semiconductor connects the source electrode of described 19 metal-oxide-semiconductor, the drain electrode of described 19 metal-oxide-semiconductor connects described rail-to-rail input stage circuit, the drain electrode of described 20 metal-oxide-semiconductor connects the source electrode of described 21 metal-oxide-semiconductor, and the drain electrode of described 21 metal-oxide-semiconductor connects the drain electrode of described 22 metal-oxide-semiconductor; The grid of described 18 metal-oxide-semiconductor connects the grid of described 20 metal-oxide-semiconductor, and the common port that the drain electrode that common port connects described 20 metal-oxide-semiconductor is connected with the source electrode of described 21 metal-oxide-semiconductor, the grid of described 19 metal-oxide-semiconductor connects the grid of described 21 metal-oxide-semiconductor, and the common port that the drain electrode that common port connects described 21 metal-oxide-semiconductor is connected with the drain electrode of described 22 metal-oxide-semiconductor, the source electrode of described 22 metal-oxide-semiconductor connects described rail-to-rail input stage circuit, external second bias voltage of grid of described 22 metal-oxide-semiconductor.

5. rail-to-rail operational amplifier according to claim 1, it is characterized in that, described current mirror circuit comprises bias current sources, the 23 metal-oxide-semiconductor, the 24 metal-oxide-semiconductor, the 25 metal-oxide-semiconductor, the 26 metal-oxide-semiconductor, the 27 metal-oxide-semiconductor, the 28 metal-oxide-semiconductor, the 29 metal-oxide-semiconductor, the 30 metal-oxide-semiconductor, the 31 metal-oxide-semiconductor and the 32 metal-oxide-semiconductor;

The input of described bias current sources connects described power end, the output of described bias current sources connects the drain electrode of described 23 metal-oxide-semiconductor, the source electrode of described 23 metal-oxide-semiconductor connects the drain electrode of described 24 metal-oxide-semiconductor, the source electrode of described 25 metal-oxide-semiconductor connects the drain electrode of described 26 metal-oxide-semiconductor, the common port that the output that the grid of described 23 metal-oxide-semiconductor connects described bias current sources is connected with the drain electrode of described 23 metal-oxide-semiconductor, and connect the grid of described 25 metal-oxide-semiconductor, the common port that the source electrode that the grid of described 24 metal-oxide-semiconductor connects described 23 metal-oxide-semiconductor is connected with the drain electrode of described 24 metal-oxide-semiconductor, and connect the grid of described 26 metal-oxide-semiconductor, the source electrode of described 24 metal-oxide-semiconductor and the source grounding of described 26 metal-oxide-semiconductor,

The drain electrode of described 27 metal-oxide-semiconductor connects the drain electrode of described 25 metal-oxide-semiconductor, the source electrode of described 27 metal-oxide-semiconductor connects the drain electrode of described 28 metal-oxide-semiconductor, the grid of described 27 metal-oxide-semiconductor connects the grid of described 30 metal-oxide-semiconductor, and the common port that the drain electrode that common port connects described 27 metal-oxide-semiconductor is connected with the drain electrode of described 25 metal-oxide-semiconductor, the source electrode of described 28 metal-oxide-semiconductor connects described power end, the grid of described 28 metal-oxide-semiconductor connects the grid of described 29 metal-oxide-semiconductor, and the common port that the drain electrode that common port connects described 28 metal-oxide-semiconductor is connected with the source electrode of described 27 metal-oxide-semiconductor, the source electrode of described 29 metal-oxide-semiconductor connects described power end, the drain electrode of described 29 metal-oxide-semiconductor connects the source electrode of described 30 metal-oxide-semiconductor, the drain electrode of described 30 metal-oxide-semiconductor connects described rail-to-rail input stage circuit and described ascending current compensating circuit,

The drain electrode of described 31 metal-oxide-semiconductor connects described rail-to-rail input stage circuit and described centrifugal current compensating circuit, the source electrode of described 31 metal-oxide-semiconductor connects the drain electrode of described 32 metal-oxide-semiconductor, the grid of described 31 metal-oxide-semiconductor connects the grid of described 25 metal-oxide-semiconductor, the grid of described 32 metal-oxide-semiconductor connects the grid of described 26 metal-oxide-semiconductor, the source ground of described 32 metal-oxide-semiconductor.

6. rail-to-rail operational amplifier according to claim 5, it is characterized in that, described current mirror circuit also comprises the 33 metal-oxide-semiconductor, the source electrode of described 33 metal-oxide-semiconductor connects the drain electrode of described 27 metal-oxide-semiconductor, the drain electrode of described 33 metal-oxide-semiconductor connects the drain electrode of described 25 metal-oxide-semiconductor, and common port connects the grid of described 33 metal-oxide-semiconductor.

7. rail-to-rail operational amplifier according to claim 1, is characterized in that, described output-stage circuit comprises the 34 metal-oxide-semiconductor, the 35 metal-oxide-semiconductor, the 36 metal-oxide-semiconductor and the 37 metal-oxide-semiconductor;

The source electrode of described 34 metal-oxide-semiconductor connects described power end, the grid of described 34 metal-oxide-semiconductor connects described current mirror circuit, the drain electrode of described 34 metal-oxide-semiconductor connects the source electrode of described 35 metal-oxide-semiconductor, the grid of described 35 metal-oxide-semiconductor connects described current mirror circuit, the drain electrode of described 35 metal-oxide-semiconductor connects the drain electrode of described 36 metal-oxide-semiconductor, and common port is the output of described output-stage circuit;

External 3rd bias voltage of grid of described 36 metal-oxide-semiconductor, the source electrode of described 36 metal-oxide-semiconductor connects the drain electrode of described 37 metal-oxide-semiconductor, the grid of described 37 metal-oxide-semiconductor connects described rail-to-rail input stage circuit, the source ground of described 37 metal-oxide-semiconductor.

8. rail-to-rail operational amplifier according to claim 1, it is characterized in that, also comprise ascending current comparison circuit and centrifugal current comparison circuit, described ascending current comparison circuit is connected described rail-to-rail input stage circuit, described current mirror circuit and described output-stage circuit respectively with described centrifugal current comparison circuit.

9. rail-to-rail operational amplifier according to claim 8, is characterized in that, described ascending current comparison circuit comprises the 38 metal-oxide-semiconductor, the 39 metal-oxide-semiconductor, the 40 metal-oxide-semiconductor, the 41 metal-oxide-semiconductor and the 42 metal-oxide-semiconductor;

The source electrode of described 38 metal-oxide-semiconductor connects described power end, the grid of described 38 metal-oxide-semiconductor connects described current mirror circuit, the drain electrode of described 38 metal-oxide-semiconductor connects the source electrode of described 39 metal-oxide-semiconductor, the grid of described 39 metal-oxide-semiconductor connects described current mirror circuit, the drain electrode of described 39 metal-oxide-semiconductor connects the drain electrode of described 40 metal-oxide-semiconductor, and common port connects the grid of described 42 metal-oxide-semiconductor; The grid of described 40 metal-oxide-semiconductor connects described rail-to-rail input stage circuit, the source electrode of described 40 metal-oxide-semiconductor connects the drain electrode of described 41 metal-oxide-semiconductor, the grid of described 41 metal-oxide-semiconductor connects described rail-to-rail input stage circuit, the source ground of described 41 metal-oxide-semiconductor; The drain electrode of described 42 metal-oxide-semiconductor connects described power end, and the source electrode of described 42 metal-oxide-semiconductor connects described output-stage circuit;

Described centrifugal current comparison circuit comprises the 43 metal-oxide-semiconductor, the 44 metal-oxide-semiconductor, the 45 metal-oxide-semiconductor, the 46 metal-oxide-semiconductor and the 47 metal-oxide-semiconductor;

The source electrode of described 43 metal-oxide-semiconductor connects described power end, the grid of described 43 metal-oxide-semiconductor connects described rail-to-rail input stage circuit, the drain electrode of described 43 metal-oxide-semiconductor connects the source electrode of described 44 metal-oxide-semiconductor, the grid of described 44 metal-oxide-semiconductor connects described rail-to-rail input stage circuit, the drain electrode of described 44 metal-oxide-semiconductor connects the drain electrode of described 45 metal-oxide-semiconductor, and common port connects the grid of described 47 metal-oxide-semiconductor; The grid of described 45 metal-oxide-semiconductor connects described current mirror circuit, the source electrode of described 45 metal-oxide-semiconductor connects the drain electrode of described 46 metal-oxide-semiconductor, the grid of described 46 metal-oxide-semiconductor connects described current mirror circuit, the source ground of described 46 metal-oxide-semiconductor; The grounded drain of described 47 metal-oxide-semiconductor, the source electrode of described 47 metal-oxide-semiconductor connects described output-stage circuit.

10. rail-to-rail operational amplifier according to claim 1, is characterized in that, also comprises miller-compensated circuit, and described rail-to-rail input stage circuit connects described output-stage circuit by described miller-compensated circuit.