CN113328711A - Constant cross-rail-to-rail input differential output high-speed programmable gain amplifier - Google Patents

Constant cross-rail-to-rail input differential output high-speed programmable gain amplifier Download PDF

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CN113328711A
CN113328711A CN202110684352.3A CN202110684352A CN113328711A CN 113328711 A CN113328711 A CN 113328711A CN 202110684352 A CN202110684352 A CN 202110684352A CN 113328711 A CN113328711 A CN 113328711A
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CN113328711B (en
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张啸蔚
钱福悦
何乐年
奚剑雄
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Zhejiang University ZJU
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
    • H03F3/45632—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit
    • H03F3/45636—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection in differential amplifiers with FET transistors as the active amplifying circuit by using feedback means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3211—Modifications of amplifiers to reduce non-linear distortion in differential amplifiers

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Abstract

The invention discloses a constant cross-guide rail to rail input differential output high-speed programmable gain amplifier which is mainly used for meeting the amplification requirement of a signal chain system on high-frequency signals, reducing harmonic distortion of the high-frequency signals and transmitting the harmonic distortion to a rear-end high-speed analog-to-digital converter. The gain amplifier structure is formed by cascade connection of two constant gm single-ended output operational amplifiers serving as a first stage and a constant gm differential output operational amplifier serving as a second stage, and input signals adjust the proportion of feedback resistors according to external gain selection signals, so that the signals are amplified to target gain. Therefore, the invention has the advantages of good linearity, high speed, constant gm, real-time amplification and the like.

Description

Constant cross-rail-to-rail input differential output high-speed programmable gain amplifier
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a constant cross-guide rail-to-rail input differential output high-speed programmable gain amplifier.
Background
The analog front end is a core module for processing analog signals in a signal system, is widely applied to data acquisition systems, sensors, radar communication and the like, and is a bridge for connecting an analog circuit and a digital circuit. Detecting and amplifying an analog signal of the nature by an analog front end signal, converting the analog signal into a digital signal which is easy to process through an analog-to-digital converter, and sending the digital signal to a digital system for processing; the Programmable Gain Amplifier (PGA) is one of the core components of the analog front-end module, and can amplify signals to different multiples according to the magnitude of input signals, thereby improving the dynamic range of the system.
Nowadays, an important feature of the development of integrated circuits is integration and miniaturization, and a system chip with high integration can reduce the overall cost and is easier to apply to the mobile portable market. As an important module of a signal system, the performance of a programmable gain amplifier has a crucial influence on the whole signal system, and the integration of the programmable gain amplifier into a system chip is a mainstream development trend; therefore, a programmable gain amplifier with high bandwidth, high linearity, and relatively large gain range adjustment is indispensable.
The conventional programmable gain amplifier generally adopts an instrument amplifier structure, as shown in fig. 1, the instrument amplifier adopts two stages of amplifiers, the first stage adopts a homodromous parallel differential amplifier, and the second stage adopts a basic differential amplifier, and has the advantages of high input impedance, strong common mode rejection capability, convenient gain adjustment and the like. However, this structure is only a single-ended output, and is often applied to amplifying a low-frequency signal, and if a high-frequency signal is amplified, a gain error is large, harmonic distortion is significant, and the like.
On the other hand, the conventional programmable gain amplifier has a certain range limit on the common-mode voltage of the input signal, so that when the input common-mode voltage is close to the power supply voltage or the ground, the programmable gain amplifier cannot normally work, and when the common-mode embezzlement plan deviation of the input signal is large, the gain of the amplifier can correspondingly fluctuate; the analog signal in nature causes unstable performance of the programmable gain amplifier because the common-mode voltage is not constant, which is not favorable for application in an integrated system.
Disclosure of Invention
In view of the above, the present invention provides a constant cross-rail to rail input differential output high speed programmable gain amplifier for application in amplifying high frequency signals, providing stable gain and low harmonic distortion.
A constant cross-guide rail-to-rail input differential output high-speed programmable gain amplifier comprises 7 adjustable resistor arrays R1～R72 primary operational amplifiers A1 and A2 and a differential output secondary operational amplifier A3, wherein the non-inverting input end of A1 is connected with a non-inverting input signal VIPOutput of A1 and R1And R2Is connected to the inverting input of A1 and R1And the other end of (1) and R7Are connected at one end to R2And the other end of (a) with the inverting input of A3 and R3Are connected at one end to R3And the other end of the same is connected with the in-phase output end of A3 to generate an amplified in-phase output signal VOUTPThe non-inverting input of A2 is connected to the inverting input signal VINOutput of A2 and R4And R5Is connected to the inverting input of A2 and R4And the other end of (1) and R7Is connected at the other end to R5And the other end of (a) and the non-inverting input terminal of A3 and R6Are connected at one end to R6Is connected to the inverting output of a3 to produce an amplified inverted output signal VOUTN。
Further, the adjustable resistor array R1～R7The device is formed by connecting a plurality of switch resistors in series, wherein each switch resistor is formed by connecting a high-linearity switch SW and a resistor in parallel; r1And R4、R2And R5、R3And R6The number of the switch resistors connected in series between every two of the switch resistors and the switch time sequence are completely consistent.
Further, the high-linearity switch SW includes 5 switching tubes M1-M5, wherein the source of M1 is connected to the working voltage VDD, the drain of M1 is connected to the source of M2, the drain of M4 and the substrate of M3, the gate of M1 is connected to the gate of M4 and the gate of M5 and connected to the inverted clock signal CLKN, the gate of M2 is connected to the gate of M3 and connected to the same phase clock signal CLKP, and the substrate of M2 is connected to the power voltage VDDThe drain of M2 is connected to the source of M3, the source of M4 and the drain of M5 as one end of SW, the drain of M3 is connected to the source of M5 as the other end of SW, and the drain of M4Substrate and substrate contact power supply ground V of M5SSM1-M3 are PMOS tubes, and M4-M5 are NMOS tubes.
Further, the high-linearity switch SW includes 8 switching tubes M1-M8, wherein the source of M1 is connected to the operating voltage VDD, the drain of M1 is connected to the source of M2, the drain of M8 and the substrate of M3, the gate of M1 is connected to the gate of M8, the gate of M7 and the gate of M6 and connected to the inverted clock signal CLKN, the gate of M2 is connected to the gate of M3, the gate of M4 and the gate of M5 and connected to the inverted clock signal p, the substrate of M2 and the substrate of M4 are connected to the power voltage VDDThe drain of M2 is connected with the source of M3, the source of M8 and the drain of M7 and serves as one end of SW, the drain of M3 is connected with the source of M4, the source of M7 and the drain of M6 and serves as the other end of SW, the drain of M4 is connected with the drain of M5, the source of M6 and the substrate of M7, the substrate of M8, the substrate of M6 and the source of M5 are connected with the power ground VSSM1-M4 are PMOS tubes, and M5-M8 are NMOS tubes.
Further, the first-stage operational amplifiers a1 and a2 and the second-stage operational amplifier A3 comprise:
a constant transconductance input stage for implementing a constant transconductance over a rail-to-rail input range;
a gain amplification stage providing gain amplification to an input signal by a folded cascode structure;
and the cross-coupling output stage provides high-linearity rail-to-rail output through a Double-Push cross-coupling structure.
Further, the two-stage operational amplifier a3 further includes a common mode feedback module for clamping the output voltage of the cross-coupled output stage at a preset value.
Further, the constant transconductance input stage comprises 21 switching tubes MA1～MA5、MC1、MC2、MBA、MBAS、MA1S、MA2S、M1N、M2N、MS1～MS4、M1NS、M2NS, MBN, MBNS, wherein MA3Source and MA4Source electrode, MC2Source electrode, MS2Source electrode and MS4Connected in parallel with a supply voltage VDD，MA4Gate of and MA2Drain electrode of (1), MA1Drain electrode of (1), MC1Drain electrode of (1) and MA3Connected to the drain, MA2Grid and M2N gate and MS3Connected as the inverting input of the operational amplifier, MA1Grid and M1N gate and MS1Connected as the non-inverting input of an operational amplifier, MC1Is connected with the grid of the MBA, the grid of the MBN and the grid of the MBNS and is connected with the reverse bias voltage VBN1，MA1Source and MA2Is connected to the drain of MBA, the source of MBA is connected to MC1Source electrode of (1), MA5Source of (1), source of MBAS, MS1Drain electrode of (1), source electrode of MBNS, source electrode of MBN, and MS3Is connected in parallel with a power ground VSS，MA4Drain of (3) and gate of MBAS and MA5Is connected to the drain, MC2Gate of and MS2Gate of and MS4Is connected with the grid and connected with the same phase bias voltage VBP1，MC2Drain electrode of (1) and MA1Source of S, MA2The source of S is connected to the drain of MBAS, MS2Drain electrode of (1) and1NS gate, MA2Grid electrode of S and MS1Are connected to the source of, MS4Drain electrode of (1) and2NS gate, MA1Grid electrode of S and MS3Is connected to the source of MA1Drain of S and M1Drain of NS and M1N is connected at its drain to the inverting output of the input stage, MA2Drain of S and M2Drain of NS and M2N drain connected as non-inverting output of input stage, M1Source and M of NS2Source of NS and drain of MBNS, M1Source of N and M2Source of N and drain of MBN are connected, MA3、MA4、MC2And MS1～MS4Is a PMOS tube, MA1、MA2、MA5、MC1、MA1S、MA2S、MBA、MBAS、M1NS、M2NS、MBN、MBNS、M1N and M2N is an NMOS tube.
Furthermore, the gain amplification stage in the first-stage operational amplifiers A1 and A2 comprises 10 switching tubes N1-N10, wherein the source of N7 is connected with the source of N8 and connected in parallel with a power supply voltage VDDThe gate of N7 is connected to the gate of N8 and is connected to a phase bias voltage VBP1The drain of N7 is connected with the source of N5 and connected with the inverting output end of the input stage, the drain of N8 is connected with the source of N6 and connected with the non-inverting output end of the input stage, the gate of N5 is connected with the gate of N6 and connected with the non-inverting bias voltage VBP2The drain of N5 is connected with the drain of N3, the gate of N1 and the gate of N2, the drain of N6 is connected with the drain and the gate of N9 to be used as the output port Z1 of the amplification stage, the source of N9 is connected with the source of N10 to be used as the output port Z2 of the amplification stage, the drain of N4 is connected with the drain and the gate of N10 to be used as the output port Z3 of the amplification stage, the gate of N3 is connected with the gate of N4 and connected with the reverse bias voltage VBN2The source of N3 is connected with the drain of N1, the source of N4 is connected with the drain of N2, the source of N1 is connected with the source of N2 and connected with the power ground VSSN1-N4 and N9 are NMOS transistors, and N5-N8 and N10 are PMOS transistors.
Furthermore, the gain amplification stage in the two-stage operational amplifier A3 comprises 14 switching tubes P1-P14, wherein the source of P7 is connected with the source of P8 and connected with the power supply voltage VDDThe gate of P7 is connected to the gate of P8 and is connected to a phase bias voltage VBP1The drain of P7 is connected to the source of P5 and connected in parallel with the inverting output terminal of the input stage, the drain of P8 is connected to the source of P6 and connected in parallel with the non-inverting output terminal of the input stage, the gate of P5 is connected to the gate of P6 and connected in parallel with the non-inverting bias voltage VBP2The drain of P5 is connected with the drain and the gate of P9 to serve as the in-phase output port ZP1 of the amplification stage, the source of P9 is connected with the source of P10 to serve as the in-phase output port ZP2 of the amplification stage, the drain of P13 is connected with the drain and the gate of P10 to serve as the in-phase output port ZP3 of the amplification stage, the drain of P6 is connected with the drain and the gate of P11 to serve as the reverse-phase output port ZN1 of the amplification stage, the source of P11 is connected with the source of P12 to serve as the reverse-phase output port ZN2 of the amplification stage, the drain of P14 is connected with the drain and the gate of P12 to serve as the reverse-phase output port ZN3 of the amplification stage, the gate of P13 is connected with the gate of P14 to serve as the reverse-phase bias electric sourcePressing VBN2The source of P13 is connected to the drain of P1 and the drain of P3, the source of P14 is connected to the drain of P2 and the drain of P4, the gate of P3 is connected to the gate of P4 and connected to the common mode feedback voltage VCFBThe gate of P1 is connected to the gate of P1 and has an inverted bias voltage VBN1The source of P1 is connected to the source of P2, P3 and P4 in parallel to power ground VSSP1-P4, P9, P11, P13 and P14 are NMOS tubes, and P5-P8, P10 and P12 are PMOS tubes.
Further, the cross-coupled output stage in the first-stage operational amplifier a1 and a2 includes a Double-Push circuit module, the cross-coupled output stage in the second-stage operational amplifier A3 includes two differential Double-Push circuit modules, the Double-Push circuit module includes a resistor R, a capacitor C and 18 switching tubes M11-M28, wherein a source of M12 is connected with a source of M14, a source of M15, a source of M20, a source of M22 and a source of M28, and is connected with a power supply voltage V in parallelDDThe grid of M12 is connected with the grid of M11 and one end of a resistor R and is connected with output ports Z2, ZN2 or ZP2 of the amplifier stage in parallel, the drain of M12 is connected with the drain of M11, the drain and the grid of M13, the drain and the grid of M14, the source of M25 and the source of M26 are connected, the source of M11 is connected with the source of M13, the source of M16, the source of M19, the source of M21 and the source of M27 and is connected with a power ground VSSThe grid of M15 is connected with output ports Z1, ZN1 or ZP1 of the amplification stage, the grid of M16 is connected with output ports Z3, ZN3 or ZP3 of the amplification stage, the source of M15 is connected with the source of M18, the source of M17 is connected with the source of M16, the drain of M17 is connected with the grid of M28 and the grid and the drain of M20, the grid of M22 is connected with a same-phase bias voltage VBP1The gate of M24 is connected to the same phase bias voltage VBP2The gate of M23 is connected to the reverse bias voltage VBN2The gate of M21 is connected to the reverse bias voltage VBN1The drain of M22 is connected with the source of M24, the drain of M24 is connected with the gate of M17 and the gate and drain of M25, the drain of M18 is connected with the gate of M27 and the gate and drain of M19, the drain of M23 is connected with the gate of M18 and the gate and drain of M26, the drain of M21 is connected with the source of M23, the other end of the resistor R is connected with one end of a capacitor C, and the other end of the capacitor C is connected with the drain of M28And the drain of the M27 is connected to serve as the output end of the output stage, M11, M13, M15, M17, M19, M21, M23, M25 and M27 are NMOS tubes, and M12, M14, M16, M18, M20, M22, M24, M26 and M28 are PMOS tubes.
Furthermore, the common mode feedback module comprises 5 switching tubes M49-M53, two resistors R3-R4 and C3-C4, wherein the source of M49 is connected with a power supply voltage VDDThe drain of M49 is connected to the source of M50 and the source of M51, and the gate of M50 is connected to the input common mode voltage VCMThe grid of M51 is connected with one end of a resistor R3, one end of a resistor R4, one end of a capacitor C3 and one end of a capacitor C4, the other end of a resistor R3 is connected with the other end of a capacitor C3 and connected with the in-phase output end of the output stage, the other end of the resistor R4 is connected with the other end of the capacitor C4 and connected with the inverted output end of the output stage, the drain of M50 is connected with the drain and the grid of M52 to generate a common-mode feedback voltage VCFBThe drain of M51 is connected to the drain and gate of M53, the source of M52 is connected to the source of M53 and connected to power ground VSSM49-M51 are PMOS tubes, and M52 and M53 are NMOS tubes.
Based on the technical scheme, the invention has the following beneficial technical effects:
1. the invention can realize the rail-to-rail of the input and output and improve the input swing amplitude of the programmable gain amplifier.
2. The invention can provide constant transconductance, so that the gain is stable under different common-mode input voltages, and the performance of the programmable gain amplifier is stable.
3. The invention can provide certain output driving capability, and can directly provide output signals to the analog-to-digital converter at the rear end without additionally adding a driving module.
4. The invention can be applied to the amplification of high frequency signals, provides low gain error and low harmonic distortion, and can also maintain the performance of low frequency signals.
Drawings
Fig. 1 is a schematic view of a structure of a conventional instrument amplifier.
Fig. 2 is a schematic structural diagram of a high-speed programmable gain amplifier according to the present invention.
Fig. 3 is a schematic structural diagram of an adjustable resistor array.
Fig. 4 is a schematic diagram of a high linearity switch.
Fig. 5 is a schematic diagram of a high linearity switch structure using a deep hydrazine process.
Fig. 6 is a schematic diagram of a constant transconductance input stage.
Fig. 7 is a schematic diagram of simulated waveforms of the input stage transconductance.
Fig. 8 is a schematic structural diagram of a first-stage operational amplifier.
Fig. 9 is a schematic structural diagram of a second stage operational amplifier.
Detailed Description
In order to more specifically describe the present invention, the following detailed description is provided for the technical solution of the present invention with reference to the accompanying drawings and the specific embodiments.
The constant cross-guide rail-to-rail input differential output high-speed programmable gain amplifier adopts an amplifier structure for a similar instrument and realizes gain adjustment through a resistor array network; the amplifier structure for the analog instrument adopts two-stage low-gain wide-bandwidth operational amplifier cascade connection to replace the original one-stage operational amplifier with high-gain wide bandwidth, reduces the design difficulty of single-stage operational amplifier, replaces the original single-end output operational amplifier with the differential output operational amplifier for the second stage, reduces one operational amplifier compared with the instrument amplifier for realizing the same differential output, and simultaneously can ensure that the output common-mode voltage is adjustable, the application occasion is wider, and the application occasion is wider. The two-stage operational amplifier adopts a full N-type input differential pair to replace the original P-N-type input differential pair, thereby avoiding the constant gm influence of the unpaired pair of P-N input pair transistors, and adding a feedforward path elimination module to further reduce the gm deviation value, so that the minimum gm deviation value can reach within 5%; and the two-stage operational amplifier adopts the design of constant gm, so that the performance of the second-stage operational amplifier is not influenced by the output swing of the first-stage operational amplifier, and the stability of the overall performance is improved. The output stage of the first-stage operational amplifier adopts a Double-Push cross coupling structure, so that the driving capability is enhanced, and the influence of resistance switching on the operational amplifier performance is reduced; the second-stage operational amplifier adopts a Double-Push cross coupling structure and adopts a common-mode feedback design to clamp the output voltage to a specified voltage in a common mode, so that differential rail-to-rail output with high linearity and large driving capability is obtained.
The gain amplifier structure of the invention is shown in fig. 2, and comprises equidirectional parallel differential amplifiers (a1 and a2 as a first-stage operational amplifier), a differential input differential output operational amplifier (A3 as a second-stage operational amplifier) and an adjustable resistor array, wherein the equidirectional parallel differential amplifiers (a1 and a2) can provide rail-to-rail input and output, keep constant gm, keep the advantages of high input impedance and strong common-mode rejection capability of an instrument amplifier and the like, and can be used as a single operational amplifier, adjust gain and reduce the design difficulty of operational amplifier bandwidth. The design of rail-to-rail input and constant gm can increase the input signal amplitude and provide relatively stable gain, improve the performance of the whole programmable gain amplifier and because of the input signal VIPAnd VINAll input from the positive end of the operational amplifier, therefore, the influence of certain input offset can be counteracted. The gain provided by the first stage operational amplifier is:
Figure BDA0003123878050000071
the second stage differential input differential output operational amplifier still adopts rail-to-rail input and output and constant gm design, so that the second stage differential input differential output operational amplifier is matched with the output of the first stage, and simultaneously, the condition of output signal topping is reduced; on the other hand, because the programmable gain amplifier is usually connected with the analog-to-digital converter, the design of using "negative resistance" as the driving output avoids the deformation of the output signal when entering the analog-to-digital converter. The gain provided by the second stage operational amplifier is:
Figure BDA0003123878050000072
the adjustable resistor array is used for adjusting the gain of the programmable gain amplifier and is mainly realized by an external coding control switch, and the unit resistance of the adjustable resistor array needs to be too large or too small according to the requirement of the actual gain, so that the influences of phase margin, gain error increase and the like are easily caused; on the other hand, the high linearity control switch can reduce the harmonic influence and improve the performance of the whole amplifier. Thus, the gain of the overall programmable gain amplifier is:
Figure BDA0003123878050000081
wherein: resistors R1, R2, R3 and RgainIs composed of an adjustable resistor array, as shown in FIG. 3, the adjustable resistor array is composed of resistors and switches, and the resistors R1, R2, R3 and R are regulated and controlled by an external coding control switchgainThe resistance value is large, and the gain of the programmable gain amplifier is adjusted. The control switch is implemented by a switch with high linearity, as shown in fig. 4, when the transmission gate is turned off, the tail current source is turned on, the body of M3 is connected with VDD, and when the transmission gate is turned on, the tail current source is turned off, the body of M3 is connected with the S terminal, and this connection mode can keep the on-resistance of the transmission gate constant, thereby reducing the nonlinearity introduced by the switch and improving the linearity. If a deep hydrazine process is used, the switch shown in fig. 5 can be used, compared with fig. 4, a pair of transmission gates is added, and M7 also adopts the same connection method as M3, so that the on-resistance is kept constant, and the nonlinearity introduced by the switch is further reduced.
The traditional rail-to-rail constant gm differential input stage is realized by adopting N-P complementary input pair transistors, constant gm in the common mode input full range is realized by compensating 3 times of input pair tube tail current, but the change of the slew rate SR in the common mode input range is caused by compensating 3 times of tail current in the common mode input stage close to a power rail. Meanwhile, under the influence of process and temperature, the carrier mobility of the N pipe and the P pipe is not matched, so that the gm deviation of about 12 percent can be caused. The constant gm in the invention is realized by adopting the full N-type input geminate transistors, the inherent deviation of the N-P MOS transistor is avoided, the tail current of the input geminate transistors is not required to be compensated, the constant gm and the SR can be realized in the full range of common-mode input, the gm deviation amount is controlled within 5 percent, and the problems of frequency response and attenuation of the common-mode rejection ratio do not exist. As shown in fig. 6, the rail-to-rail common mode input full-range constant gm in the present embodiment is specifically implemented as follows:
when the common mode input is at the near ground stage, the input pair tube M1N、M2N is turned off, the source follower input tubes MS1 and MS2 are turned on, and the other pair of N-type input pair tubes M is lifted1NS、M2Input voltage V of NSi +sh、Vi -sh，M1NS、M2The NS is in the on state. Accordingly, MA in feed-forward path elimination module1、MA2In the off state, thus is in communication with M1NS、M2Input pair pipe MA corresponding to NS1S、MA2S is in off state due to no tail current, and only the input pair tube M is in the interval1NS、M2NS is in on state, providing gm0。
When the common mode input is in the middle stage, the input pair tube M1N、M2N is turned on while M is1NS、M2The NS is also in the on state. Accordingly, MA in feed-forward path elimination module1、MA2Conducting, inputting geminate transistors MA1S、MA2S is started, and since the polarity of the input voltage of the pair tube in the feedforward path elimination module is opposite to that of the main module, the contribution to the output is-gm0For counteracting M1NS、M2Gm contributed by NS to output0The input pair tube M in the interval1N、M2N、M1NS、M2NS is in conducting state, and the pair transistors MA in the feed-forward path elimination module1、MA2、MA1S、MA2S is also turned on, and the transconductance finally contributing to the output is gm0。
When the common mode input is in the stage close to the power supply voltage, M is turned off due to the MS1 and the MS21NS、M2NS is in the on state but does not contribute to the output transconductance. Accordingly, MA in feed-forward path elimination module1、MA2Conducting, inputting geminate transistors MA1S、MA2S is turned on but does not contribute to the gain of the output, and the input pair tube M in the interval1N、M2N，M1NS、M2NS is in conducting state, and the pair transistors MA in the feed-forward path elimination module1、MA2、MA1S、MA2S is also conducted, and the source follower stage is turned off, so that the S is finally conductedTransconductance of output contribution is gm0。
Therefore, the rail-to-rail input stage contributes a constant cross-over to gm over the full range of common mode input voltages0And the slew rate SR remains constant. As shown in fig. 7, the simulation result shows that the input stage transconductance gm deviation is 5.38% at the maximum under the full range of the common mode input.
As shown in fig. 8, the output stage of the present embodiment adopts a Double-Push cross-coupled output stage, which provides a rail-to-rail output swing and has a large driving capability. Compared with the common class-AB output, the differential drive circuit has the advantages that the cross coupling is adopted to provide higher linearity, and the differential drive output end is obtained by using Double-Push, so that higher output current is obtained. As shown in fig. 9, the second stage operational amplifier adopts a Double-Push cross-coupled structure, and adds common mode feedback, so that the output common mode voltage can be clamped to the pointing voltage, and differential rail-to-rail output with high linearity and large driving capability is obtained. The Double-Push cross coupling output stage is specifically realized as follows:
firstly, MOS tubes M9 and M10 copy cascode input stage currents to M15 and M16; MOS tubes M21, M22, M23 and M24 copy a branch current of a cascode, and then copy the branch current to M17 and M18 through M25 and M26; m19 and M20 copy the cross current to output tubes M27 and M28 in proportion to obtain output end current; MOS tubes M11, M12, M13 and M14 form an inverter to obtain a node voltage B which is in phase reversal with the voltage of a point A at the input end of the output stage and obtain the other differential input end of the output stage; finally, the differential input terminal A, B of the output stage amplifies and outputs the signal of the alternating current change, so as to obtain a dynamic output current with larger change.
The embodiments described above are presented to enable a person having ordinary skill in the art to make and use the invention. It will be readily apparent to those skilled in the art that various modifications to the above-described embodiments may be made, and the generic principles defined herein may be applied to other embodiments without the use of inventive faculty. Therefore, the present invention is not limited to the above embodiments, and those skilled in the art should make improvements and modifications to the present invention based on the disclosure of the present invention within the protection scope of the present invention.

Claims (10)

1. A constant cross-guide rail-to-rail input differential output high-speed programmable gain amplifier comprises 7 adjustable resistor arrays R1～R72 one-level operational amplifiers A1 and A2 and the two-level operational amplifier A3 of differential output, its characterized in that: the non-inverting input end of A1 receives a non-inverting input signal VIPOutput of A1 and R1And R2Is connected to the inverting input of A1 and R1And the other end of (1) and R7Are connected at one end to R2And the other end of (a) with the inverting input of A3 and R3Are connected at one end to R3And the other end of the same is connected with the in-phase output end of A3 to generate an amplified in-phase output signal VOUTPThe non-inverting input of A2 is connected to the inverting input signal VINOutput of A2 and R4And R5Is connected to the inverting input of A2 and R4And the other end of (1) and R7Is connected at the other end to R5And the other end of (a) and the non-inverting input terminal of A3 and R6Are connected at one end to R6Is connected to the inverting output of a3 to produce an amplified inverted output signal VOUTN。
2. The high speed programmable gain amplifier of claim 1, wherein: the adjustable resistor array R1～R7The device is formed by connecting a plurality of switch resistors in series, wherein each switch resistor is formed by connecting a high-linearity switch SW and a resistor in parallel; r1And R4、R2And R5、R3And R6The number of the switch resistors connected in series between every two of the switch resistors and the switch time sequence are completely consistent.
3. The high speed programmable gain amplifier of claim 2, wherein: the high-linearity switch SW comprises 5 switch tubes M1-M5, wherein a source electrode of M1 is connected with a working voltage VDD, a drain electrode of M1 is connected with a source electrode of M2, a drain electrode of M4 and a substrate of M3, a grid electrode of M1 is connected with a grid electrode of M4 and a grid electrode of M5 and connected with an inverted clock signal CLKN, a grid electrode of M2 is connected with a grid electrode of M3 and connected with a CLKNA substrate-to-power supply voltage V connected to the in-phase clock signal CLKP, M2DDThe drain of M2 is connected with the source of M3, the source of M4 and the drain of M5 and serves as one end of SW, the drain of M3 is connected with the source of M5 and serves as the other end of SW, and the substrate of M4 and the substrate of M5 are connected with a power ground VSSM1-M3 are PMOS tubes, and M4-M5 are NMOS tubes.
4. The high speed programmable gain amplifier of claim 2, wherein: the high-linearity switch SW comprises 8 switch tubes M1-M8, wherein a source electrode of M1 is connected with a working voltage VDD, a drain electrode of M1 is connected with a source electrode of M2, a drain electrode of M8 and a substrate of M3, a grid electrode of M1 is connected with a grid electrode of M8, a grid electrode of M7 and a grid electrode of M6 and connected with an inverted clock signal CLKN, a grid electrode of M2 is connected with a grid electrode of M3, a grid electrode of M4 and a grid electrode of M5 and connected with an inverted clock signal CLKP, a substrate of M2 and a substrate of M4 are connected with a power supply voltage VDDThe drain of M2 is connected with the source of M3, the source of M8 and the drain of M7 and serves as one end of SW, the drain of M3 is connected with the source of M4, the source of M7 and the drain of M6 and serves as the other end of SW, the drain of M4 is connected with the drain of M5, the source of M6 and the substrate of M7, the substrate of M8, the substrate of M6 and the source of M5 are connected with the power ground VSSM1-M4 are PMOS tubes, and M5-M8 are NMOS tubes.
5. The high speed programmable gain amplifier of claim 1, wherein: the first-level operational amplifier A1 and A2 and the second-level operational amplifier A3 comprise:
a constant transconductance input stage for implementing a constant transconductance over a rail-to-rail input range;
a gain amplification stage providing gain amplification to an input signal by a folded cascode structure;
the cross coupling output stage provides high-linearity rail-to-rail output through a Double-Push cross coupling structure;
the secondary operational amplifier a3 also includes a common mode feedback module for clamping the output voltage of the cross-coupled output stages at a preset value.
6. The high speed programmable gain amplifier of claim 5, wherein: the constant transconductance input stage comprises 21 switching tubes MA1～MA5、MC1、MC2、MBA、MBAS、MA1S、MA2S、M1N、M2N、MS1～MS4、M1NS、M2NS, MBN, MBNS, wherein MA3Source and MA4Source electrode, MC2Source electrode, MS2Source electrode and MS4Connected in parallel with a supply voltage VDD，MA4Gate of and MA2Drain electrode of (1), MA1Drain electrode of (1), MC1Drain electrode of (1) and MA3Connected to the drain, MA2Grid and M2N gate and MS3Connected as the inverting input of the operational amplifier, MA1Grid and M1N gate and MS1Connected as the non-inverting input of an operational amplifier, MC1Is connected with the grid of the MBA, the grid of the MBN and the grid of the MBNS and is connected with the reverse bias voltage VBN1，MA1Source and MA2Is connected to the drain of MBA, the source of MBA is connected to MC1Source electrode of (1), MA5Source of (1), source of MBAS, MS1Drain electrode of (1), source electrode of MBNS, source electrode of MBN, and MS3Is connected in parallel with a power ground VSS，MA4Drain of (3) and gate of MBAS and MA5Is connected to the drain, MC2Gate of and MS2Gate of and MS4Is connected with the grid and connected with the same phase bias voltage VBP1，MC2Drain electrode of (1) and MA1Source of S, MA2The source of S is connected to the drain of MBAS, MS2Drain electrode of (1) and1NS gate, MA2Grid electrode of S and MS1Are connected to the source of, MS4Drain electrode of (1) and2NS gate, MA1Grid electrode of S and MS3Is connected to the source of MA1Drain of S and M1Drain of NS and M1N is connected at its drain to the inverting output of the input stage, MA2Drain of S and M2Leakage of NSElectrode and M2N drain connected as non-inverting output of input stage, M1Source and M of NS2Source of NS and drain of MBNS, M1Source of N and M2Source of N and drain of MBN are connected, MA3、MA4、MC2And MS1～MS4Is a PMOS tube, MA1、MA2、MA5、MC1、MA1S、MA2S、MBA、MBAS、M1NS、M2NS、MBN、MBNS、M1N and M2N is an NMOS tube.
7. The high speed programmable gain amplifier of claim 5, wherein: the gain amplification stage in the first-stage operational amplifiers A1 and A2 comprises 10 switching tubes N1-N10, wherein the source electrode of N7 is connected with the source electrode of N8 and connected in parallel with a power supply voltage VDDThe gate of N7 is connected to the gate of N8 and is connected to a phase bias voltage VBP1The drain of N7 is connected with the source of N5 and connected with the inverting output end of the input stage, the drain of N8 is connected with the source of N6 and connected with the non-inverting output end of the input stage, the gate of N5 is connected with the gate of N6 and connected with the non-inverting bias voltage VBP2The drain of N5 is connected with the drain of N3, the gate of N1 and the gate of N2, the drain of N6 is connected with the drain and the gate of N9 to be used as the output port Z1 of the amplification stage, the source of N9 is connected with the source of N10 to be used as the output port Z2 of the amplification stage, the drain of N4 is connected with the drain and the gate of N10 to be used as the output port Z3 of the amplification stage, the gate of N3 is connected with the gate of N4 and connected with the reverse bias voltage VBN2The source of N3 is connected with the drain of N1, the source of N4 is connected with the drain of N2, the source of N1 is connected with the source of N2 and connected with the power ground VSSN1-N4 and N9 are NMOS transistors, and N5-N8 and N10 are PMOS transistors.
8. The high speed programmable gain amplifier of claim 5, wherein: the gain amplifier stage in the two-stage operational amplifier A3 comprises 14 switching tubes P1-P14, wherein the source electrode of P7 is connected with the source electrode of P8 and connected with a power supply voltage V in parallelDDThe gate of P7 is connected to the gate of P8 and is connected to a phase biasPressure VBP1The drain of P7 is connected to the source of P5 and connected in parallel with the inverting output terminal of the input stage, the drain of P8 is connected to the source of P6 and connected in parallel with the non-inverting output terminal of the input stage, the gate of P5 is connected to the gate of P6 and connected in parallel with the non-inverting bias voltage VBP2The drain of P5 is connected with the drain and gate of P9 as the in-phase output port ZP1 of the amplifier stage, the source of P9 is connected with the source of P10 as the in-phase output port ZP2 of the amplifier stage, the drain of P13 is connected with the drain and gate of P10 as the in-phase output port ZP3 of the amplifier stage, the drain of P6 is connected with the drain and gate of P11 as the out-phase output port ZN1 of the amplifier stage, the source of P11 is connected with the source of P12 as the out-phase output port ZN2 of the amplifier stage, the drain of P14 is connected with the drain and gate of P12 as the out-phase output port ZN3 of the amplifier stage, the gate of P13 is connected with the gate of P14 and connected with the reverse bias voltage VBN 32The source of P13 is connected to the drain of P1 and the drain of P3, the source of P14 is connected to the drain of P2 and the drain of P4, the gate of P3 is connected to the gate of P4 and connected to the common mode feedback voltage VCFBThe gate of P1 is connected to the gate of P1 and has an inverted bias voltage VBN1The source of P1 is connected to the source of P2, P3 and P4 in parallel to power ground VSSP1-P4, P9, P11, P13 and P14 are NMOS tubes, and P5-P8, P10 and P12 are PMOS tubes.
9. The high speed programmable gain amplifier of claim 5, wherein: the cross-coupled output stage in the first-stage operational amplifier A1 and A2 comprises a Double-Push circuit module, the cross-coupled output stage in the second-stage operational amplifier A3 comprises two differential Double-Push circuit modules, the Double-Push circuit module comprises a resistor R, a capacitor C and 18 switching tubes M11-M28, wherein a source electrode of M12 is connected with a source electrode of M14, a source electrode of M15, a source electrode of M20, a source electrode of M22 and a source electrode of M28 and connected with a power supply voltage V in parallelDDThe grid of M12 is connected with the grid of M11 and one end of a resistor R and is connected with output ports Z2, ZN2 or ZP2 of the amplifier stage in parallel, the drain of M12 is connected with the drain of M11, the drain and the grid of M13, the drain and the grid of M14, the source of M25 and the source of M26, the source of M11 is connected with the source of M13,The source of M16, the source of M19, the source of M21 and the source of M27 are connected in parallel to a power ground VSSThe grid of M15 is connected with output ports Z1, ZN1 or ZP1 of the amplification stage, the grid of M16 is connected with output ports Z3, ZN3 or ZP3 of the amplification stage, the source of M15 is connected with the source of M18, the source of M17 is connected with the source of M16, the drain of M17 is connected with the grid of M28 and the grid and the drain of M20, the grid of M22 is connected with a same-phase bias voltage VBP1The gate of M24 is connected to the same phase bias voltage VBP2The gate of M23 is connected to the reverse bias voltage VBN2The gate of M21 is connected to the reverse bias voltage VBN1The drain of M22 is connected with the source of M24, the drain of M24 is connected with the gate of M17 and the gate and drain of M25, the drain of M18 is connected with the gate of M27 and the gate and drain of M19, the drain of M23 is connected with the gate of M18 and the gate and drain of M26, the drain of M21 is connected with the source of M23, the other end of resistor R is connected with one end of capacitor C, the other end of capacitor C is connected with the drain of M28 and the drain of M27 to serve as the output end of the output stage, M11, M13, M15, M17, M19, M21, M23, M25 and M27 are NMOS tubes, M12, M14, M16, M18, M20, M22, M24, M26 and M28 are PMOS tubes.
10. The high speed programmable gain amplifier of claim 5, wherein: the common mode feedback module comprises 5 switching tubes M49-M53, two resistors R3-R4 and C3-C4, wherein the source of M49 is connected with a power supply voltage VDDThe drain of M49 is connected to the source of M50 and the source of M51, and the gate of M50 is connected to the input common mode voltage VCMThe grid of M51 is connected with one end of a resistor R3, one end of a resistor R4, one end of a capacitor C3 and one end of a capacitor C4, the other end of a resistor R3 is connected with the other end of a capacitor C3 and connected with the in-phase output end of the output stage, the other end of the resistor R4 is connected with the other end of the capacitor C4 and connected with the inverted output end of the output stage, the drain of M50 is connected with the drain and the grid of M52 to generate a common-mode feedback voltage VCFBThe drain of M51 is connected to the drain and gate of M53, the source of M52 is connected to the source of M53 and connected to power ground VSSM49-M51 are PMOS tubes, and M52 and M53 are NMOS tubes.
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