CN111431490B - Fully differential amplifier for pipelined ADC - Google Patents
Fully differential amplifier for pipelined ADC Download PDFInfo
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- CN111431490B CN111431490B CN202010382472.3A CN202010382472A CN111431490B CN 111431490 B CN111431490 B CN 111431490B CN 202010382472 A CN202010382472 A CN 202010382472A CN 111431490 B CN111431490 B CN 111431490B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection
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Abstract
The invention discloses a fully differential amplifier for a pipelined ADC, comprising: the differential amplifier comprises a voltage bias circuit, a differential amplifier body circuit and a switched capacitor common mode feedback circuit; through the fully differential structural design of the differential amplifier body circuit, the signal to noise ratio is improved, the requirement of gain bandwidth product is reduced, and therefore the power consumption is reduced, and the energy is saved; providing common mode feedback for the differential amplifier body circuit through the switch capacitor common mode feedback circuit, so that the differential amplifier body circuit has high gain; providing a stable voltage bias for the differential amplifier body circuit through the voltage bias circuit; compared with the prior art, the device has the advantages of large input swing range, large output swing range and high linearity.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to a fully differential amplifier for a pipelined ADC.
Background
In response to the increasing speed and resolution requirements, pipelined analog-to-digital converters (analogtodigitalconverter, ADC) convert signals in bit-wise (bits) parallel in a manner similar to a factory pipeline, such that the conversion rate is primarily dependent on single stage speed, and resolution is primarily dependent on number of stages, thereby greatly increasing speed and resolution, and having great development prospects.
The pipelined ADC includes a plurality of stages (stages), the last stage typically being formed of a common flash ADC circuit, the hardware configuration of the first stages being identical, including: a sub ADC and a gain digital to analog conversion unit (MDAC). The MDAC is composed of a sub DAC and a residual amplifier controlled by two non-overlapped sampling hold signals (including a sampling phase clock signal and an amplifying phase clock signal). The existing residual amplifier generally uses a closed-loop single-ended amplifier, and in order to meet the requirement of high speed and high precision of the ADC, a large gain bandwidth product is required, so that the power consumption is increased. In the process of improving the gain, a two-stage sleeve type design or a folding type design structure based on a switch capacitor is generally adopted, and the structure is mainly characterized in that more transistors are stacked in the vertical direction, so that the requirement on the power supply voltage is higher, and the problem of small swing range is not negligible; at present, a method for improving gain by using positive feedback is also available, for example, a negative resistance type positive feedback high-gain operational amplifier formed by locally adopting an NMOS tube in a cross-coupled diode connection mode is proposed in a university of eastern and south China patent CN109474249A, however, in actual production, due to the existence of CMOS process deviation, an accurate and invariable negative resistance is difficult to obtain in reality, so that a positive feedback technology in a real environment can only be used as a thought to be developed, and engineering is not robust.
Disclosure of Invention
Aiming at the defects in the prior art, the fully differential amplifier for the pipelined ADC solves the problems of small swing range, poor robustness and high power consumption existing in the existing implementation scheme of the residual amplifier in the pipelined ADC.
In order to achieve the aim of the invention, the invention adopts the following technical scheme: a fully differential amplifier for a pipelined ADC, comprising: the differential amplifier comprises a voltage bias circuit, a differential amplifier body circuit and a switched capacitor common mode feedback circuit;
The voltage bias circuit is respectively connected with the differential amplifier body circuit and the switched capacitor common mode feedback circuit;
the switch capacitor common mode feedback circuit is connected with the differential amplifier body circuit;
The voltage bias circuit is used for providing bias voltage for the differential amplifier body circuit;
The differential amplifier body circuit is used for amplifying an input signal in a differential form;
the switched capacitor common mode feedback circuit is used for providing common mode feedback for the differential amplifier body circuit.
Further, the voltage bias circuit includes: the CMOS current source circuit, the NMOS tube M1, the NMOS tube M2, the NMOS tube M3, the NMOS tube M4, the PMOS tube M5, the PMOS tube M6 and the PMOS tube M7;
The grid electrode of the NMOS tube M1 is respectively connected with the grid electrode of the NMOS tube M4, the grid electrode of the PMOS tube M5 and the grid electrode of the PMOS tube M7, and is used as a common-mode voltage reference input end Vcm of the fully differential amplifier; the current output end of the CMOS current source circuit is respectively connected with the drain electrode of the NMOS tube M1, the grid electrode of the NMOS tube M2 and the grid electrode of the NMOS tube M3 and is used as a second voltage bias signal output end of the voltage bias circuit; the drain electrode of the NMOS tube M2 is connected with the source electrode of the NMOS tube M1, and the source electrode of the NMOS tube M1 is grounded; the source electrode of the NMOS tube M3 is grounded, and the drain electrode of the NMOS tube M3 is connected with the source electrode of the NMOS tube M4; the drain electrode of the NMOS tube M4 is respectively connected with the drain electrode of the PMOS tube M5 and the grid electrode of the PMOS tube M6 and is used as a first voltage bias signal output end of the voltage bias circuit; the source electrode of the PMOS tube M5 is connected with the drain electrode of the PMOS tube M6; the source electrode of the PMOS tube M6 is connected with the drain electrode of the PMOS tube M7; the source electrode of the PMOS tube M7 and the power supply end of the CMOS current source circuit are connected with a direct current power supply VDD; the common ground of the CMOS current source circuits is grounded.
Further, the CMOS current source circuit includes: PMOS tube M27, NMOS tube M28, PMOS tube M29, NMOS tube M30, grounding resistor R3 and PMOS tube M31;
The source electrode of the PMOS tube M27 is respectively connected with the drain electrode of the PMOS tube M29 and the drain electrode of the PMOS tube M31 and is used as a power supply end, the grid electrode of the PMOS tube M29, the drain electrode of the NMOS tube M30 and the grid electrode of the PMOS tube M31 are respectively connected, and the drain electrode of the PMOS tube M28, the grid electrode of the NMOS tube M28 and the grid electrode of the NMOS tube M30 are respectively connected; the source electrode of the NMOS tube M30 is connected with a grounding resistor R3; the source electrode of the NMOS tube M28 is grounded; the drain electrode of the PMOS tube M31 is used as the current output end of the CMOS current source circuit.
The beneficial effects of the above-mentioned further scheme are: through the connection relation of the specific PMOS tube and the NMOS tube, a current source irrelevant to the power supply voltage is realized, the influence of the power supply voltage and the power supply noise is avoided, and the robustness to the power supply is high.
Further, the differential amplifier body circuit includes: PMOS tube M8, NMOS tube M9, PMOS tube M11, resistor R1, NMOS tube M10, PMOS tube M12, NMOS tube M13, PMOS tube M14, NMOS tube M15, PMOS tube M16, PMOS tube M17, PMOS tube M18, NMOS tube M19, NMOS tube M20, NMOS tube M21, PMOS tube M22, resistor R2, PMOS tube M23, NMOS tube M24 and first switch circuit;
the drain electrode of the PMOS tube M8 is connected with the drain electrode of the NMOS tube M9 and is used as a differential signal inversion output end Vout-; the source electrode of the NMOS tube M9 is grounded, and the grid electrode of the NMOS tube M9 is respectively connected with one end of the resistor R1 and the drain electrode of the NMOS tube M10; the source electrode of the PMOS tube M8 is respectively connected with the source electrode of the PMOS tube M11, the source electrode of the PMOS tube M17, the source electrode of the PMOS tube M18, the source electrode of the PMOS tube M22, the source electrode of the PMOS tube M23 and the power supply end of the first switch circuit, and is used as the power supply end of the differential amplifier body circuit to be connected with the direct current power supply VDD, and the grid electrode of the differential amplifier body circuit is respectively connected with the other end of the resistor R1 and the drain electrode of the PMOS tube M11; the grid electrode of the NMOS tube M10 is respectively connected with the grid electrode of the PMOS tube M11, the drain electrode of the PMOS tube M12, the drain electrode of the NMOS tube M13 and the grid electrode of the PMOS tube M17, and the source electrode of the NMOS tube M is grounded; the grid electrode of the PMOS tube M12 is connected with the grid electrode of the NMOS tube M13 and is used as a differential signal non-inverting input end vin+ of the fully differential amplifier, and the source electrode of the PMOS tube M12 is respectively connected with the drain electrode of the PMOS tube M14 and the source electrode of the PMOS tube M16; the source electrode of the NMOS tube M13 is respectively connected with the drain electrode of the NMOS tube M19, the drain electrode of the NMOS tube M20 and the source electrode of the NMOS tube M15; the grid electrode of the NMOS tube M19 is used as a second voltage bias signal input end of the differential amplifier body circuit, and the source electrode of the NMOS tube M19 is respectively connected with the source electrode of the NMOS tube M20 and the communication end 1 of the first switch circuit; the second voltage bias signal input end of the differential amplifier body circuit is connected with the second voltage bias signal output end of the voltage bias circuit; the grid electrode of the NMOS tube M20 is used as a tail current control end of the differential amplifier body circuit; the grid electrode of the PMOS tube M16 is used as a first voltage bias signal input end of the differential amplifier body circuit, and the source electrode of the PMOS tube M16 is respectively connected with the drain electrode of the PMOS tube M17 and the drain electrode of the PMOS tube M18; the first voltage bias signal input end of the differential amplifier body circuit is connected with the first voltage bias signal output end of the voltage bias circuit; the drain electrode of the PMOS tube M14 is respectively connected with the grid electrode of the PMOS tube M18, the drain electrode of the NMOS tube M15, the grid electrode of the PMOS tube M22 and the grid electrode of the NMOS tube M21, and the grid electrode of the PMOS tube M14 is connected with the grid electrode of the NMOS tube M15 and is used as a differential signal inverting input end Vin-of the fully differential amplifier; the drain electrode of the NMOS tube M21 is respectively connected with one end of the resistor R2 and the grid electrode of the NMOS tube M24, and the source electrode of the NMOS tube M24 is connected with the source electrode of the NMOS tube M24 and grounded; the drain electrode of the PMOS tube M22 is respectively connected with the other end of the resistor R2 and the grid electrode of the PMOS tube M23; the drain electrode of the NMOS tube M24 is connected with the drain electrode of the PMOS tube M23 and is used as a differential signal in-phase output end Vout+ of the fully differential amplifier; the communication end 2 of the first switch circuit is grounded, the control end 3 of the first switch circuit is used as an enabling clock signal input end of the fully differential amplifier, and the common end of the first switch circuit is grounded.
Further, the switched capacitor common mode feedback circuit comprises: the second switch circuit, the third switch circuit, the fourth switch circuit, the fifth switch circuit, the sixth switch circuit, the capacitor C1, the capacitor C2, the PMOS tube M25 and the NMOS tube M26;
The control end 3 of the second switch circuit is connected with the control end 3 of the fourth switch circuit, is used as the control end b of the switch capacitor common mode feedback circuit, is also used as an amplified phase clock signal input end of the fully differential amplifier, the communication end 1 of the switch capacitor common mode feedback circuit is respectively connected with the communication end 1 of the third switch circuit and one end of the capacitor C1, and the communication end 2 of the switch capacitor common mode feedback circuit is used as the communication end d of the switch capacitor common mode feedback circuit and is connected with the differential signal inverting output end Vout-of the fully differential amplifier; the control end 3 of the third switching circuit is connected with the grid electrode of the PMOS tube M25, the grid electrode of the NMOS tube M26 and the control end 3 of the fifth switching circuit, and is used as the control end a of the switched capacitor common mode feedback circuit, and is also used as the sampling phase clock signal input end of the fully differential amplifier, the communication end 2 of the third switching circuit is connected with the communication end 1 of the fifth switching circuit, and is used as the communication end g of the switched capacitor common mode feedback circuit to be connected with the common mode voltage reference input end Vcm; the communication end 2 of the fourth switching circuit is respectively connected with one end of the capacitor C2 and the communication end 2 of the fifth switching circuit, and the communication end 1 is used as the communication end C of the switched capacitor common mode feedback circuit and is connected with the differential signal in-phase output end Vout+ of the fully differential amplifier; the communication end 1 of the sixth switching circuit is respectively connected with the other end of the capacitor C1 and the other end of the capacitor C2, and is used as a communication end e of the switched capacitor common mode feedback circuit to be connected with a tail current control end of the differential amplifier body circuit, the control end 3 of the sixth switching circuit is respectively connected with the drain electrode of the PMOS tube M25 and the drain electrode of the NMOS tube M26, and the communication end 2 is used as a communication end f of the switched capacitor common mode feedback circuit to be connected with a second voltage bias signal output end of the voltage bias circuit; the power supply end of the second switch circuit is respectively connected with the power supply end of the third switch circuit, the power supply end of the fourth switch circuit, the power supply end of the fifth switch circuit, the power supply end of the sixth switch circuit and the source electrode of the PMOS tube M25, and is used as the power supply end of the switched capacitor common mode feedback circuit to be connected with the direct current power supply VDD.
Further, the first switch circuit, the second switch circuit, the third switch circuit, the fourth switch circuit, the fifth switch circuit and the sixth switch circuit have the same structure, and each of them includes: PMOS tube Q1, NMOS tube Q2, PMOS tube Q3 and NMOS tube Q4;
The grid electrode of the PMOS tube Q1 is respectively connected with the grid electrode of the NMOS tube Q2 and the grid electrode of the NMOS tube Q4, and is used as a control end 3 of the first switch circuit, the second switch circuit, the third switch circuit, the fourth switch circuit, the fifth switch circuit and the sixth switch circuit, the source electrode of the PMOS tube Q1 is used as a power supply end of the first switch circuit, the second switch circuit, the third switch circuit, the fourth switch circuit, the fifth switch circuit and the sixth switch circuit, and the drain electrode of the PMOS tube Q3 is respectively connected with the drain electrode of the NMOS tube Q2 and the grid electrode of the PMOS tube Q3; the drain electrode of the PMOS tube Q3 is connected with the source electrode of the NMOS tube Q4, and is used as a communication end 1 of the first switch circuit, the second switch circuit, the third switch circuit, the fourth switch circuit, the fifth switch circuit and the sixth switch circuit, and the source electrode of the PMOS tube Q3 is connected with the drain electrode of the NMOS tube Q4 and is used as a communication end 2 of the first switch circuit, the second switch circuit, the third switch circuit, the fourth switch circuit, the fifth switch circuit and the sixth switch circuit.
The beneficial effects of the above-mentioned further scheme are: the first to sixth switching circuits are designed in a complementary mode through the PMOS tube and the NMOS tube, so that the switching circuits can be effectively conducted when the switching circuits are required to be conducted, and ideal switching characteristics are always achieved.
Further, the fully differential amplifier for pipelined ADC is fabricated using SMIC130nm integrated circuit technology.
The beneficial effects of the invention are as follows: through the fully differential structural design of the differential amplifier body circuit, the signal to noise ratio is improved, the requirement of gain bandwidth product is reduced, and therefore the power consumption is reduced, and the energy is saved; providing common mode feedback for the differential amplifier body circuit through the switch capacitor common mode feedback circuit, so that the differential amplifier body circuit has high gain; providing a stable voltage bias for the differential amplifier body circuit through the voltage bias circuit; compared with the prior art, the device has the advantages of large input swing range, large output swing range and high linearity.
Drawings
FIG. 1 is a circuit diagram of a fully differential amplifier for a pipelined ADC;
FIG. 2 is a circuit diagram of a CMOS current source;
FIG. 3 is a schematic diagram of a switched capacitor common mode feedback circuit;
fig. 4 is a switching circuit diagram.
Detailed Description
The following description of the embodiments of the present invention is provided to facilitate understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and all the inventions which make use of the inventive concept are protected by the spirit and scope of the present invention as defined and defined in the appended claims to those skilled in the art.
As shown in fig. 1, in one embodiment of the present invention, a fully differential amplifier for a pipelined ADC comprises: the differential amplifier comprises a voltage bias circuit, a differential amplifier body circuit and a switched capacitor common mode feedback circuit;
The voltage bias circuit is respectively connected with the differential amplifier body circuit and the switched capacitor common mode feedback circuit;
the switch capacitor common mode feedback circuit is connected with the differential amplifier body circuit;
The voltage bias circuit is used for providing bias voltage for the differential amplifier body circuit;
The differential amplifier body circuit is used for amplifying an input signal in a differential form;
the switched capacitor common mode feedback circuit is used for providing common mode feedback for the differential amplifier body circuit.
The fully differential amplifier is processed by adopting an SMIC130nm integrated circuit process, and in the field, a current signal flowing between a drain electrode and a source electrode of the MOS tube is often referred to as drain-source current, and a voltage signal applied to a grid electrode of the MOS tube is also often referred to as grid voltage.
As shown in fig. 1, the voltage bias circuit includes: the CMOS current source circuit, the NMOS tube M1, the NMOS tube M2, the NMOS tube M3, the NMOS tube M4, the PMOS tube M5, the PMOS tube M6 and the PMOS tube M7;
The grid electrode of the NMOS tube M1 is respectively connected with the grid electrode of the NMOS tube M4, the grid electrode of the PMOS tube M5 and the grid electrode of the PMOS tube M7, and is used as a common-mode voltage reference input end Vcm of the fully differential amplifier; the current output end of the CMOS current source circuit is respectively connected with the drain electrode of the NMOS tube M1, the grid electrode of the NMOS tube M2 and the grid electrode of the NMOS tube M3 and is used as a second voltage bias signal output end of the voltage bias circuit; the drain electrode of the NMOS tube M2 is connected with the source electrode of the NMOS tube M1, and the source electrode of the NMOS tube M1 is grounded; the source electrode of the NMOS tube M3 is grounded, and the drain electrode of the NMOS tube M3 is connected with the source electrode of the NMOS tube M4; the drain electrode of the NMOS tube M4 is respectively connected with the drain electrode of the PMOS tube M5 and the grid electrode of the PMOS tube M6 and is used as a first voltage bias signal output end of the voltage bias circuit; the source electrode of the PMOS tube M5 is connected with the drain electrode of the PMOS tube M6; the source electrode of the PMOS tube M6 is connected with the drain electrode of the PMOS tube M7; the source electrode of the PMOS tube M7 and the power supply end of the CMOS current source circuit are connected with a direct current power supply VDD; the common ground of the CMOS current source circuits is grounded.
As shown in fig. 2, the CMOS current source circuit includes: PMOS tube M27, NMOS tube M28, PMOS tube M29, NMOS tube M30, grounding resistor R3 and PMOS tube M31;
The source electrode of the PMOS tube M27 is respectively connected with the drain electrode of the PMOS tube M29 and the drain electrode of the PMOS tube M31 and is used as a power supply end, the grid electrode of the PMOS tube M29, the drain electrode of the NMOS tube M30 and the grid electrode of the PMOS tube M31 are respectively connected, and the drain electrode of the PMOS tube M28, the grid electrode of the NMOS tube M28 and the grid electrode of the NMOS tube M30 are respectively connected; the source electrode of the NMOS tube M30 is connected with a grounding resistor R3; the source electrode of the NMOS tube M28 is grounded; the drain electrode of the PMOS tube M31 is used as the current output end of the CMOS current source circuit.
In the field of integrated circuits, the connection of the grid electrode and the drain electrode of the MOS tube is a diode connection method of the MOS tube, at the moment, the MOS tube is always locked in a saturation region and is in a saturated conduction state because the electric potential of the drain electrode and the grid electrode of the MOS tube is the same, and the grid voltage can be controlled by regulating the electric potential of the drain electrode and the source electrode because the characteristic relation between the grid voltage and the drain electrode current of the saturation region of the MOS tube is only related to the technological characteristics of the MOS tube. The PMOS tube M27 drives the diode-connected NMOS tube M28, the drain-source current of the M28 is controlled by the drain-source current of the M27, and the drain-source current of the M27 is controlled by the grid voltage of the M27, so the grid voltage of the M27 can control the grid voltage of the M28; because the NMOS tube M30 and the PMOS tube M29 connected by the diode are the same mechanism, the grid of the M27 is communicated with the grid of the M29, and the grid of the M28 is communicated with the grid of the M30, a set of grid voltage controlled by drain-source current is formed, and the grid voltage controls the drain-source current and is irrelevant to the power supply voltage; at this time, a voltage difference exists between the source voltage of M30 and the source voltage of M28 through the resistor R3, so that the current value is specifically controlled, under the connection relationship of the present circuit, if the gate oxide width-to-length ratios in the process parameters of M27, M29 and M31 are all the same, and the gate oxide width-to-length ratios of M28 and M30 are all the same, and the value is k, in this embodiment, no matter how much the voltage value of the dc power supply VDD is, the output current of the present circuit is as follows:
Wherein I is a CMOS current source output current value, u n is electron mobility, C ox is a physical process used by the NMOS transistor, namely, the grid oxide layer permittivity of the SMIC130nm integrated circuit process, and R is the resistance value of a resistor R3. Therefore, the invention realizes a current source irrelevant to the power supply voltage through the connection relation of the specific PMOS tube and the NMOS tube, is not influenced by the power supply voltage and the power supply noise, and has high robustness to the power supply.
As shown in fig. 1, the differential amplifier body circuit includes: PMOS tube M8, NMOS tube M9, PMOS tube M11, resistor R1, NMOS tube M10, PMOS tube M12, NMOS tube M13, PMOS tube M14, NMOS tube M15, PMOS tube M16, PMOS tube M17, PMOS tube M18, NMOS tube M19, NMOS tube M20, NMOS tube M21, PMOS tube M22, resistor R2, PMOS tube M23, NMOS tube M24 and first switch circuit;
the drain electrode of the PMOS tube M8 is connected with the drain electrode of the NMOS tube M9 and is used as a differential signal inversion output end Vout-; the source electrode of the NMOS tube M9 is grounded, and the grid electrode of the NMOS tube M9 is respectively connected with one end of the resistor R1 and the drain electrode of the NMOS tube M10; the source electrode of the PMOS tube M8 is respectively connected with the source electrode of the PMOS tube M11, the source electrode of the PMOS tube M17, the source electrode of the PMOS tube M18, the source electrode of the PMOS tube M22, the source electrode of the PMOS tube M23 and the power supply end of the first switch circuit, and is used as the power supply end of the differential amplifier body circuit to be connected with the direct current power supply VDD, and the grid electrode of the differential amplifier body circuit is respectively connected with the other end of the resistor R1 and the drain electrode of the PMOS tube M11; the grid electrode of the NMOS tube M10 is respectively connected with the grid electrode of the PMOS tube M11, the drain electrode of the PMOS tube M12, the drain electrode of the NMOS tube M13 and the grid electrode of the PMOS tube M17, and the source electrode of the NMOS tube M is grounded; the grid electrode of the PMOS tube M12 is connected with the grid electrode of the NMOS tube M13 and is used as a differential signal non-inverting input end vin+ of the fully differential amplifier, and the source electrode of the PMOS tube M12 is respectively connected with the drain electrode of the PMOS tube M14 and the source electrode of the PMOS tube M16; the source electrode of the NMOS tube M13 is respectively connected with the drain electrode of the NMOS tube M19, the drain electrode of the NMOS tube M20 and the source electrode of the NMOS tube M15; the grid electrode of the NMOS tube M19 is used as a second voltage bias signal input end of the differential amplifier body circuit, and the source electrode of the NMOS tube M19 is respectively connected with the source electrode of the NMOS tube M20 and the communication end 1 of the first switch circuit; the second voltage bias signal input end of the differential amplifier body circuit is connected with the second voltage bias signal output end of the voltage bias circuit; the grid electrode of the NMOS tube M20 is used as a tail current control end of the differential amplifier body circuit; the grid electrode of the PMOS tube M16 is used as a first voltage bias signal input end of the differential amplifier body circuit, and the source electrode of the PMOS tube M16 is respectively connected with the drain electrode of the PMOS tube M17 and the drain electrode of the PMOS tube M18; the first voltage bias signal input end of the differential amplifier body circuit is connected with the first voltage bias signal output end of the voltage bias circuit; the drain electrode of the PMOS tube M14 is respectively connected with the grid electrode of the PMOS tube M18, the drain electrode of the NMOS tube M15, the grid electrode of the PMOS tube M22 and the grid electrode of the NMOS tube M21, and the grid electrode of the PMOS tube M14 is connected with the grid electrode of the NMOS tube M15 and is used as a differential signal inverting input end Vin-of the fully differential amplifier; the drain electrode of the NMOS tube M21 is respectively connected with one end of the resistor R2 and the grid electrode of the NMOS tube M24, and the source electrode of the NMOS tube M24 is connected with the source electrode of the NMOS tube M24 and grounded; the drain electrode of the PMOS tube M22 is respectively connected with the other end of the resistor R2 and the grid electrode of the PMOS tube M23; the drain electrode of the NMOS tube M24 is connected with the drain electrode of the PMOS tube M23 and is used as a differential signal in-phase output end Vout+ of the fully differential amplifier; the communication end 2 of the first switch circuit is grounded, the control end 3 of the first switch circuit is used as an enabling clock signal input end of the fully differential amplifier, and the common end of the first switch circuit is grounded.
As shown in fig. 3, the switched capacitor common mode feedback circuit includes: the second switch circuit, the third switch circuit, the fourth switch circuit, the fifth switch circuit, the sixth switch circuit, the capacitor C1, the capacitor C2, the PMOS tube M25 and the NMOS tube M26;
The control end 3 of the second switch circuit is connected with the control end 3 of the fourth switch circuit, is used as the control end b of the switch capacitor common mode feedback circuit, is also used as an amplified phase clock signal input end of the fully differential amplifier, the communication end 1 of the switch capacitor common mode feedback circuit is respectively connected with the communication end 1 of the third switch circuit and one end of the capacitor C1, and the communication end 2 of the switch capacitor common mode feedback circuit is used as the communication end d of the switch capacitor common mode feedback circuit and is connected with the differential signal inverting output end Vout-of the fully differential amplifier; the control end 3 of the third switching circuit is connected with the grid electrode of the PMOS tube M25, the grid electrode of the NMOS tube M26 and the control end 3 of the fifth switching circuit, and is used as the control end a of the switched capacitor common mode feedback circuit, and is also used as the sampling phase clock signal input end of the fully differential amplifier, the communication end 2 of the third switching circuit is connected with the communication end 1 of the fifth switching circuit, and is used as the communication end g of the switched capacitor common mode feedback circuit to be connected with the common mode voltage reference input end Vcm; the communication end 2 of the fourth switching circuit is respectively connected with one end of the capacitor C2 and the communication end 2 of the fifth switching circuit, and the communication end 1 is used as the communication end C of the switched capacitor common mode feedback circuit and is connected with the differential signal in-phase output end Vout+ of the fully differential amplifier; the communication end 1 of the sixth switching circuit is respectively connected with the other end of the capacitor C1 and the other end of the capacitor C2, and is used as a communication end e of the switched capacitor common mode feedback circuit to be connected with a tail current control end of the differential amplifier body circuit, the control end 3 of the sixth switching circuit is respectively connected with the drain electrode of the PMOS tube M25 and the drain electrode of the NMOS tube M26, and the communication end 2 is used as a communication end f of the switched capacitor common mode feedback circuit to be connected with a second voltage bias signal output end of the voltage bias circuit; the power supply end of the second switch circuit is respectively connected with the power supply end of the third switch circuit, the power supply end of the fourth switch circuit, the power supply end of the fifth switch circuit, the power supply end of the sixth switch circuit and the source electrode of the PMOS tube M25, and is used as the power supply end of the switched capacitor common mode feedback circuit to be connected with the direct current power supply VDD.
As shown in fig. 4, the first switch circuit, the second switch circuit, the third switch circuit, the fourth switch circuit, the fifth switch circuit, and the sixth switch circuit have the same structure, and each includes: PMOS tube Q1, NMOS tube Q2, PMOS tube Q3 and NMOS tube Q4;
The grid electrode of the PMOS tube Q1 is respectively connected with the grid electrode of the NMOS tube Q2 and the grid electrode of the NMOS tube Q4, and is used as a control end 3 of the first switch circuit, the second switch circuit, the third switch circuit, the fourth switch circuit, the fifth switch circuit and the sixth switch circuit, the source electrode of the PMOS tube Q1 is used as a power supply end of the first switch circuit, the second switch circuit, the third switch circuit, the fourth switch circuit, the fifth switch circuit and the sixth switch circuit, and the drain electrode of the PMOS tube Q3 is respectively connected with the drain electrode of the NMOS tube Q2 and the grid electrode of the PMOS tube Q3; the drain electrode of the PMOS tube Q3 is connected with the source electrode of the NMOS tube Q4, and is used as a communication end 1 of the first switch circuit, the second switch circuit, the third switch circuit, the fourth switch circuit, the fifth switch circuit and the sixth switch circuit, and the source electrode of the PMOS tube Q3 is connected with the drain electrode of the NMOS tube Q4 and is used as a communication end 2 of the first switch circuit, the second switch circuit, the third switch circuit, the fourth switch circuit, the fifth switch circuit and the sixth switch circuit.
For various MOS tubes, the PMOS tube can be conducted when the difference value obtained by subtracting the grid voltage from the grid voltage is larger than the threshold voltage, namely a passage is formed between the source electrode and the drain electrode, and the NMOS tube can be conducted when the difference value obtained by subtracting the grid voltage from the grid voltage is larger than the threshold voltage, however, the equivalent internal resistance between the source electrode and the drain electrode is larger and the conduction capacity is weaker when the difference value between the grid voltage and the source voltage is not larger than the threshold voltage of the PMOS tube or the NMOS tube, and the property limits the on-off capacity of the independent PMOS switch and the NMOS switch. In this embodiment, the source of the PMOS transistor Q3 is connected to the drain of the NMOS transistor Q4, and the drain of the PMOS transistor Q3 is connected to the source of the NMOS transistor Q4, so as to form a controlled switch formed by parallel connection of PMOS and NMOS, and the control signals are inverted by an inverter circuit formed by the PMOS transistor Q1 and the NMOS transistor Q2, and the NMOS transistor Q4 and the PMOS transistor Q3 are driven by the control signals before and after the inversion, respectively. In the design, Q4 and Q3 can be simultaneously turned on or turned off, so that an effective controlled switch is formed; and when the conduction capacity of Q4 is weak, the conduction capacity of Q3 is strong, and when the conduction capacity of Q3 is weak, the conduction capacity of Q4 is strong, and the parallel connection design of the complementation of the strong and weak ensures that the switching circuit always has ideal switching characteristics.
In general, the embodiment inputs signals in a differential mode through the circuit design of the fully differential structure, outputs the signals in a differential mode, and can cancel common mode noise mixed in the signals, and the signal to noise ratio is improved under the condition that gain does not need to be increased, so compared with an amplifier with a single-ended structure, the power consumption is reduced theoretically without designing a huge gain bandwidth product, meanwhile, a first switch circuit is additionally arranged, the fully differential amplifier is controlled by an enabling clock signal, and the energy consumption is further reduced when the fully differential amplifier is idle.
The voltage bias circuit is driven by a voltage-independent current source circuit, so that the robustness of the invention to the power supply voltage is improved. In the differential amplifier body circuit, MOS transistors M17, M18, M16, M12, M14, M13, M15, M19 and M20 form a first stage of the differential amplifier body circuit, wherein M16 is a PMOS type tail current source, and M19 and M20 are a group of parallel NMOS transistors to form a double-tube NMOS type tail current source; in the voltage bias circuit, NMOS transistors M3 and M4 and PMOS transistors M5, M6 and M7 form a cascade relationship which is completely consistent with NMOS transistors M19 and M13 and PMOS transistors M12, M16 and M17 in the first stage and NMOS transistors M20 and M15 and PMOS transistors M14, M16 and M18 in the first stage, on the basis, the grid voltages of NMOS transistors M1 and M4 and PMOS transistor M5 are controlled through common mode voltage reference input signals V cm, the grid voltage of drain voltage of M1 is fed back to the grid voltage of M2, the grid voltage of drain voltage value M6 of M4 and M5 is fed back, the grid voltage of PMOS tail current source M16 is controlled through the grid voltage of M6, the grid of NMOS tail current source M19 is controlled through the grid voltage of M2, so that when the grid static voltages of M12 and M13 are equal to the voltage value of reference common mode voltage input signals V cm, the grid voltages of M12, M16, M13 and M14 and M13 are saturated in the ideal regions; because the gates of M12 and M13 are the differential signal in-phase input ends vin+ and the gates of M14 and M15 are the differential signal reverse input ends Vin-, the design of the invention provides two paths of voltage bias controlled by a common mode voltage reference input signal V cm for the differential input ends of the fully differential amplifier, and under the cooperation of the CMOS complementary circuit formed by the PMOS tube M12 and the NMOS tube M13 and the CMOS complementary circuit formed by the PMOS tube M14 and the NMOS tube M15, the characteristics of large swing input and high gain amplification can be realized. In order to provide common-mode output feedback for the two output ends of the first stage, in the voltage bias circuit, the grid electrode of the MOS tube M7 which is in a similar cascade relation with the MOS tubes M17 and M18 is also connected with the common-mode voltage reference input signal V cm, in this case, because the grid electrodes of the M16 and M19 are respectively controlled by the first voltage bias signal and the second voltage bias signal, the theoretical grid voltages of the M17 and M18 are also the voltage value of V cm, the grid electrode of the M17 is connected with the drain electrode of the M12, namely the inverting output end of the first stage, and the static voltage of the output end of the first stage is also the voltage value of V cm by connecting the grid electrode of the M18 with the drain electrode of the M14, namely the inverting output end of the first stage, so that the common-mode output feedback of the first stage is realized. In the switched capacitor common mode feedback circuit, when the sampling phase clock signal is invalid, namely the pipeline ADC is in a non-sampling state, the grid electrode of an NMOS tube M20 connected in parallel with an NMOS tail current source NMOS tube M19 is communicated with the grid electrode of the M19, and is commonly connected with a second voltage bias signal, so that the second voltage bias signal and the M19 enter the same working state, and the tail current of the first stage of the differential amplifier body circuit is cooperatively regulated.
MOS tubes M11, M10 and resistor R1, MOS tubes M22, M21 and resistor R2 respectively form an inverting part and an in-phase part of the second stage of the differential amplifier body circuit; MOS tubes M8 and M9, and MOS tubes M23 and M24 respectively form an inverting part and an in-phase part of the third stage of the differential amplifier body circuit. The second stage and the third stage of the differential amplifier body circuit are both in a hardware structure similar to an inverter and have large output swing, and the resistors R1 and R2 in the second stage are used for dynamically applying bias voltage to the third stage, so that the gain of the second stage is prevented from being reduced.
The switched capacitor common mode feedback circuit has the function of regulating and controlling the tail current of the first stage, and also has the function of capacitive coupling common mode feedback of the final output signals of the fully differential amplifier, namely the differential signal in-phase output end Vout+ and the differential signal out-of-phase output end Vout-). When the sampling phase clock signal is valid, namely the pipeline ADC works in a sampling state, one end of the capacitor C1 is connected with the common mode voltage reference input signal V cm, the other end of the capacitor C2 is connected with the grid electrode of the MOS tube M19, one end of the capacitor C2 is also connected with the common mode voltage reference input signal V cm, and the other end of the capacitor C2 is also connected with the grid electrode of the MOS tube M19; when the amplified phase clock signal is effective, that is, when the pipeline ADC works in an amplified state, one end of the capacitor C1 is connected with the differential signal inverting output end Vout-and the other end of the capacitor C1 is connected with the grid electrode of the MOS tube M19, and one end of the capacitor C2 is connected with the differential signal in-phase output end Vout+ and the other end of the capacitor C2 is connected with the grid electrode of the MOS tube M19. It is noted that in the field, two important clock signals of the pipeline ADC are two-phase non-overlapping clock signals, and an effective period of an amplified phase clock signal is always included in an ineffective period of a sampled phase clock signal, that is, the pipeline ADC only performs hold amplification during a non-sampling period, and the hold amplification time of the pipeline ADC is shorter than the duration of the non-sampling period.
In summary, the invention improves the signal to noise ratio and reduces the requirement of gain bandwidth product through the fully differential structural design of the differential amplifier body circuit, thereby reducing the power consumption and saving energy; providing common mode feedback for the differential amplifier body circuit through the switch capacitor common mode feedback circuit, so that the differential amplifier body circuit has high gain; providing a stable voltage bias for the differential amplifier body circuit through the voltage bias circuit; compared with the prior art, the device has the advantages of large input swing range, large output swing range and high linearity.
Claims (3)
1. A fully differential amplifier for a pipelined ADC, comprising: the differential amplifier comprises a voltage bias circuit, a differential amplifier body circuit and a switched capacitor common mode feedback circuit;
the voltage bias circuit is respectively connected with the differential amplifier body circuit and the switched capacitor common mode feedback circuit; the switch capacitor common mode feedback circuit is connected with the differential amplifier body circuit; the voltage bias circuit is used for providing bias voltage for the differential amplifier body circuit; the differential amplifier body circuit is used for amplifying an input signal in a differential form; the switch capacitor common mode feedback circuit is used for providing common mode feedback for the differential amplifier body circuit;
the voltage bias circuit includes: the CMOS current source circuit, the NMOS tube M1, the NMOS tube M2, the NMOS tube M3, the NMOS tube M4, the PMOS tube M5, the PMOS tube M6 and the PMOS tube M7;
The grid electrode of the NMOS tube M1 is respectively connected with the grid electrode of the NMOS tube M4, the grid electrode of the PMOS tube M5 and the grid electrode of the PMOS tube M7, and is used as a common-mode voltage reference input end Vcm of the fully differential amplifier; the current output end of the CMOS current source circuit is respectively connected with the drain electrode of the NMOS tube M1, the grid electrode of the NMOS tube M2 and the grid electrode of the NMOS tube M3 and is used as a second voltage bias signal output end of the voltage bias circuit; the drain electrode of the NMOS tube M2 is connected with the source electrode of the NMOS tube M1, and the source electrode of the NMOS tube M1 is grounded; the source electrode of the NMOS tube M3 is grounded, and the drain electrode of the NMOS tube M3 is connected with the source electrode of the NMOS tube M4; the drain electrode of the NMOS tube M4 is respectively connected with the drain electrode of the PMOS tube M5 and the grid electrode of the PMOS tube M6 and is used as a first voltage bias signal output end of the voltage bias circuit; the source electrode of the PMOS tube M5 is connected with the drain electrode of the PMOS tube M6; the source electrode of the PMOS tube M6 is connected with the drain electrode of the PMOS tube M7; the source electrode of the PMOS tube M7 and the power supply end of the CMOS current source circuit are connected with a direct current power supply VDD; the common ground of the CMOS current source circuit is grounded;
The CMOS current source circuit includes: PMOS tube M27, NMOS tube M28, PMOS tube M29, NMOS tube M30, grounding resistor R3 and PMOS tube M31;
The source electrode of the PMOS tube M27 is respectively connected with the source electrode of the PMOS tube M29 and the source electrode of the PMOS tube M31, and is used as a power supply end, the grid electrode of the PMOS tube M29, the drain electrode of the NMOS tube M30 and the grid electrode of the PMOS tube M31 are respectively connected, and the drain electrode of the PMOS tube M28, the grid electrode of the NMOS tube M28 and the grid electrode of the NMOS tube M30 are respectively connected; the source electrode of the NMOS tube M30 is connected with a grounding resistor R3; the source electrode of the NMOS tube M28 is grounded; the drain electrode of the PMOS tube M31 is used as a current output end of the CMOS current source circuit;
the differential amplifier body circuit includes: PMOS tube M8, NMOS tube M9, PMOS tube M11, resistor R1, NMOS tube M10, PMOS tube M12, NMOS tube M13, PMOS tube M14, NMOS tube M15, PMOS tube M16, PMOS tube M17, PMOS tube M18, NMOS tube M19, NMOS tube M20, NMOS tube M21, PMOS tube M22, resistor R2, PMOS tube M23, NMOS tube M24 and first switch circuit;
The drain electrode of the PMOS tube M8 is connected with the drain electrode of the NMOS tube M9 and is used as a differential signal inversion output end Vout-; the source electrode of the NMOS tube M9 is grounded, and the grid electrode of the NMOS tube M9 is respectively connected with one end of the resistor R1 and the drain electrode of the NMOS tube M10; the source electrode of the PMOS tube M8 is respectively connected with the source electrode of the PMOS tube M11, the source electrode of the PMOS tube M17, the source electrode of the PMOS tube M18, the source electrode of the PMOS tube M22, the source electrode of the PMOS tube M23 and the power supply end of the first switch circuit, and is used as the power supply end of the differential amplifier body circuit to be connected with the direct current power supply VDD, and the grid electrode of the differential amplifier body circuit is respectively connected with the other end of the resistor R1 and the drain electrode of the PMOS tube M11; the grid electrode of the NMOS tube M10 is respectively connected with the grid electrode of the PMOS tube M11, the drain electrode of the PMOS tube M12, the drain electrode of the NMOS tube M13 and the grid electrode of the PMOS tube M17, and the source electrode of the NMOS tube M is grounded; the grid electrode of the PMOS tube M12 is connected with the grid electrode of the NMOS tube M13 and is used as a differential signal non-inverting input end vin+ of the fully differential amplifier, and the source electrode of the PMOS tube M12 is respectively connected with the drain electrode of the PMOS tube M14 and the source electrode of the PMOS tube M16; the source electrode of the NMOS tube M13 is respectively connected with the drain electrode of the NMOS tube M19, the drain electrode of the NMOS tube M20 and the source electrode of the NMOS tube M15; the grid electrode of the NMOS tube M19 is used as a second voltage bias signal input end of the differential amplifier body circuit, and the source electrode of the NMOS tube M19 is respectively connected with the source electrode of the NMOS tube M20 and the communication end 1 of the first switch circuit; the second voltage bias signal input end of the differential amplifier body circuit is connected with the second voltage bias signal output end of the voltage bias circuit; the grid electrode of the NMOS tube M20 is used as a tail current control end of the differential amplifier body circuit; the grid electrode of the PMOS tube M16 is used as a first voltage bias signal input end of the differential amplifier body circuit, and the source electrode of the PMOS tube M16 is respectively connected with the drain electrode of the PMOS tube M17 and the drain electrode of the PMOS tube M18; the first voltage bias signal input end of the differential amplifier body circuit is connected with the first voltage bias signal output end of the voltage bias circuit; the drain electrode of the PMOS tube M14 is respectively connected with the grid electrode of the PMOS tube M18, the drain electrode of the NMOS tube M15, the grid electrode of the PMOS tube M22 and the grid electrode of the NMOS tube M21, and the grid electrode of the PMOS tube M14 is connected with the grid electrode of the NMOS tube M15 and is used as a differential signal inverting input end Vin-of the fully differential amplifier; the drain electrode of the NMOS tube M21 is respectively connected with one end of the resistor R2 and the grid electrode of the NMOS tube M24, and the source electrode of the NMOS tube M24 is connected with the source electrode of the NMOS tube M24 and grounded; the drain electrode of the PMOS tube M22 is respectively connected with the other end of the resistor R2 and the grid electrode of the PMOS tube M23; the drain electrode of the NMOS tube M24 is connected with the drain electrode of the PMOS tube M23 and is used as a differential signal in-phase output end Vout+ of the fully differential amplifier; the communication end 2 of the first switch circuit is grounded, the control end 3 of the first switch circuit is used as an enabling clock signal input end of the fully differential amplifier, and the common end of the first switch circuit is grounded;
The switched capacitor common mode feedback circuit comprises: the second switch circuit, the third switch circuit, the fourth switch circuit, the fifth switch circuit, the sixth switch circuit, the capacitor C1, the capacitor C2, the PMOS tube M25 and the NMOS tube M26;
The control end 3 of the second switch circuit is connected with the control end 3 of the fourth switch circuit, is used as the control end b of the switch capacitor common mode feedback circuit, is also used as an amplified phase clock signal input end of the fully differential amplifier, the communication end 1 of the switch capacitor common mode feedback circuit is respectively connected with the communication end 1 of the third switch circuit and one end of the capacitor C1, and the communication end 2 of the switch capacitor common mode feedback circuit is used as the communication end d of the switch capacitor common mode feedback circuit and is connected with the differential signal inverting output end Vout-of the fully differential amplifier; the control end 3 of the third switching circuit is connected with the grid electrode of the PMOS tube M25, the grid electrode of the NMOS tube M26 and the control end 3 of the fifth switching circuit, and is used as the control end a of the switched capacitor common mode feedback circuit, and is also used as the sampling phase clock signal input end of the fully differential amplifier, the communication end 2 of the third switching circuit is connected with the communication end 1 of the fifth switching circuit, and is used as the communication end g of the switched capacitor common mode feedback circuit to be connected with the common mode voltage reference input end Vcm; the communication end 2 of the fourth switching circuit is respectively connected with one end of the capacitor C2 and the communication end 2 of the fifth switching circuit, and the communication end 1 is used as the communication end C of the switched capacitor common mode feedback circuit and is connected with the differential signal in-phase output end Vout+ of the fully differential amplifier; the communication end 1 of the sixth switching circuit is respectively connected with the other end of the capacitor C1 and the other end of the capacitor C2, and is used as a communication end e of the switched capacitor common mode feedback circuit to be connected with a tail current control end of the differential amplifier body circuit, the control end 3 of the sixth switching circuit is respectively connected with the drain electrode of the PMOS tube M25 and the drain electrode of the NMOS tube M26, and the communication end 2 is used as a communication end f of the switched capacitor common mode feedback circuit to be connected with a second voltage bias signal output end of the voltage bias circuit; the power supply end of the second switch circuit is respectively connected with the power supply end of the third switch circuit, the power supply end of the fourth switch circuit, the power supply end of the fifth switch circuit, the power supply end of the sixth switch circuit and the source electrode of the PMOS tube M25, and is used as the power supply end of the switched capacitor common mode feedback circuit to be connected with the direct current power supply VDD.
2. The fully differential amplifier for a pipelined ADC of claim 1, wherein the first, second, third, fourth, fifth and sixth switching circuits are identical in structure, each comprising: PMOS tube Q1, NMOS tube Q2, PMOS tube Q3 and NMOS tube Q4;
The grid electrode of the PMOS tube Q1 is respectively connected with the grid electrode of the NMOS tube Q2 and the grid electrode of the NMOS tube Q4, and is used as a control end 3 of the first switch circuit, the second switch circuit, the third switch circuit, the fourth switch circuit, the fifth switch circuit and the sixth switch circuit, the source electrode of the PMOS tube Q1 is used as a power supply end of the first switch circuit, the second switch circuit, the third switch circuit, the fourth switch circuit, the fifth switch circuit and the sixth switch circuit, and the drain electrode of the PMOS tube Q3 is respectively connected with the drain electrode of the NMOS tube Q2 and the grid electrode of the PMOS tube Q3; the drain electrode of the PMOS tube Q3 is connected with the source electrode of the NMOS tube Q4, and is used as a communication end 1 of the first switch circuit, the second switch circuit, the third switch circuit, the fourth switch circuit, the fifth switch circuit and the sixth switch circuit, and the source electrode of the PMOS tube Q3 is connected with the drain electrode of the NMOS tube Q4 and is used as a communication end 2 of the first switch circuit, the second switch circuit, the third switch circuit, the fourth switch circuit, the fifth switch circuit and the sixth switch circuit.
3. The fully differential amplifier for a pipelined ADC of any one of claims 1-2, wherein the fully differential amplifier for a pipelined ADC is fabricated using a SMIC130nm integrated circuit process.
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