CN111431490A - Fully differential amplifier for pipeline ADC - Google Patents

Fully differential amplifier for pipeline ADC Download PDF

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Publication number
CN111431490A
CN111431490A CN202010382472.3A CN202010382472A CN111431490A CN 111431490 A CN111431490 A CN 111431490A CN 202010382472 A CN202010382472 A CN 202010382472A CN 111431490 A CN111431490 A CN 111431490A
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circuit
tube
switch circuit
pmos
electrode
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CN111431490B (en
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陈功
郭函
石跃
凌味未
黄姚
董倩宇
李蠡
魏华
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Chengdu University of Information Technology
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Chengdu University of Information Technology
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45479—Differential amplifiers with semiconductor devices only characterised by the way of common mode signal rejection

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Abstract

The invention discloses a fully differential amplifier for a pipeline ADC, comprising: the voltage bias circuit, the differential amplifier body circuit and the switch capacitor common mode feedback circuit; through the fully differential structural design of the differential amplifier body circuit, the signal-to-noise ratio is improved, and the requirement of gain bandwidth product is reduced, so that the power consumption is reduced, and the energy is saved; the common-mode feedback circuit of the switched capacitor provides common-mode feedback for the main body circuit of the differential amplifier, so that the main body circuit of the differential amplifier has high gain; providing stable voltage bias for the differential amplifier body circuit through the voltage bias circuit; compared with the traditional technology, the method also has the advantages of large input swing range, large output swing range and high linearity.

Description

Fully differential amplifier for pipeline ADC
Technical Field
The invention relates to the field of integrated circuits, in particular to a fully differential amplifier for a pipeline ADC.
Background
In the face of higher and higher speed and resolution requirements, a pipeline analog-to-digital converter (ADC) converts signals in a manner similar to a factory pipeline in bit (bits) in parallel, so that the conversion rate mainly depends on a single-stage speed, and the resolution mainly depends on the stage number, thereby greatly increasing the speed and the resolution and having great development prospect.
The pipeline ADC includes a plurality of stages (stages), the last stage is usually composed of a common flash ADC circuit, and the hardware structures of the first stages are the same, including: a sub-ADC and a gain digital-to-analog conversion unit (MDAC). The MDAC is comprised of a sub-DAC and a residue amplifier controlled by two non-overlapping sample and hold signals (including a sample phase clock signal and an amplified phase clock signal). The existing margin amplifier usually uses a closed-loop single-ended amplifier, and in order to meet the requirement of high speed and high precision of an ADC, a large gain-bandwidth product is needed, so that the power consumption is increased. In the process of improving the gain, a two-stage sleeve type design or folding type design structure based on a switched capacitor is usually adopted, and the structure is mainly characterized in that more transistors are stacked in the vertical direction, the requirement on power supply voltage is higher, and the problem of small oscillation range is solved; at present, there is also a method for improving gain by using positive feedback, for example, in the document CN109474249A of southeast university, a high-gain operational amplifier of negative resistance type positive feedback composed of NMOS transistors partially adopting a cross-coupled diode connection mode is proposed, however, in actual production, due to the existence of CMOS process deviation, it is difficult to obtain an accurate and unchangeable negative resistance in reality, so the positive feedback technology in a real environment can only be used as an idea to be developed, and has no robustness in engineering.
Disclosure of Invention
Aiming at the defects in the prior art, the fully differential amplifier for the pipeline ADC provided by the invention solves the problems of small swing range, poor robustness and high power consumption in the existing implementation scheme of the margin amplifier in the pipeline ADC.
In order to achieve the purpose of the invention, the invention adopts the technical scheme that: a fully-differential amplifier for a pipelined ADC, comprising: the voltage bias circuit, the differential amplifier body circuit and the switch capacitor common mode feedback circuit;
the voltage bias circuit is respectively connected with the differential amplifier body circuit and the switch capacitor common mode feedback circuit;
the switch capacitor common mode feedback circuit is connected with the differential amplifier body circuit;
the voltage bias circuit is used for providing bias voltage for the differential amplifier body circuit;
the differential amplifier body circuit is used for amplifying the differential input signal;
the switch capacitor common mode feedback circuit is used for providing common mode feedback for the differential amplifier body circuit.
Further, the voltage bias circuit includes: the CMOS current source circuit comprises a CMOS current source circuit, an NMOS tube M1, an NMOS tube M2, an NMOS tube M3, an NMOS tube M4, a PMOS tube M5, a PMOS tube M6 and a PMOS tube M7;
the grid electrode of the NMOS transistor M1 is respectively connected with the grid electrode of the NMOS transistor M4, the grid electrode of the PMOS transistor M5 and the grid electrode of the PMOS transistor M7 and is used as a common-mode voltage reference input end Vcm of the fully differential amplifier; the current output end of the CMOS current source circuit is respectively connected with the drain electrode of the NMOS tube M1, the grid electrode of the NMOS tube M2 and the grid electrode of the NMOS tube M3 and serves as a second voltage bias signal output end of the voltage bias circuit; the drain electrode of the NMOS tube M2 is connected with the source electrode of the NMOS tube M1, and the source electrode of the NMOS tube M2 is grounded; the source electrode of the NMOS tube M3 is grounded, and the drain electrode of the NMOS tube M3 is connected with the source electrode of the NMOS tube M4; the drain electrode of the NMOS transistor M4 is respectively connected with the drain electrode of the PMOS transistor M5 and the grid electrode of the PMOS transistor M6 and is used as a first voltage bias signal output end of the voltage bias circuit; the source electrode of the PMOS tube M5 is connected with the drain electrode of the PMOS tube M6; the source electrode of the PMOS tube M6 is connected with the drain electrode of the PMOS tube M7; the source electrode of the PMOS tube M7 and the power supply end of the CMOS current source circuit are connected with a direct-current power supply VDD; and the common end of the CMOS current source circuit is grounded.
Further, the CMOS current source circuit includes: a PMOS tube M27, an NMOS tube M28, a PMOS tube M29, an NMOS tube M30, a grounding resistor R3 and a PMOS tube M31;
the source electrode of the PMOS tube M27 is respectively connected with the drain electrode of the PMOS tube M29 and the drain electrode of the PMOS tube M31 and serves as a power supply end, the grid electrode of the PMOS tube M27 is respectively connected with the grid electrode of the PMOS tube M29, the drain electrode of the NMOS tube M30 and the grid electrode of the PMOS tube M31, and the drain electrode of the PMOS tube M27 is respectively connected with the drain electrode of the NMOS tube M28, the grid electrode of the NMOS tube M28 and the grid electrode of the NMOS tube M30; the source electrode of the NMOS tube M30 is connected with a grounding resistor R3; the source electrode of the NMOS tube M28 is grounded; the drain electrode of the PMOS pipe M31 is used as the current output end of the CMOS current source circuit.
The beneficial effects of the above further scheme are: through the connection relation of the specific PMOS tube and the specific NMOS tube, a current source irrelevant to power supply voltage is realized, the influence of the power supply voltage and power supply noise is avoided, and the robustness of the power supply is high.
Further, the differential type amplifier body circuit includes: a PMOS transistor M8, an NMOS transistor M9, a PMOS transistor M11, a resistor R1, an NMOS transistor M10, a PMOS transistor M12, an NMOS transistor M13, a PMOS transistor M14, an NMOS transistor M15, a PMOS transistor M16, a PMOS transistor M17, a PMOS transistor M18, an NMOS transistor M19, an NMOS transistor M20, an NMOS transistor M21, a PMOS transistor M22, a resistor R2, a PMOS transistor M23, an NMOS transistor M24 and a first switch circuit;
the drain electrode of the PMOS tube M8 is connected with the drain electrode of the NMOS tube M9 and is used as a differential signal inverting output end Vout-; the source electrode of the NMOS tube M9 is grounded, and the grid electrode of the NMOS tube M9 is respectively connected with one end of a resistor R1 and the drain electrode of the NMOS tube M10; the source electrode of the PMOS tube M8 is respectively connected with the source electrode of the PMOS tube M11, the source electrode of the PMOS tube M17, the source electrode of the PMOS tube M18, the source electrode of the PMOS tube M22, the source electrode of the PMOS tube M23 and the power supply end of the first switch circuit, the power supply end of the differential amplifier body circuit is connected with a direct-current power supply VDD, and the grid electrode of the differential amplifier body circuit is respectively connected with the other end of the resistor R1 and the drain electrode of the PMOS tube M11; the grid electrode of the NMOS tube M10 is respectively connected with the grid electrode of the PMOS tube M11, the drain electrode of the PMOS tube M12, the drain electrode of the NMOS tube M13 and the grid electrode of the PMOS tube M17, and the source electrode of the NMOS tube M10 is grounded; the grid electrode of the PMOS tube M12 is connected with the grid electrode of the NMOS tube M13 and is used as a differential signal non-inverting input end Vin + of the fully differential amplifier, and the source electrode of the PMOS tube M12 is respectively connected with the drain electrode of the PMOS tube M16 and the source electrode of the PMOS tube M14; the source electrode of the NMOS tube M13 is respectively connected with the drain electrode of the NMOS tube M19, the drain electrode of the NMOS tube M20 and the source electrode of the NMOS tube M15; the grid electrode of the NMOS tube M19 is used as a second voltage bias signal input end of the differential amplifier body circuit, and the source electrode of the NMOS tube M19 is respectively connected with the source electrode of the NMOS tube M20 and the communication end 1 of the first switch circuit; a second voltage bias signal input end of the differential amplifier body circuit is connected with a second voltage bias signal output end of the voltage bias circuit; the grid electrode of the NMOS tube M20 is used as a tail current control end of the differential amplifier body circuit; the grid electrode of the PMOS tube M16 is used as a first voltage bias signal input end of the differential amplifier body circuit, and the source electrode of the PMOS tube M16 is respectively connected with the drain electrode of the PMOS tube M17 and the drain electrode of the PMOS tube M18; a first voltage bias signal input end of the differential amplifier body circuit is connected with a first voltage bias signal output end of the voltage bias circuit; the drain electrode of the PMOS tube M14 is respectively connected with the grid electrode of the PMOS tube M18, the drain electrode of the NMOS tube M15, the grid electrode of the PMOS tube M22 and the grid electrode of the NMOS tube M21, and the grid electrode of the PMOS tube M22 is connected with the grid electrode of the NMOS tube M15 and is used as a differential signal inverting input end Vin-of the fully differential amplifier; the drain electrode of the NMOS tube M21 is respectively connected with one end of a resistor R2 and the grid electrode of the NMOS tube M24, and the source electrode of the NMOS tube M24 is connected with the source electrode of the NMOS tube M24 and grounded; the drain electrode of the PMOS tube M22 is respectively connected with the other end of the resistor R2 and the gate electrode of the PMOS tube M23; the drain electrode of the NMOS tube M24 is connected with the drain electrode of the PMOS tube M23 and is used as a differential signal in-phase output end Vout + of the fully differential amplifier; the communication end 2 of the first switch circuit is grounded, the control end 3 of the first switch circuit is used as an enabling clock signal input end of the fully differential amplifier, and the common end of the first switch circuit is grounded.
Further, the switched capacitor common mode feedback circuit comprises: the second switch circuit, the third switch circuit, the fourth switch circuit, the fifth switch circuit, the sixth switch circuit, the capacitor C1, the capacitor C2, the PMOS transistor M25 and the NMOS transistor M26;
the control end 3 of the second switch circuit is connected with the control end 3 of the fourth switch circuit, and is used as the control end b of the switch capacitor common mode feedback circuit and also used as the amplified phase clock signal input end of the fully differential amplifier, the communication end 1 of the second switch circuit is respectively connected with the communication end 1 of the third switch circuit and one end of a capacitor C1, and the communication end 2 of the second switch circuit is used as the communication end d of the switch capacitor common mode feedback circuit and is connected with the differential signal inverted output end Vout-of the fully differential amplifier; the control end 3 of the third switch circuit is connected with the grid of the PMOS transistor M25, the grid of the NMOS transistor M26 and the control end 3 of the fifth switch circuit, and is used as the control end a of the switch capacitor common mode feedback circuit and also used as the sampling phase clock signal input end of the fully differential amplifier, the connecting end 2 of the third switch circuit is connected with the connecting end 1 of the fifth switch circuit and is used as the connecting end g of the switch capacitor common mode feedback circuit and connected with the common mode voltage reference input end Vcm; a communication end 2 of the fourth switch circuit is respectively connected with one end of a capacitor C2 and a communication end 2 of the fifth switch circuit, and a communication end 1 of the fourth switch circuit is used as a communication end C of the switch capacitor common mode feedback circuit and is connected with a differential signal in-phase output end Vout + of the fully differential amplifier; a connection end 1 of the sixth switching circuit is respectively connected with the other end of the capacitor C1 and the other end of the capacitor C2, and is used as a connection end e of the switched capacitor common mode feedback circuit to be connected with a tail current control end of the differential amplifier body circuit, a control end 3 of the sixth switching circuit is respectively connected with a drain electrode of the PMOS tube M25 and a drain electrode of the NMOS tube M26, and a connection end 2 of the sixth switching circuit is used as a connection end f of the switched capacitor common mode feedback circuit to be connected with a second voltage bias signal output end of the voltage bias circuit; and the power supply end of the second switch circuit is respectively connected with the power supply end of the third switch circuit, the power supply end of the fourth switch circuit, the power supply end of the fifth switch circuit, the power supply end of the sixth switch circuit and the source electrode of the PMOS tube M25, and is connected with a direct-current power supply VDD as the power supply end of the switch capacitor common mode feedback circuit.
Further, the first switch circuit, the second switch circuit, the third switch circuit, the fourth switch circuit, the fifth switch circuit and the sixth switch circuit have the same structure, and each of the first switch circuit, the second switch circuit, the third switch circuit, the fourth switch circuit, the fifth switch circuit and the sixth switch circuit includes: PMOS transistor Q1, NMOS transistor Q2, PMOS transistor Q3 and NMOS transistor Q4;
the grid electrode of the PMOS tube Q1 is respectively connected with the grid electrode of the NMOS tube Q2 and the grid electrode of the NMOS tube Q4 and is used as the control end 3 of the first switch circuit, the second switch circuit, the third switch circuit, the fourth switch circuit, the fifth switch circuit and the sixth switch circuit, the source electrode of the PMOS tube Q1 is used as the power supply end of the first switch circuit, the second switch circuit, the third switch circuit, the fourth switch circuit, the fifth switch circuit and the sixth switch circuit, and the drain electrode of the PMOS tube Q2 is respectively connected with the drain electrode of the NMOS tube Q2 and the grid electrode of the PMOS tube Q3; the drain of the PMOS tube Q3 is connected with the source of the NMOS tube Q4 and is used as the communication end 1 of the first switch circuit, the second switch circuit, the third switch circuit, the fourth switch circuit, the fifth switch circuit and the sixth switch circuit, and the source thereof is connected with the drain of the NMOS tube Q4 and is used as the communication end 2 of the first switch circuit, the second switch circuit, the third switch circuit, the fourth switch circuit, the fifth switch circuit and the sixth switch circuit.
The beneficial effects of the above further scheme are: the first to sixth switching circuits can be effectively conducted when the switching circuits need to be conducted through the complementary design of the PMOS tube and the NMOS tube, and have ideal switching characteristics all the time.
Further, the fully differential amplifier for pipelined ADC is fabricated using the SMIC130nm integrated circuit process.
The invention has the beneficial effects that: through the fully differential structural design of the differential amplifier body circuit, the signal-to-noise ratio is improved, and the requirement of gain bandwidth product is reduced, so that the power consumption is reduced, and the energy is saved; the common-mode feedback circuit of the switched capacitor provides common-mode feedback for the main body circuit of the differential amplifier, so that the main body circuit of the differential amplifier has high gain; providing stable voltage bias for the differential amplifier body circuit through the voltage bias circuit; compared with the traditional technology, the method also has the advantages of large input swing range, large output swing range and high linearity.
Drawings
FIG. 1 is a circuit diagram of a fully differential amplifier for a pipelined ADC;
FIG. 2 is a CMOS current source circuit diagram;
FIG. 3 is a circuit diagram of a common mode feedback circuit of the switched capacitor;
fig. 4 is a switch circuit diagram.
Detailed Description
The following description of the embodiments of the present invention is provided to facilitate the understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and it will be apparent to those skilled in the art that various changes may be made without departing from the spirit and scope of the invention as defined and defined in the appended claims, and all matters produced by the invention using the inventive concept are protected.
In one embodiment of the invention, as shown in fig. 1, a fully differential amplifier for a pipelined ADC comprises: the voltage bias circuit, the differential amplifier body circuit and the switch capacitor common mode feedback circuit;
the voltage bias circuit is respectively connected with the differential amplifier body circuit and the switch capacitor common mode feedback circuit;
the switch capacitor common mode feedback circuit is connected with the differential amplifier body circuit;
the voltage bias circuit is used for providing bias voltage for the differential amplifier body circuit;
the differential amplifier body circuit is used for amplifying the differential input signal;
the switch capacitor common mode feedback circuit is used for providing common mode feedback for the differential amplifier body circuit.
The fully differential amplifier is fabricated by using an integrated circuit process of the SMIC130nm, and in the field, a current signal flowing between a drain and a source of a MOS transistor is often referred to as a drain-source current, and a voltage signal applied to a gate of the MOS transistor is often referred to as a gate voltage.
As shown in fig. 1, the voltage bias circuit includes: the CMOS current source circuit comprises a CMOS current source circuit, an NMOS tube M1, an NMOS tube M2, an NMOS tube M3, an NMOS tube M4, a PMOS tube M5, a PMOS tube M6 and a PMOS tube M7;
the grid electrode of the NMOS transistor M1 is respectively connected with the grid electrode of the NMOS transistor M4, the grid electrode of the PMOS transistor M5 and the grid electrode of the PMOS transistor M7 and is used as a common-mode voltage reference input end Vcm of the fully differential amplifier; the current output end of the CMOS current source circuit is respectively connected with the drain electrode of the NMOS tube M1, the grid electrode of the NMOS tube M2 and the grid electrode of the NMOS tube M3 and serves as a second voltage bias signal output end of the voltage bias circuit; the drain electrode of the NMOS tube M2 is connected with the source electrode of the NMOS tube M1, and the source electrode of the NMOS tube M2 is grounded; the source electrode of the NMOS tube M3 is grounded, and the drain electrode of the NMOS tube M3 is connected with the source electrode of the NMOS tube M4; the drain electrode of the NMOS transistor M4 is respectively connected with the drain electrode of the PMOS transistor M5 and the grid electrode of the PMOS transistor M6 and is used as a first voltage bias signal output end of the voltage bias circuit; the source electrode of the PMOS tube M5 is connected with the drain electrode of the PMOS tube M6; the source electrode of the PMOS tube M6 is connected with the drain electrode of the PMOS tube M7; the source electrode of the PMOS tube M7 and the power supply end of the CMOS current source circuit are connected with a direct-current power supply VDD; and the common end of the CMOS current source circuit is grounded.
As shown in fig. 2, the CMOS current source circuit includes: a PMOS tube M27, an NMOS tube M28, a PMOS tube M29, an NMOS tube M30, a grounding resistor R3 and a PMOS tube M31;
the source electrode of the PMOS tube M27 is respectively connected with the drain electrode of the PMOS tube M29 and the drain electrode of the PMOS tube M31 and serves as a power supply end, the grid electrode of the PMOS tube M27 is respectively connected with the grid electrode of the PMOS tube M29, the drain electrode of the NMOS tube M30 and the grid electrode of the PMOS tube M31, and the drain electrode of the PMOS tube M27 is respectively connected with the drain electrode of the NMOS tube M28, the grid electrode of the NMOS tube M28 and the grid electrode of the NMOS tube M30; the source electrode of the NMOS tube M30 is connected with a grounding resistor R3; the source electrode of the NMOS tube M28 is grounded; the drain electrode of the PMOS pipe M31 is used as the current output end of the CMOS current source circuit.
In the field of integrated circuits, a grid electrode and a drain electrode of an MOS tube are connected, and the MOS tube is in a diode connection method, at the moment, because the potential of the drain electrode and the potential of the grid electrode of the MOS tube are the same, the MOS tube is always locked in a saturation region and is in a saturation conduction state, and because the characteristic relation between the grid voltage and the drain-source current of the saturation region of the MOS tube is only related to the process characteristic of the MOS tube, the grid voltage can be controlled by regulating the size of the drain-source current. In the invention, a PMOS tube M27 drives a diode-connected NMOS tube M28, at the moment, the drain-source current of M28 is controlled by the drain-source current of M27, and the drain-source current of M27 is controlled by the gate voltage of M27, so that the gate voltage of M28 can be controlled by the gate voltage of M27; because the NMOS transistor M30 and the diode-connected PMOS transistor M29 are the same mechanism, the grid electrode of M27 is communicated with the grid electrode of M29, and the grid electrode of M28 is communicated with the grid electrode of M30, a system which controls the grid voltage of the grid electrode by the drain-source current and controls the drain-source current and is irrelevant to the power supply voltage is formed; at this time, the present invention makes a voltage difference exist between the source voltage of M30 and the source voltage of M28 through the resistor R3, so as to specifically control the value of the current, and under the connection relationship of the present circuit, if the width-to-length ratios of the gate oxides in the process parameters of M27, M29 and M31 are set to be the same, and the width-to-length ratios of the gate oxides of M28 and M30 are set to be the same, and the value is k, in the present embodiment, the output current of the present circuit is as shown in the following formula no matter what the voltage value of the dc power supply VDD is:
Figure BDA0002482684400000091
wherein I is the output current value of the CMOS current source, unFor electron mobility, CoxThe gate oxide permittivity R is the resistance value of the resistor R3 in the physical process of the NMOS transistor, namely the integrated circuit process of the SMIC130 nm. Therefore, the invention realizes a current source irrelevant to the power supply voltage through the connection relation of the specific PMOS tube and the specific NMOS tube, is not influenced by the power supply voltage and the power supply noise, and has high robustness to the power supply.
As shown in fig. 1, the differential amplifier main body circuit includes: a PMOS transistor M8, an NMOS transistor M9, a PMOS transistor M11, a resistor R1, an NMOS transistor M10, a PMOS transistor M12, an NMOS transistor M13, a PMOS transistor M14, an NMOS transistor M15, a PMOS transistor M16, a PMOS transistor M17, a PMOS transistor M18, an NMOS transistor M19, an NMOS transistor M20, an NMOS transistor M21, a PMOS transistor M22, a resistor R2, a PMOS transistor M23, an NMOS transistor M24 and a first switch circuit;
the drain electrode of the PMOS tube M8 is connected with the drain electrode of the NMOS tube M9 and is used as a differential signal inverting output end Vout-; the source electrode of the NMOS tube M9 is grounded, and the grid electrode of the NMOS tube M9 is respectively connected with one end of a resistor R1 and the drain electrode of the NMOS tube M10; the source electrode of the PMOS tube M8 is respectively connected with the source electrode of the PMOS tube M11, the source electrode of the PMOS tube M17, the source electrode of the PMOS tube M18, the source electrode of the PMOS tube M22, the source electrode of the PMOS tube M23 and the power supply end of the first switch circuit, the power supply end of the differential amplifier body circuit is connected with a direct-current power supply VDD, and the grid electrode of the differential amplifier body circuit is respectively connected with the other end of the resistor R1 and the drain electrode of the PMOS tube M11; the grid electrode of the NMOS tube M10 is respectively connected with the grid electrode of the PMOS tube M11, the drain electrode of the PMOS tube M12, the drain electrode of the NMOS tube M13 and the grid electrode of the PMOS tube M17, and the source electrode of the NMOS tube M10 is grounded; the grid electrode of the PMOS tube M12 is connected with the grid electrode of the NMOS tube M13 and is used as a differential signal non-inverting input end Vin + of the fully differential amplifier, and the source electrode of the PMOS tube M12 is respectively connected with the drain electrode of the PMOS tube M16 and the source electrode of the PMOS tube M14; the source electrode of the NMOS tube M13 is respectively connected with the drain electrode of the NMOS tube M19, the drain electrode of the NMOS tube M20 and the source electrode of the NMOS tube M15; the grid electrode of the NMOS tube M19 is used as a second voltage bias signal input end of the differential amplifier body circuit, and the source electrode of the NMOS tube M19 is respectively connected with the source electrode of the NMOS tube M20 and the communication end 1 of the first switch circuit; a second voltage bias signal input end of the differential amplifier body circuit is connected with a second voltage bias signal output end of the voltage bias circuit; the grid electrode of the NMOS tube M20 is used as a tail current control end of the differential amplifier body circuit; the grid electrode of the PMOS tube M16 is used as a first voltage bias signal input end of the differential amplifier body circuit, and the source electrode of the PMOS tube M16 is respectively connected with the drain electrode of the PMOS tube M17 and the drain electrode of the PMOS tube M18; a first voltage bias signal input end of the differential amplifier body circuit is connected with a first voltage bias signal output end of the voltage bias circuit; the drain electrode of the PMOS tube M14 is respectively connected with the grid electrode of the PMOS tube M18, the drain electrode of the NMOS tube M15, the grid electrode of the PMOS tube M22 and the grid electrode of the NMOS tube M21, and the grid electrode of the PMOS tube M22 is connected with the grid electrode of the NMOS tube M15 and is used as a differential signal inverting input end Vin-of the fully differential amplifier; the drain electrode of the NMOS tube M21 is respectively connected with one end of a resistor R2 and the grid electrode of the NMOS tube M24, and the source electrode of the NMOS tube M24 is connected with the source electrode of the NMOS tube M24 and grounded; the drain electrode of the PMOS tube M22 is respectively connected with the other end of the resistor R2 and the gate electrode of the PMOS tube M23; the drain electrode of the NMOS tube M24 is connected with the drain electrode of the PMOS tube M23 and is used as a differential signal in-phase output end Vout + of the fully differential amplifier; the communication end 2 of the first switch circuit is grounded, the control end 3 of the first switch circuit is used as an enabling clock signal input end of the fully differential amplifier, and the common end of the first switch circuit is grounded.
As shown in fig. 3, the switched capacitor common mode feedback circuit includes: the second switch circuit, the third switch circuit, the fourth switch circuit, the fifth switch circuit, the sixth switch circuit, the capacitor C1, the capacitor C2, the PMOS transistor M25 and the NMOS transistor M26;
the control end 3 of the second switch circuit is connected with the control end 3 of the fourth switch circuit, and is used as the control end b of the switch capacitor common mode feedback circuit and also used as the amplified phase clock signal input end of the fully differential amplifier, the communication end 1 of the second switch circuit is respectively connected with the communication end 1 of the third switch circuit and one end of a capacitor C1, and the communication end 2 of the second switch circuit is used as the communication end d of the switch capacitor common mode feedback circuit and is connected with the differential signal inverted output end Vout-of the fully differential amplifier; the control end 3 of the third switch circuit is connected with the grid of the PMOS transistor M25, the grid of the NMOS transistor M26 and the control end 3 of the fifth switch circuit, and is used as the control end a of the switch capacitor common mode feedback circuit and also used as the sampling phase clock signal input end of the fully differential amplifier, the connecting end 2 of the third switch circuit is connected with the connecting end 1 of the fifth switch circuit and is used as the connecting end g of the switch capacitor common mode feedback circuit and connected with the common mode voltage reference input end Vcm; a communication end 2 of the fourth switch circuit is respectively connected with one end of a capacitor C2 and a communication end 2 of the fifth switch circuit, and a communication end 1 of the fourth switch circuit is used as a communication end C of the switch capacitor common mode feedback circuit and is connected with a differential signal in-phase output end Vout + of the fully differential amplifier; a connection end 1 of the sixth switching circuit is respectively connected with the other end of the capacitor C1 and the other end of the capacitor C2, and is used as a connection end e of the switched capacitor common mode feedback circuit to be connected with a tail current control end of the differential amplifier body circuit, a control end 3 of the sixth switching circuit is respectively connected with a drain electrode of the PMOS tube M25 and a drain electrode of the NMOS tube M26, and a connection end 2 of the sixth switching circuit is used as a connection end f of the switched capacitor common mode feedback circuit to be connected with a second voltage bias signal output end of the voltage bias circuit; and the power supply end of the second switch circuit is respectively connected with the power supply end of the third switch circuit, the power supply end of the fourth switch circuit, the power supply end of the fifth switch circuit, the power supply end of the sixth switch circuit and the source electrode of the PMOS tube M25, and is connected with a direct-current power supply VDD as the power supply end of the switch capacitor common mode feedback circuit.
As shown in fig. 4, the first switch circuit, the second switch circuit, the third switch circuit, the fourth switch circuit, the fifth switch circuit, and the sixth switch circuit have the same structure, and each of the first switch circuit, the second switch circuit, the third switch circuit, the fourth switch circuit, the fifth switch circuit, and the sixth switch circuit includes: PMOS transistor Q1, NMOS transistor Q2, PMOS transistor Q3 and NMOS transistor Q4;
the grid electrode of the PMOS tube Q1 is respectively connected with the grid electrode of the NMOS tube Q2 and the grid electrode of the NMOS tube Q4 and is used as the control end 3 of the first switch circuit, the second switch circuit, the third switch circuit, the fourth switch circuit, the fifth switch circuit and the sixth switch circuit, the source electrode of the PMOS tube Q1 is used as the power supply end of the first switch circuit, the second switch circuit, the third switch circuit, the fourth switch circuit, the fifth switch circuit and the sixth switch circuit, and the drain electrode of the PMOS tube Q2 is respectively connected with the drain electrode of the NMOS tube Q2 and the grid electrode of the PMOS tube Q3; the drain of the PMOS tube Q3 is connected with the source of the NMOS tube Q4 and is used as the communication end 1 of the first switch circuit, the second switch circuit, the third switch circuit, the fourth switch circuit, the fifth switch circuit and the sixth switch circuit, and the source thereof is connected with the drain of the NMOS tube Q4 and is used as the communication end 2 of the first switch circuit, the second switch circuit, the third switch circuit, the fourth switch circuit, the fifth switch circuit and the sixth switch circuit.
For various MOS tubes, a PMOS tube can be conducted when the difference obtained by subtracting the gate voltage from the source voltage is larger than the threshold voltage, namely a channel is formed between a source electrode and a drain electrode, and an NMOS tube can be conducted when the difference obtained by subtracting the source voltage from the gate voltage is larger than the threshold voltage. In this embodiment, the source of the PMOS transistor Q3 is connected to the drain of the NMOS transistor Q4, and the drain of the PMOS transistor Q3 is connected to the source of the NMOS transistor Q4, so as to form a controlled switch with parallel PMOS and NMOS, and the control signal is inverted by the inverter circuit formed by the PMOS transistor Q1 and the NMOS transistor Q2, and the control signals before and after inversion respectively drive the NMOS transistor Q4 and the PMOS transistor Q3. With the design, the Q4 and the Q3 can be switched on or off simultaneously, so that an effective controlled switch is formed; and when the conduction capability of Q4 is weak, the conduction capability of Q3 is strong, and when the conduction capability of Q3 is weak, the conduction capability of Q4 is strong, and the parallel design with complementary strength makes the switch circuit always have ideal switch characteristics.
On the whole, the present embodiment inputs the signal in a differential form and outputs the signal in a differential form through the circuit design of the fully differential structure, so that the common mode noise mixed in the signal can be cancelled, and the signal-to-noise ratio is improved without increasing the gain, so that compared with the amplifier in a single-ended structure, the amplifier does not need to design a huge gain bandwidth product, and theoretically reduces the power consumption.
The voltage bias circuit is driven by the current source circuit irrelevant to voltage, so that the robustness of the invention to the power supply voltage is improved. In the differential amplifier body circuit, MOS transistors M17, M18, M16, M12, M14, M13, M15, M19 and M20 form a first stage of the differential amplifier body circuit, wherein M16 is a PMOS tail current source, and M19 and M20 are a group of NMOS transistors connected in parallel to form a double-transistor NMOS tail current source; in the voltage bias circuit, NMOS transistors M3 and M4 and PMOS transistors M5, M6 and M7 constitute a cascade relation completely consistent with NMOS transistors M19 and M13 and PMOS transistors M12, M16 and M17 in the first stage and with NMOS transistors M20 and M15 and PMOS transistors M14, M16 and M18 in the first stage, and on the basis, the input signal V is referenced by a common mode voltagecmThe grid voltages of NMOS transistors M1, M4 and a PMOS transistor M5 are controlled, the drain voltage of M1 is fed back to the grid voltage of M2, the drain voltage values of M4 and M5 are fed back to the grid voltage of M6, a first voltage bias signal is formed by the grid voltage of M6 to control the grid of a PMOS tail current source M16, a second voltage bias signal is formed by the grid voltage of M2 to control the grid of an NMOS tail current source M19, and therefore grid static voltages of M12 and M13 and static grid voltages of M14 and M15 are equal to a common mode voltage reference input signal VcmAt the voltage value of (3), the six MOS transistors of M16, M19, M12, M13, M14 and M15 work in an ideal saturation region; since the gates of M12 and M13 are the non-inverting inputs Vin + of the differential signal, and the gates of M14 and M15 are the inverting inputs Vin-, of the differential signal, the design of the present invention provides a common-mode voltage reference input signal V to the differential inputs of the fully differential amplifiercmThe two controlled paths of voltage are biased, and the CMOS complementary circuit formed by the PMOS transistor M12 and the NMOS transistor M13 and the CMOS complementary circuit formed by the PMOS transistor M14 and the NMOS transistor M15 cooperateMeanwhile, the characteristics of large-swing input and high-gain amplification can be realized. The drains of M12 and M13 are the inverting output of the first stage, the drains of M14 and M15 are the non-inverting output of the first stage, and in order to provide common mode output feedback to the two outputs of the first stage, in the voltage bias circuit, the gate of MOS transistor M7 at a position corresponding to the position of MOS transistors M17 and M18 in a similar cascade relationship is also connected to a common mode voltage reference input signal VcmIn this case, the gate voltages of M17 and M18 are also V, since the M16 and M19 gates are controlled by the first voltage bias signal and the second voltage bias signal, respectivelycmBy connecting the gate of M17 to the drain of M12, i.e., the inverting output terminal of the first stage, and by connecting the gate of M18 to the drain of M14, i.e., the non-inverting output terminal of the first stage, the quiescent voltage at the output terminal of the first stage is also VcmIn addition, when the fully differential amplifier has an input signal, the grid voltages of M17 and M18 can change according to the change of the current output voltage of the first stage, so that the drain-source current of the fully differential amplifier is regulated and controlled through the grid voltages, the two large current paths of the first stage are further compensated, dynamic adjustment is realized, the linearity of the first stage is improved, and the condition of gain decline when a large signal is input is avoided. In the switch capacitor common mode feedback circuit, when a sampling phase clock signal is invalid, namely when the pipeline ADC is in a non-sampling state, the grid electrode of the NMOS tube M20 connected with the NMOS tail current source NMOS tube M19 in parallel is communicated with the grid electrode of the M19, a second voltage bias signal is connected together, the grid electrode and the M19 enter the same working state, and the tail current of the first stage of the differential amplifier body circuit is adjusted in a coordinated mode.
MOS tubes M11 and M10 and a resistor R1, and MOS tubes M22 and M21 and a resistor R2 respectively form an anti-phase part and an in-phase part of the second stage of the differential amplifier body circuit; the MOS transistors M8 and M9, and the MOS transistors M23 and M24 constitute the inverting part and the non-inverting part, respectively, of the third stage of the differential amplifier body circuit. The second stage and the third stage of the differential amplifier body circuit adopt a hardware structure similar to an inverter and have large output swing, and the resistors R1 and R2 in the second stage play a role of dynamically applying bias voltage to the third stage, so that the gain of the second stage is prevented from being reduced.
Besides the function of regulating the first-stage tail current, the switched capacitor common mode feedback circuit also plays a role of capacitive coupling common mode feedback of the final output signal of the fully differential amplifier, namely the differential signal in-phase output end Vout + and the differential signal out-phase output end Vout-: when the sampling phase clock signal is effective, namely the pipeline ADC works in a sampling state, one end of the capacitor C1 is connected with a common-mode voltage reference input signal VcmThe other end is connected with the grid of the MOS tube M19, and one end of the capacitor C2 is also connected with a common mode voltage reference input signal VcmThe other end is also connected with the grid electrode of the MOS tube M19; when the amplified phase clock signal is effective, that is, the pipeline ADC operates in the amplification state, one end of the capacitor C1 is connected to the differential signal inverting output terminal Vout-, and the other end is connected to the gate of the MOS transistor M19, and one end of the capacitor C2 is connected to the differential signal non-inverting output terminal Vout +, and the other end is connected to the gate of the MOS transistor M19. It is worth noting that in the field, two important clock signals of the pipeline ADC are two-phase non-overlapping clock signals, the valid period of the amplified phase clock signal is always included in the invalid period of the sampled phase clock signal, that is, the pipeline ADC will keep amplifying only in the non-sampled period, and the time for the pipeline ADC to keep amplifying is shorter than the duration of the non-sampled period.
In conclusion, the invention improves the signal-to-noise ratio and reduces the requirement of gain bandwidth product by the fully differential structural design of the differential amplifier body circuit, thereby reducing the power consumption and saving energy; the common-mode feedback circuit of the switched capacitor provides common-mode feedback for the main body circuit of the differential amplifier, so that the main body circuit of the differential amplifier has high gain; providing stable voltage bias for the differential amplifier body circuit through the voltage bias circuit; compared with the traditional technology, the method also has the advantages of large input swing range, large output swing range and high linearity.

Claims (7)

1. A fully differential amplifier for a pipelined ADC, comprising: the voltage bias circuit, the differential amplifier body circuit and the switch capacitor common mode feedback circuit;
the voltage bias circuit is respectively connected with the differential amplifier body circuit and the switch capacitor common mode feedback circuit; the switch capacitor common mode feedback circuit is connected with the differential amplifier body circuit; the voltage bias circuit is used for providing bias voltage for the differential amplifier body circuit; the differential amplifier body circuit is used for amplifying the differential input signal; the switch capacitor common mode feedback circuit is used for providing common mode feedback for the differential amplifier body circuit.
2. The fully-differential amplifier for a pipelined ADC of claim 1, wherein the voltage bias circuit comprises: the CMOS current source circuit comprises a CMOS current source circuit, an NMOS tube M1, an NMOS tube M2, an NMOS tube M3, an NMOS tube M4, a PMOS tube M5, a PMOS tube M6 and a PMOS tube M7;
the grid electrode of the NMOS transistor M1 is respectively connected with the grid electrode of the NMOS transistor M4, the grid electrode of the PMOS transistor M5 and the grid electrode of the PMOS transistor M7 and is used as a common-mode voltage reference input end Vcm of the fully differential amplifier; the current output end of the CMOS current source circuit is respectively connected with the drain electrode of the NMOS tube M1, the grid electrode of the NMOS tube M2 and the grid electrode of the NMOS tube M3 and serves as a second voltage bias signal output end of the voltage bias circuit; the drain electrode of the NMOS tube M2 is connected with the source electrode of the NMOS tube M1, and the source electrode of the NMOS tube M2 is grounded; the source electrode of the NMOS tube M3 is grounded, and the drain electrode of the NMOS tube M3 is connected with the source electrode of the NMOS tube M4; the drain electrode of the NMOS transistor M4 is respectively connected with the drain electrode of the PMOS transistor M5 and the grid electrode of the PMOS transistor M6 and is used as a first voltage bias signal output end of the voltage bias circuit; the source electrode of the PMOS tube M5 is connected with the drain electrode of the PMOS tube M6; the source electrode of the PMOS tube M6 is connected with the drain electrode of the PMOS tube M7; the source electrode of the PMOS tube M7 and the power supply end of the CMOS current source circuit are connected with a direct-current power supply VDD; and the common end of the CMOS current source circuit is grounded.
3. The fully-differential amplifier for a pipelined ADC of claim 2, wherein the CMOS current source circuit comprises: a PMOS tube M27, an NMOS tube M28, a PMOS tube M29, an NMOS tube M30, a grounding resistor R3 and a PMOS tube M31;
the source electrode of the PMOS tube M27 is respectively connected with the drain electrode of the PMOS tube M29 and the drain electrode of the PMOS tube M31 and serves as a power supply end, the grid electrode of the PMOS tube M27 is respectively connected with the grid electrode of the PMOS tube M29, the drain electrode of the NMOS tube M30 and the grid electrode of the PMOS tube M31, and the drain electrode of the PMOS tube M27 is respectively connected with the drain electrode of the NMOS tube M28, the grid electrode of the NMOS tube M28 and the grid electrode of the NMOS tube M30; the source electrode of the NMOS tube M30 is connected with a grounding resistor R3; the source electrode of the NMOS tube M28 is grounded; the drain electrode of the PMOS pipe M31 is used as the current output end of the CMOS current source circuit.
4. The fully-differential amplifier for pipelined ADCs of claim 2, wherein the differential amplifier bulk circuit comprises: a PMOS transistor M8, an NMOS transistor M9, a PMOS transistor M11, a resistor R1, an NMOS transistor M10, a PMOS transistor M12, an NMOS transistor M13, a PMOS transistor M14, an NMOS transistor M15, a PMOS transistor M16, a PMOS transistor M17, a PMOS transistor M18, an NMOS transistor M19, an NMOS transistor M20, an NMOS transistor M21, a PMOS transistor M22, a resistor R2, a PMOS transistor M23, an NMOS transistor M24 and a first switch circuit;
the drain electrode of the PMOS tube M8 is connected with the drain electrode of the NMOS tube M9 and is used as a differential signal inverting output end Vout-; the source electrode of the NMOS tube M9 is grounded, and the grid electrode of the NMOS tube M9 is respectively connected with one end of a resistor R1 and the drain electrode of the NMOS tube M10; the source electrode of the PMOS tube M8 is respectively connected with the source electrode of the PMOS tube M11, the source electrode of the PMOS tube M17, the source electrode of the PMOS tube M18, the source electrode of the PMOS tube M22, the source electrode of the PMOS tube M23 and the power supply end of the first switch circuit, the power supply end of the differential amplifier body circuit is connected with a direct-current power supply VDD, and the grid electrode of the differential amplifier body circuit is respectively connected with the other end of the resistor R1 and the drain electrode of the PMOS tube M11; the grid electrode of the NMOS tube M10 is respectively connected with the grid electrode of the PMOS tube M11, the drain electrode of the PMOS tube M12, the drain electrode of the NMOS tube M13 and the grid electrode of the PMOS tube M17, and the source electrode of the NMOS tube M10 is grounded; the grid electrode of the PMOS tube M12 is connected with the grid electrode of the NMOS tube M13 and is used as a differential signal non-inverting input end Vin + of the fully differential amplifier, and the source electrode of the PMOS tube M12 is respectively connected with the drain electrode of the PMOS tube M16 and the source electrode of the PMOS tube M14; the source electrode of the NMOS tube M13 is respectively connected with the drain electrode of the NMOS tube M19, the drain electrode of the NMOS tube M20 and the source electrode of the NMOS tube M15; the grid electrode of the NMOS tube M19 is used as a second voltage bias signal input end of the differential amplifier body circuit, and the source electrode of the NMOS tube M19 is respectively connected with the source electrode of the NMOS tube M20 and the communication end 1 of the first switch circuit; a second voltage bias signal input end of the differential amplifier body circuit is connected with a second voltage bias signal output end of the voltage bias circuit; the grid electrode of the NMOS tube M20 is used as a tail current control end of the differential amplifier body circuit; the grid electrode of the PMOS tube M16 is used as a first voltage bias signal input end of the differential amplifier body circuit, and the source electrode of the PMOS tube M16 is respectively connected with the drain electrode of the PMOS tube M17 and the drain electrode of the PMOS tube M18; a first voltage bias signal input end of the differential amplifier body circuit is connected with a first voltage bias signal output end of the voltage bias circuit; the drain electrode of the PMOS tube M14 is respectively connected with the grid electrode of the PMOS tube M18, the drain electrode of the NMOS tube M15, the grid electrode of the PMOS tube M22 and the grid electrode of the NMOS tube M21, and the grid electrode of the PMOS tube M22 is connected with the grid electrode of the NMOS tube M15 and is used as a differential signal inverting input end Vin-of the fully differential amplifier; the drain electrode of the NMOS tube M21 is respectively connected with one end of a resistor R2 and the grid electrode of the NMOS tube M24, and the source electrode of the NMOS tube M24 is connected with the source electrode of the NMOS tube M24 and grounded; the drain electrode of the PMOS tube M22 is respectively connected with the other end of the resistor R2 and the gate electrode of the PMOS tube M23; the drain electrode of the NMOS tube M24 is connected with the drain electrode of the PMOS tube M23 and is used as a differential signal in-phase output end Vout + of the fully differential amplifier; the communication end 2 of the first switch circuit is grounded, the control end 3 of the first switch circuit is used as an enabling clock signal input end of the fully differential amplifier, and the common end of the first switch circuit is grounded.
5. The fully-differential amplifier for a pipelined ADC of claim 4, wherein the switched-capacitor common-mode feedback circuit comprises: the second switch circuit, the third switch circuit, the fourth switch circuit, the fifth switch circuit, the sixth switch circuit, the capacitor C1, the capacitor C2, the PMOS transistor M25 and the NMOS transistor M26;
the control end 3 of the second switch circuit is connected with the control end 3 of the fourth switch circuit, and is used as the control end b of the switch capacitor common mode feedback circuit and also used as the amplified phase clock signal input end of the fully differential amplifier, the communication end 1 of the second switch circuit is respectively connected with the communication end 1 of the third switch circuit and one end of a capacitor C1, and the communication end 2 of the second switch circuit is used as the communication end d of the switch capacitor common mode feedback circuit and is connected with the differential signal inverted output end Vout-of the fully differential amplifier; the control end 3 of the third switch circuit is connected with the grid of the PMOS transistor M25, the grid of the NMOS transistor M26 and the control end 3 of the fifth switch circuit, and is used as the control end a of the switch capacitor common mode feedback circuit and also used as the sampling phase clock signal input end of the fully differential amplifier, the connecting end 2 of the third switch circuit is connected with the connecting end 1 of the fifth switch circuit and is used as the connecting end g of the switch capacitor common mode feedback circuit and connected with the common mode voltage reference input end Vcm; a communication end 2 of the fourth switch circuit is respectively connected with one end of a capacitor C2 and a communication end 2 of the fifth switch circuit, and a communication end 1 of the fourth switch circuit is used as a communication end C of the switch capacitor common mode feedback circuit and is connected with a differential signal in-phase output end Vout + of the fully differential amplifier; a connection end 1 of the sixth switching circuit is respectively connected with the other end of the capacitor C1 and the other end of the capacitor C2, and is used as a connection end e of the switched capacitor common mode feedback circuit to be connected with a tail current control end of the differential amplifier body circuit, a control end 3 of the sixth switching circuit is respectively connected with a drain electrode of the PMOS tube M25 and a drain electrode of the NMOS tube M26, and a connection end 2 of the sixth switching circuit is used as a connection end f of the switched capacitor common mode feedback circuit to be connected with a second voltage bias signal output end of the voltage bias circuit; and the power supply end of the second switch circuit is respectively connected with the power supply end of the third switch circuit, the power supply end of the fourth switch circuit, the power supply end of the fifth switch circuit, the power supply end of the sixth switch circuit and the source electrode of the PMOS tube M25, and is connected with a direct-current power supply VDD as the power supply end of the switch capacitor common mode feedback circuit.
6. The fully-differential amplifier for pipelined ADCs of claim 5, wherein the first, second, third, fourth, fifth and sixth switching circuits are identical in structure and each comprise: PMOS transistor Q1, NMOS transistor Q2, PMOS transistor Q3 and NMOS transistor Q4;
the grid electrode of the PMOS tube Q1 is respectively connected with the grid electrode of the NMOS tube Q2 and the grid electrode of the NMOS tube Q4 and is used as the control end 3 of the first switch circuit, the second switch circuit, the third switch circuit, the fourth switch circuit, the fifth switch circuit and the sixth switch circuit, the source electrode of the PMOS tube Q1 is used as the power supply end of the first switch circuit, the second switch circuit, the third switch circuit, the fourth switch circuit, the fifth switch circuit and the sixth switch circuit, and the drain electrode of the PMOS tube Q2 is respectively connected with the drain electrode of the NMOS tube Q2 and the grid electrode of the PMOS tube Q3; the drain of the PMOS tube Q3 is connected with the source of the NMOS tube Q4 and is used as the communication end 1 of the first switch circuit, the second switch circuit, the third switch circuit, the fourth switch circuit, the fifth switch circuit and the sixth switch circuit, and the source thereof is connected with the drain of the NMOS tube Q4 and is used as the communication end 2 of the first switch circuit, the second switch circuit, the third switch circuit, the fourth switch circuit, the fifth switch circuit and the sixth switch circuit.
7. The fully-differential amplifier for pipelined ADCs of any of claims 1-6, wherein the fully-differential amplifier for pipelined ADCs is fabricated using SMIC130nm integrated circuit technology.
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