CN115378433B - 1.25GHz broadband self-bias low-power-consumption sample hold circuit - Google Patents

1.25GHz broadband self-bias low-power-consumption sample hold circuit Download PDF

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CN115378433B
CN115378433B CN202210910174.6A CN202210910174A CN115378433B CN 115378433 B CN115378433 B CN 115378433B CN 202210910174 A CN202210910174 A CN 202210910174A CN 115378433 B CN115378433 B CN 115378433B
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mos tube
mos
switch
electrode
source electrode
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CN115378433A (en
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郑宾
初飞
王宗民
张铁良
纪亚飞
黄策策
孙丹
杨鑫
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Beijing Microelectronic Technology Institute
Mxtronics Corp
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Beijing Microelectronic Technology Institute
Mxtronics Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Theoretical Computer Science (AREA)
  • Amplifiers (AREA)

Abstract

The invention discloses a 1.25GHz broadband self-bias low-power-consumption sample hold circuit, which comprises: gate voltage bootstrap switches BSW1 to 4, sampling capacitors Cs1 to 2, MOS switch SW1, and fully differential operational amplifier AMP; the left polar plate of Cs1 is connected with the input signal VP through BSW1 and is connected with the output signal VOM through BSW 3; the Cs1 right polar plate is connected with the AMP negative input end; the Cs2 left polar plate is connected with an input signal VM through BSW2 and is connected with an output signal VOP through BSW 4; the Cs2 right polar plate is connected with the AMP positive input end; the Cs1 right polar plate and the Cs2 right polar plate are both input with a common mode level V CM . The invention adopts the self-bias technology, the input stage circuit can work normally without inputting bias current from a reference source, and meanwhile, the common-mode negative feedback module of the operational amplifier is saved.

Description

1.25GHz broadband self-bias low-power-consumption sample hold circuit
Technical Field
The invention belongs to the technical field of analog-to-digital converters, and particularly relates to a 1.25GHz broadband self-bias low-power-consumption sample hold circuit.
Background
In recent years, the design level of the integrated circuit industry is rapidly improved, and the related communication media field is also greatly developed. The performance of an analog-to-digital converter, which is the medium connecting analog and digital signals, directly determines the overall performance of an information handling system. With the rapid development of the fields of new generation 5G communication systems, digital signal processing, signal chain systems and the like, the requirements on the low-power-consumption, high-speed and high-precision analog-digital converter are also higher and higher.
The sample hold circuit is one of key modules of the analog-to-digital converter with the pipeline structure and is positioned at the front end of the whole circuit. The method has the function of sampling continuous analog signals at equal intervals, discretizing the signals and keeping the signals for a period of time for further processing by a later-stage circuit. The performance of the sample-and-hold circuit directly determines the conversion speed and accuracy of the analog-to-digital converter, so that a sample-and-hold circuit with low power consumption, low noise and high bandwidth needs to be designed.
Disclosure of Invention
The technical solution of the invention is as follows: the self-bias low-power-consumption sampling hold circuit for the 1.25GHz broadband is provided, the self-bias technology is adopted to improve the existing sampling hold circuit, and the problem of larger power consumption of the existing sampling hold circuit is solved.
In order to solve the technical problems, the invention discloses a 1.25GHz broadband self-bias low-power-consumption sample hold circuit, which comprises: the gate voltage bootstrapping switch BSW1, the gate voltage bootstrapping switch BSW2, the gate voltage bootstrapping switch BSW3, the gate voltage bootstrapping switch BSW4, the sampling capacitor Cs1, the sampling capacitor Cs2, the MOS switch SW1 and the fully differential operational amplifier AMP;
the left polar plate of the sampling capacitor Cs1 is connected with the input signal VP through a gate voltage bootstrap switch BSW1, and is connected with the output signal VOM through a gate voltage bootstrap switch BSW 3; the right polar plate of the sampling capacitor Cs1 is connected with the negative input end of the fully differential operational amplifier AMP;
the left polar plate of the sampling capacitor Cs2 is connected with the input signal VM through a gate voltage bootstrapping switch BSW2 and is connected with the output signal VOP through a gate voltage bootstrapping switch BSW 4; the right polar plate of the sampling capacitor Cs2 is connected with the positive input end of the fully differential operational amplifier AMP;
the right polar plate of the sampling capacitor Cs1 and the right polar plate of the sampling capacitor Cs2 are input togetherMode level V CM ；
The output signal VOM and the output signal VOP are connected through the MOS switch SW 1.
In the above 1.25GHz broadband self-bias low-power-consumption sample-and-hold circuit, the fully differential operational amplifier AMP includes: auxiliary operational amplifier A1, auxiliary operational amplifier A2, MOS tube M1, MOS tube M2, MOS tube M3, MOS tube M4, MOS tube M5, MOS tube M6, MOS tube M7, MOS tube M8, MOS tube M9, MOS tube M10, MOS switch S1, MOS switch S2 and MOS switch S3;
MOS tube M1 grid and input signal Vin + Is connected with the output signal VOUT through the MOS switch S2 - The drain electrode of the MOS tube M5 is connected with the drain electrode of the MOS tube M7, and is simultaneously connected with an input signal Vin through a MOS switch S1 - The MOS transistor M2 is connected with the grid electrode of the MOS transistor M; the drain electrode of the MOS tube M1 is connected with the drain electrode of the MOS tube M3, the source electrode of the MOS tube M5 and the positive input end of the auxiliary operational amplifier A1; the source electrode of the MOS tube M1 is grounded;
the grid electrode of the MOS tube M2 is connected with the output signal VOUT through the MOS switch S3 + The drain electrode of the MOS tube M6 is connected with the drain electrode of the MOS tube M8; the drain electrode of the MOS tube M2 is connected with the drain electrode of the MOS tube M4, the source electrode of the MOS tube M6 and the negative input end of the auxiliary operational amplifier A1; the source electrode of the MOS tube M2 is grounded;
the grid electrode of the MOS tube M3 and the grid electrode of the MOS tube M4 are connected with a bias signal Vb1_AMP; the source electrode of the MOS tube M3 is grounded, and the source electrode of the MOS tube M4 is grounded;
the grid electrode of the MOS tube M5 is connected with the negative output end of the auxiliary operational amplifier A1;
the grid electrode of the MOS tube M6 is connected with the positive output end of the auxiliary operational amplifier A1;
the grid electrode of the MOS tube M7 is connected with the negative output end of the auxiliary operational amplifier A2; the source electrode of the MOS tube M7 is connected with the drain electrode of the MOS tube M9 and the positive input end of the auxiliary operational amplifier A2;
the grid electrode of the MOS tube M8 is connected with the positive output end of the auxiliary operational amplifier A2; the source electrode of the MOS tube M8 is connected with the drain electrode of the MOS tube M10 and the negative input end of the auxiliary operational amplifier A2;
the grid electrode of the MOS tube M9 and the grid electrode of the MOS tube M10 are connected with a bias signal Vb2_AMP; the source electrode of the MOS tube M9 and the source electrode of the MOS tube M10 are both connected with power supplies.
In the above 1.25GHz broadband self-bias low-power-consumption sample-and-hold circuit, the auxiliary operational amplifier A1 comprises: MOS tube MP1, MOS tube MP2, MOS tube MP3, MOS tube MP4, MOS tube MP5, MOS tube MP6, MOS tube MP7, MOS tube MN1, MOS tube MN2, MOS tube MN3 and MOS tube MN4;
MOS tube MP1 grid and input signal Vin + A1 is connected; the source electrode of the MOS tube MP1 is connected with the source electrode of the MOS tube MP2 and the drain electrode of the MOS tube MP 3; the drain electrode of the MOS tube MP1 is connected with the drain electrode of the MOS tube MN1 and the source electrode of the MOS tube MN 3;
MOS tube MP2 grid and input signal Vin - A1 is connected; the drain electrode of the MOS tube MP2 is connected with the drain electrode of the MOS tube MN2 and the source electrode of the MOS tube MN4;
the grid electrode of the MOS tube MP3, the grid electrode of the MOS tube MP6 and the grid electrode of the MOS tube MP7 are connected with the bias signal Vb4_A1; the source electrode of the MOS tube MP3, the source electrode of the MOS tube MP6 and the source electrode of the MOS tube MP7 are all connected with power supplies; the drain electrode of the MOS tube MP6 is connected with the source electrode of the MOS tube MP 4; the drain electrode of the MOS tube MP7 is connected with the source electrode of the MOS tube MP 5;
the grid electrode of the MOS tube MP4 and the grid electrode of the MOS tube MP5 are connected with the bias signal Vb3_A1; MOS tube MP4 drain electrode, MOS tube MN3 drain electrode and output signal VOUT - A1 is connected;
MOS tube MP5 drain electrode, MOS tube MN4 drain electrode and output signal VOUT + A1 is connected;
the grid electrode of the MOS tube MN3 and the grid electrode of the MOS tube MN4 are connected with the bias signal Vb2_A1; the grid electrode of the MOS tube MN1 and the grid electrode of the MOS tube MN2 are connected with the bias signal Vb1_A1; the source electrode of the MOS tube MN1 and the source electrode of the MOS tube MN2 are grounded.
In the above 1.25GHz broadband self-bias low-power-consumption sample-and-hold circuit, the auxiliary operational amplifier A2 comprises: MOS tube MN5, MOS tube MN6, MOS tube MN7, MOS tube MN8, MOS tube MN9, MOS tube MN10, MOS tube MN11, MOS tube MP8, MOS tube MP9, MOS tube MP10 and MOS tube MP11;
MOS tube MN5 grid electrode and input signal Vin - A2 is connected; the source electrode of the MOS tube MN5 is connected with the source electrode of the MOS tube MN6 and the drain electrode of the MOS tube MN 7; the drain electrode of the MOS tube MN5 is connected with the source electrode of the MOS tube MP8 and the drain electrode of the MOS tube MP 10;
MOS tube MN6 grid electrode and input signal Vin + A2 is connected; the drain electrode of the MOS tube MN6 is connected with the MP9 source electrode and the MP11 drain electrode;
the grid electrode of the MOS tube MN7, the grid electrode of the MOS tube MN8 and the grid electrode of the MOS tube MN9 are connected with the bias signal Vb1_A2; the source electrode of the MOS tube MN7, the source electrode of the MOS tube MN8 and the source electrode of the MOS tube MN9 are all grounded; the drain electrode of the MOS tube MN8 is connected with the source electrode of the MOS tube MN 10; the drain electrode of the MOS tube MN9 is connected with the source electrode of the MOS tube MN 11;
the grid electrode of the MOS tube MN10 and the grid electrode of the MOS tube MN11 are connected with the bias signal Vb2_A2; MOS tube MN10 drain electrode, MOS tube MP8 drain electrode and output signal VOUT + A2 is connected;
MOS tube MN11 drain electrode, MOS tube MP9 drain electrode and output signal VOUT - A2 is connected;
the grid electrode of the MOS tube MP8 and the grid electrode of the MOS tube MP9 are connected with the bias signal Vb3_A2; the grid electrode of the MOS tube MP10 and the grid electrode of the MOS tube MP11 are connected with the bias signal Vb4_A2; the source electrode of the MOS tube MP10 and the source electrode of the MOS tube MP11 are both connected with a power supply.
In the 1.25GHz broadband self-bias low-power-consumption sample hold circuit, the working time sequence of the sample hold circuit is controlled by a two-phase non-overlapping clock; the working time sequence of the grid voltage bootstrapping switch BSW1 and the grid voltage bootstrapping switch BSW2 is phi 1; the working time sequence of the gate voltage bootstrapping switch BSW3, the gate voltage bootstrapping switch BSW4 and the MOS switch SW1 is phi 2; the phi 1 and phi 2 phases do not overlap and are inverted; the operation timings of the MOS switch S1, the MOS switch S2, and the MOS switch S3 are Φ3.
In the 1.25GHz broadband self-bias low-power-consumption sample-hold circuit, the sample-hold circuit comprises two working phases: a sampling stage and a holding stage; wherein, the gate voltage bootstrapping switch BSW1 and the gate voltage bootstrapping switch BSW2 are closed in the sampling stage and opened in the holding stage; the gate voltage bootstrapping switch BSW3 and the gate voltage bootstrapping switch BSW4 are opened in a sampling stage and closed in a holding stage; the MOS switch SW1, the MOS switch S2 and the MOS switch S3 are closed in the sampling phase and open in the holding phase.
In the 1.25GHz broadband self-bias low-power-consumption sample-hold circuit, when the sample-hold circuit is in a sampling stage, the sampling stage comprises:
the gate voltage bootstrapping switch BSW1 and the gate voltage bootstrapping switch BSW2 are closed, the gate voltage bootstrapping switch BSW3 and the gate voltage bootstrapping switch BSW4 are opened, an input signal VP and an input signal VM are respectively connected with a left polar plate of the sampling capacitor Cs1 and a left polar plate of the sampling capacitor Cs2, and at the moment, the input signal is sampled to the left polar plate of the sampling capacitor; meanwhile, the MOS switch SW1, the MOS switch S2 and the MOS switch S3 are closed, the input end of the fully differential operational amplifier AMP is connected with the output end, and the output end outputs common-mode electricityFlat V CM 。
In the 1.25GHz broadband self-bias low-power-consumption sample-and-hold circuit, when the sample-and-hold circuit is in a hold phase, there are:
the gate voltage bootstrapping switch BSW1 and the gate voltage bootstrapping switch BSW2 are opened, the gate voltage bootstrapping switch BSW3 and the gate voltage bootstrapping switch BSW4 are closed, the left polar plate of the sampling capacitor Cs1 is connected with the output signal VOM, and the left polar plate of the sampling capacitor Cs2 is connected with the output signal VOP; meanwhile, the MOS switch SW1, the MOS switch S2 and the MOS switch S3 are turned off, the fully differential operational amplifier AMP is in an amplified state, and the output terminal outputs a hold level.
In the 1.25GHz broadband self-bias low-power-consumption sample hold circuit, the MOS tube M1 and the MOS tube M2 adopt a self-bias technology, and the circuit power consumption is reduced by saving bias current.
In the 1.25GHz broadband self-bias low-power-consumption sample hold circuit, the MOS switch S1, the MOS switch S2 and the MOS switch S3 adopt NMOS tubes or PMOS tubes.
The invention has the following advantages:
(1) The invention discloses a 1.25GHz broadband self-bias low-power-consumption sample hold circuit, wherein the input end of a fully differential operational amplifier adopts a self-bias technology, and compared with the input end structure of a traditional fully differential operational amplifier, the self-bias low-power-consumption sample hold circuit can normally work without inputting bias current from a reference source, thereby avoiding the influence of bias current change on circuit performance, further improving the anti-interference capability of the circuit on the environment and reducing the circuit power consumption.
(2) The invention discloses a 1.25GHz broadband self-bias low-power-consumption sampling and holding circuit, wherein an MOS switch S1, an MOS switch S2 and an MOS switch S3 are added in a fully differential operational amplifier, and when the sampling and holding circuit is in a sampling working state, the MOS switch S1, the MOS switch S2 and the MOS switch S3 are closed, and the fully differential operational amplifier outputs a common mode level; when the sample hold circuit is in a hold operation state, the MOS switch S1, the MOS switch S2, and the MOS switch S3 are turned off, and the fully differential operational amplifier enters an amplification state. Compared with the traditional fully differential operational amplifier structure, the invention saves a common mode negative feedback module and greatly reduces the area and the power consumption of a sampling hold circuit.
Drawings
FIG. 1 is a schematic diagram of a topology of a 1.25GHz broadband self-bias low-power-consumption sample-and-hold circuit in an embodiment of the invention;
fig. 2 is a schematic diagram of a topology of a fully differential operational amplifier AMP according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a topology of an auxiliary operational amplifier A1 according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a topology of an auxiliary op-amp A2 according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of the operation timing sequence of a 1.25GHz broadband self-bias low-power-consumption sample-and-hold circuit in an embodiment of the invention;
fig. 6 is a diagram of a spectrum simulation result of a 1.25GHz broadband self-bias low power consumption sample-and-hold circuit in an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the embodiments of the present invention disclosed herein will be described in further detail with reference to the accompanying drawings.
As shown in fig. 1, in this embodiment, the 1.25GHz broadband self-bias low-power-consumption sample-and-hold circuit includes: the gate voltage bootstrapping switch BSW1, the gate voltage bootstrapping switch BSW2, the gate voltage bootstrapping switch BSW3, the gate voltage bootstrapping switch BSW4, the sampling capacitor Cs1, the sampling capacitor Cs2, the MOS switch SW1, and the fully differential operational amplifier AMP. The left polar plate of the sampling capacitor Cs1 is connected with the input signal VP through a gate voltage bootstrap switch BSW1, and is connected with the output signal VOM through a gate voltage bootstrap switch BSW 3; the right polar plate of the sampling capacitor Cs1 is connected with the negative input end of the fully differential operational amplifier AMP; the left polar plate of the sampling capacitor Cs2 is connected with the input signal VM through a gate voltage bootstrapping switch BSW2 and is connected with the output signal VOP through a gate voltage bootstrapping switch BSW 4; the right polar plate of the sampling capacitor Cs2 is connected with the positive input end of the fully differential operational amplifier AMP; the right polar plate of the sampling capacitor Cs1 and the right polar plate of the sampling capacitor Cs2 both input common mode level V CM The method comprises the steps of carrying out a first treatment on the surface of the The output signal VOM and the output signal VOP are connected through the MOS switch SW 1.
In the present embodiment, as shown in FIG. 2, the full differential operationThe amplifier AMP may specifically include: auxiliary operational amplifier A1, auxiliary operational amplifier A2, MOS tube M1, MOS tube M2, MOS tube M3, MOS tube M4, MOS tube M5, MOS tube M6, MOS tube M7, MOS tube M8, MOS tube M9, MOS tube M10, MOS switch S1, MOS switch S2 and MOS switch S3. Wherein, the grid electrode of the MOS tube M1 and the input signal Vin + Is connected with the output signal VOUT through the MOS switch S2 - The drain electrode of the MOS tube M5 is connected with the drain electrode of the MOS tube M7, and is simultaneously connected with an input signal Vin through a MOS switch S1 - The MOS transistor M2 is connected with the grid electrode of the MOS transistor M; the drain electrode of the MOS tube M1 is connected with the drain electrode of the MOS tube M3, the source electrode of the MOS tube M5 and the positive input end of the auxiliary operational amplifier A1; the source electrode of the MOS tube M1 is grounded; the grid electrode of the MOS tube M2 is connected with the output signal VOUT through the MOS switch S3 + The drain electrode of the MOS tube M6 is connected with the drain electrode of the MOS tube M8; the drain electrode of the MOS tube M2 is connected with the drain electrode of the MOS tube M4, the source electrode of the MOS tube M6 and the negative input end of the auxiliary operational amplifier A1; the source electrode of the MOS tube M2 is grounded; the grid electrode of the MOS tube M3 and the grid electrode of the MOS tube M4 are connected with a bias signal Vb1_AMP; the source electrode of the MOS tube M3 is grounded, and the source electrode of the MOS tube M4 is grounded; the grid electrode of the MOS tube M5 is connected with the negative output end of the auxiliary operational amplifier A1; the grid electrode of the MOS tube M6 is connected with the positive output end of the auxiliary operational amplifier A1; the grid electrode of the MOS tube M7 is connected with the negative output end of the auxiliary operational amplifier A2; the source electrode of the MOS tube M7 is connected with the drain electrode of the MOS tube M9 and the positive input end of the auxiliary operational amplifier A2; the grid electrode of the MOS tube M8 is connected with the positive output end of the auxiliary operational amplifier A2; the source electrode of the MOS tube M8 is connected with the drain electrode of the MOS tube M10 and the negative input end of the auxiliary operational amplifier A2; the grid electrode of the MOS tube M9 and the grid electrode of the MOS tube M10 are connected with a bias signal Vb2_AMP; the source electrode of the MOS tube M9 and the source electrode of the MOS tube M10 are both connected with power supplies.
In this embodiment, as shown in fig. 3, the auxiliary op-amp A1 may specifically include: MOS tube MP1, MOS tube MP2, MOS tube MP3, MOS tube MP4, MOS tube MP5, MOS tube MP6, MOS tube MP7, MOS tube MN1, MOS tube MN2, MOS tube MN3 and MOS tube MN4. Wherein, the grid electrode of the MOS tube MP1 and the input signal Vin + A1 is connected; the source electrode of the MOS tube MP1 is connected with the source electrode of the MOS tube MP2 and the drain electrode of the MOS tube MP 3; the drain electrode of the MOS tube MP1 is connected with the drain electrode of the MOS tube MN1 and the source electrode of the MOS tube MN 3; MOS tube MP2 grid and input signal Vin - A1 is connected; the drain electrode of the MOS tube MP2 is connected with the drain electrode of the MOS tube MN2 and the source electrode of the MOS tube MN4; the grid electrode of the MOS tube MP3, the grid electrode of the MOS tube MP6 and the grid electrode of the MOS tube MP7 are connected with the bias signal Vb4_A1; the source electrode of the MOS tube MP3, the source electrode of the MOS tube MP6 and the source electrode of the MOS tube MP7 are all connected with power supplies; MOS tube MP6 drain electrodeThe source electrode of the MOS tube MP4 is connected; the drain electrode of the MOS tube MP7 is connected with the source electrode of the MOS tube MP 5; the grid electrode of the MOS tube MP4 and the grid electrode of the MOS tube MP5 are connected with the bias signal Vb3_A1; MOS tube MP4 drain electrode, MOS tube MN3 drain electrode and output signal VOUT - A1 is connected; MOS tube MP5 drain electrode, MOS tube MN4 drain electrode and output signal VOUT + A1 is connected; the grid electrode of the MOS tube MN3 and the grid electrode of the MOS tube MN4 are connected with the bias signal Vb2_A1; the grid electrode of the MOS tube MN1 and the grid electrode of the MOS tube MN2 are connected with the bias signal Vb1_A1; the source electrode of the MOS tube MN1 and the source electrode of the MOS tube MN2 are grounded.
In this embodiment, as shown in fig. 4, the auxiliary op-amp A2 may specifically include: MOS pipe MN5, MOS pipe MN6, MOS pipe MN7, MOS pipe MN8, MOS pipe MN9, MOS pipe MN10, MOS pipe MN11, MOS pipe MP8, MOS pipe MP9, MOS pipe MP10 and MOS pipe MP11. Wherein, the grid electrode of the MOS tube MN5 and the input signal Vin - A2 is connected; the source electrode of the MOS tube MN5 is connected with the source electrode of the MOS tube MN6 and the drain electrode of the MOS tube MN 7; the drain electrode of the MOS tube MN5 is connected with the source electrode of the MOS tube MP8 and the drain electrode of the MOS tube MP 10; MOS tube MN6 grid electrode and input signal Vin + A2 is connected; the drain electrode of the MOS tube MN6 is connected with the MP9 source electrode and the MP11 drain electrode; the grid electrode of the MOS tube MN7, the grid electrode of the MOS tube MN8 and the grid electrode of the MOS tube MN9 are connected with the bias signal Vb1_A2; the source electrode of the MOS tube MN7, the source electrode of the MOS tube MN8 and the source electrode of the MOS tube MN9 are all grounded; the drain electrode of the MOS tube MN8 is connected with the source electrode of the MOS tube MN 10; the drain electrode of the MOS tube MN9 is connected with the source electrode of the MOS tube MN 11; the grid electrode of the MOS tube MN10 and the grid electrode of the MOS tube MN11 are connected with the bias signal Vb2_A2; MOS tube MN10 drain electrode, MOS tube MP8 drain electrode and output signal VOUT + A2 is connected; MOS tube MN11 drain electrode, MOS tube MP9 drain electrode and output signal VOUT - A2 is connected; the grid electrode of the MOS tube MP8 and the grid electrode of the MOS tube MP9 are connected with the bias signal Vb3_A2; the grid electrode of the MOS tube MP10 and the grid electrode of the MOS tube MP11 are connected with the bias signal Vb4_A2; the source electrode of the MOS tube MP10 and the source electrode of the MOS tube MP11 are both connected with a power supply.
In this embodiment, as shown in fig. 5, the operation timing of the sample-and-hold circuit is controlled by a two-phase non-overlapping clock; the working time sequence of the grid voltage bootstrapping switch BSW1 and the grid voltage bootstrapping switch BSW2 is phi 1; the working time sequence of the gate voltage bootstrapping switch BSW3, the gate voltage bootstrapping switch BSW4 and the MOS switch SW1 is phi 2; the operation timings of the MOS switch S1, the MOS switch S2, and the MOS switch S3 are Φ3. The phases Φ1 and Φ2 do not overlap and are inverted, and the phases Φ1 and Φ3 are the same and are inverted.
In this embodiment, the sample-and-hold circuit includes two phases of operation: a sampling stage and a holding stage; wherein, the gate voltage bootstrapping switch BSW1 and the gate voltage bootstrapping switch BSW2 are closed in the sampling stage and opened in the holding stage; the gate voltage bootstrapping switch BSW3 and the gate voltage bootstrapping switch BSW4 are opened in a sampling stage and closed in a holding stage; the MOS switch SW1, the MOS switch S2 and the MOS switch S3 are closed in the sampling phase and open in the holding phase.
In this embodiment, when the sample-and-hold circuit is in the sampling phase, there are: the gate voltage bootstrapping switch BSW1 and the gate voltage bootstrapping switch BSW2 are closed, the gate voltage bootstrapping switch BSW3 and the gate voltage bootstrapping switch BSW4 are opened, an input signal VP and an input signal VM are respectively connected with a left polar plate of the sampling capacitor Cs1 and a left polar plate of the sampling capacitor Cs2, and at the moment, the input signal is sampled to the left polar plate of the sampling capacitor; meanwhile, the MOS switch SW1, the MOS switch S2 and the MOS switch S3 are closed, the input end of the fully differential operational amplifier AMP is connected with the output end, and the output end outputs the common mode level V CM 。
In the present embodiment, when the sample-and-hold circuit is in the hold phase, there are: the gate voltage bootstrapping switch BSW1 and the gate voltage bootstrapping switch BSW2 are opened, the gate voltage bootstrapping switch BSW3 and the gate voltage bootstrapping switch BSW4 are closed, the left polar plate of the sampling capacitor Cs1 is connected with the output signal VOM, and the left polar plate of the sampling capacitor Cs2 is connected with the output signal VOP; meanwhile, the MOS switch SW1, the MOS switch S2 and the MOS switch S3 are turned off, the fully differential operational amplifier AMP is in an amplified state, and the output terminal outputs a hold level.
In this embodiment, the MOS transistor M1 and the MOS transistor M2 adopt a self-bias technique, and reduce circuit power consumption by saving bias current. The MOS switch S1, the MOS switch S2 and the MOS switch S3 adopt NMOS tubes or PMOS tubes.
According to the application scene of the sample hold circuit, the fully differential operational amplifier AMP needs to meet the requirements of high gain, high bandwidth, high input/output voltage swing and high linearity, so that the gain bootstrap folding type cascode structure is adopted, and the gain of the operational amplifier is improved by improving the output impedance. Fig. 2 is a schematic diagram of an AMP topology of a fully differential operational amplifier according to the present invention. The auxiliary operational amplifier A1 and the auxiliary operational amplifier A2 both adopt folding type common-source common-gate structures, and the MOS tube M1 and the MOS tube M2 adopt NMOS tubes as input stages. Compared with single-ended input, the full-differential structure can obtain larger output swing, has good common mode rejection characteristic and has higher linearity. The gain bootstrap technology is introduced by adding the auxiliary operational amplifiers A1 and A2, so that the MOS tube M5, the MOS tube M6, the MOS tube M7 and the MOS tube M8 are in a current-voltage negative feedback loop, the output impedance of the circuit is improved, the gain of the circuit is improved, and the low-frequency small signal gain |A of the full-differential operational amplifier AMP at the moment can be calculated V The I is:
|A V |≈g m1 {[A 1 g m5 r 05 (r 01 //r 03 )]//(A 2 g m7 r 07 r 09 )}
wherein A is 1 Representing the low-frequency small signal gain of the auxiliary operational amplifier A1, A 2 Low frequency small signal gain g representing auxiliary operational amplifier A2 m1 Representing the transconductance, g, of MOS transistor M1 m5 Representing the transconductance, g, of MOS transistor M5 m7 Represents the transconductance, r, of the MOS tube M7 01 Represents the channel resistance, r, of the MOS tube M1 03 Represents the channel resistance, r, of the MOS tube M3 05 Represents the channel resistance, r, of the MOS tube M5 07 Represents the channel resistance, r, of the MOS tube M7 09 The channel resistance of the MOS transistor M9 is shown.
Compared with a folding type cascade structure, the gain is obviously improved.
FIG. 6 is a graph of the spectrum simulation result of the 1.25GHz broadband self-bias low-power-consumption sample-and-hold circuit, under the simulation conditions of 1.8V power supply voltage, tt process angle, 27 ℃ ambient temperature and 310MHz clock sampling frequency, sinusoidal signals with 150MHz and 640mV are input for simulation, and the power consumption of the sample-and-hold circuit is calculated to be about 43mW. And carrying out FFT (fast Fourier transform) on the output signal of the sample hold circuit, and calculating to obtain the output signal with 85dB signal-to-noise ratio, 96dB spurious-free dynamic range and 13.8 effective bits. Simulation shows that the invention has great improvement in power consumption and performance and application value.
Although the present invention has been described in terms of the preferred embodiments, it is not intended to be limited to the embodiments, and any person skilled in the art can make any possible variations and modifications to the technical solution of the present invention by using the methods and technical matters disclosed above without departing from the spirit and scope of the present invention, so any simple modifications, equivalent variations and modifications to the embodiments described above according to the technical matters of the present invention are within the scope of the technical matters of the present invention.
What is not described in detail in the present specification belongs to the known technology of those skilled in the art.

Claims (9)

1. A 1.25GHz broadband self-biasing low-power sample-and-hold circuit, comprising: the gate voltage bootstrapping switch BSW1, the gate voltage bootstrapping switch BSW2, the gate voltage bootstrapping switch BSW3, the gate voltage bootstrapping switch BSW4, the sampling capacitor Cs1, the sampling capacitor Cs2, the MOS switch SW1 and the fully differential operational amplifier AMP;
the left polar plate of the sampling capacitor Cs1 is connected with the input signal VP through a gate voltage bootstrap switch BSW1, and is connected with the output signal VOM through a gate voltage bootstrap switch BSW 3; the right polar plate of the sampling capacitor Cs1 is connected with the negative input end of the fully differential operational amplifier AMP;
the left polar plate of the sampling capacitor Cs2 is connected with the input signal VM through a gate voltage bootstrapping switch BSW2 and is connected with the output signal VOP through a gate voltage bootstrapping switch BSW 4; the right polar plate of the sampling capacitor Cs2 is connected with the positive input end of the fully differential operational amplifier AMP;
the right polar plate of the sampling capacitor Cs1 and the right polar plate of the sampling capacitor Cs2 both input common mode level V CM ；
The output signal VOM and the output signal VOP are connected through the MOS switch SW 1;
a fully differential operational amplifier AMP comprising: auxiliary operational amplifier A1, auxiliary operational amplifier A2, MOS tube M1, MOS tube M2, MOS tube M3, MOS tube M4, MOS tube M5, MOS tube M6, MOS tube M7, MOS tube M8, MOS tube M9, MOS tube M10, MOS switch S1, MOS switch S2 and MOS switch S3;
MOS tube M1 grid and input signal Vin + Is connected with the output signal VOUT through the MOS switch S2 - MOS transistor M5 drain and MOSThe drain electrode of the tube M7 is connected with the input signal Vin through the MOS switch S1 - The MOS transistor M2 is connected with the grid electrode of the MOS transistor M; the drain electrode of the MOS tube M1 is connected with the drain electrode of the MOS tube M3, the source electrode of the MOS tube M5 and the positive input end of the auxiliary operational amplifier A1; the source electrode of the MOS tube M1 is grounded;
the grid electrode of the MOS tube M2 is connected with the output signal VOUT through the MOS switch S3 + The drain electrode of the MOS tube M6 is connected with the drain electrode of the MOS tube M8; the drain electrode of the MOS tube M2 is connected with the drain electrode of the MOS tube M4, the source electrode of the MOS tube M6 and the negative input end of the auxiliary operational amplifier A1; the source electrode of the MOS tube M2 is grounded;
the grid electrode of the MOS tube M3 and the grid electrode of the MOS tube M4 are connected with a bias signal Vb1_AMP; the source electrode of the MOS tube M3 is grounded, and the source electrode of the MOS tube M4 is grounded;
the grid electrode of the MOS tube M5 is connected with the negative output end of the auxiliary operational amplifier A1;
the grid electrode of the MOS tube M6 is connected with the positive output end of the auxiliary operational amplifier A1;
the grid electrode of the MOS tube M7 is connected with the negative output end of the auxiliary operational amplifier A2; the source electrode of the MOS tube M7 is connected with the drain electrode of the MOS tube M9 and the positive input end of the auxiliary operational amplifier A2;
the grid electrode of the MOS tube M8 is connected with the positive output end of the auxiliary operational amplifier A2; the source electrode of the MOS tube M8 is connected with the drain electrode of the MOS tube M10 and the negative input end of the auxiliary operational amplifier A2;
the grid electrode of the MOS tube M9 and the grid electrode of the MOS tube M10 are connected with a bias signal Vb2_AMP; the source electrode of the MOS tube M9 and the source electrode of the MOS tube M10 are both connected with power supplies.
2. The 1.25GHz broadband self-biasing low power sample-and-hold circuit of claim 1, wherein the auxiliary op-amp A1 comprises: MOS tube MP1, MOS tube MP2, MOS tube MP3, MOS tube MP4, MOS tube MP5, MOS tube MP6, MOS tube MP7, MOS tube MN1, MOS tube MN2, MOS tube MN3 and MOS tube MN4;
MOS tube MP1 grid and input signal Vin + A1 is connected; the source electrode of the MOS tube MP1 is connected with the source electrode of the MOS tube MP2 and the drain electrode of the MOS tube MP 3; the drain electrode of the MOS tube MP1 is connected with the drain electrode of the MOS tube MN1 and the source electrode of the MOS tube MN 3;
MOS tube MP2 grid and input signal Vin - A1 is connected; the drain electrode of the MOS tube MP2 is connected with the drain electrode of the MOS tube MN2 and the source electrode of the MOS tube MN4;
the grid electrode of the MOS tube MP3, the grid electrode of the MOS tube MP6 and the grid electrode of the MOS tube MP7 are connected with the bias signal Vb4_A1; the source electrode of the MOS tube MP3, the source electrode of the MOS tube MP6 and the source electrode of the MOS tube MP7 are all connected with power supplies; the drain electrode of the MOS tube MP6 is connected with the source electrode of the MOS tube MP 4; the drain electrode of the MOS tube MP7 is connected with the source electrode of the MOS tube MP 5;
the grid electrode of the MOS tube MP4 and the grid electrode of the MOS tube MP5 are connected with the bias signal Vb3_A1; MOS tube MP4 drain electrode, MOS tube MN3 drain electrode and output signal VOUT - A1 is connected;
MOS tube MP5 drain electrode, MOS tube MN4 drain electrode and output signal VOUT + A1 is connected;
the grid electrode of the MOS tube MN3 and the grid electrode of the MOS tube MN4 are connected with the bias signal Vb2_A1; the grid electrode of the MOS tube MN1 and the grid electrode of the MOS tube MN2 are connected with the bias signal Vb1_A1; the source electrode of the MOS tube MN1 and the source electrode of the MOS tube MN2 are grounded.
3. The 1.25GHz broadband self-biasing low power sample-and-hold circuit of claim 1, wherein the auxiliary op-amp A2 comprises: MOS tube MN5, MOS tube MN6, MOS tube MN7, MOS tube MN8, MOS tube MN9, MOS tube MN10, MOS tube MN11, MOS tube MP8, MOS tube MP9, MOS tube MP10 and MOS tube MP11;
MOS tube MN5 grid electrode and input signal Vin - A2 is connected; the source electrode of the MOS tube MN5 is connected with the source electrode of the MOS tube MN6 and the drain electrode of the MOS tube MN 7; the drain electrode of the MOS tube MN5 is connected with the source electrode of the MOS tube MP8 and the drain electrode of the MOS tube MP 10;
MOS tube MN6 grid electrode and input signal Vin + A2 is connected; the drain electrode of the MOS tube MN6 is connected with the MP9 source electrode and the MP11 drain electrode;
the grid electrode of the MOS tube MN7, the grid electrode of the MOS tube MN8 and the grid electrode of the MOS tube MN9 are connected with the bias signal Vb1_A2; the source electrode of the MOS tube MN7, the source electrode of the MOS tube MN8 and the source electrode of the MOS tube MN9 are all grounded; the drain electrode of the MOS tube MN8 is connected with the source electrode of the MOS tube MN 10; the drain electrode of the MOS tube MN9 is connected with the source electrode of the MOS tube MN 11;
the grid electrode of the MOS tube MN10 and the grid electrode of the MOS tube MN11 are connected with the bias signal Vb2_A2; MOS tube MN10 drain electrode, MOS tube MP8 drain electrode and output signal VOUT + A2 is connected;
MOS tube MN11 drain electrode, MOS tube MP9 drain electrode and output signal VOUT - A2 is connected;
the grid electrode of the MOS tube MP8 and the grid electrode of the MOS tube MP9 are connected with the bias signal Vb3_A2; the grid electrode of the MOS tube MP10 and the grid electrode of the MOS tube MP11 are connected with the bias signal Vb4_A2; the source electrode of the MOS tube MP10 and the source electrode of the MOS tube MP11 are both connected with a power supply.
4. The 1.25GHz broadband self-biasing low power consumption sample-and-hold circuit of claim 1, wherein the sample-and-hold circuit is operated with a two-phase non-overlapping clock; the working time sequence of the grid voltage bootstrapping switch BSW1 and the grid voltage bootstrapping switch BSW2 is phi 1; the working time sequence of the gate voltage bootstrapping switch BSW3, the gate voltage bootstrapping switch BSW4 and the MOS switch SW1 is phi 2; the phi 1 and phi 2 phases do not overlap and are inverted; the operation timings of the MOS switch S1, the MOS switch S2, and the MOS switch S3 are Φ3.
5. The 1.25GHz broadband self-biasing low power sample-and-hold circuit of claim 1, wherein the sample-and-hold circuit comprises two phases of operation: a sampling stage and a holding stage; wherein, the gate voltage bootstrapping switch BSW1 and the gate voltage bootstrapping switch BSW2 are closed in the sampling stage and opened in the holding stage; the gate voltage bootstrapping switch BSW3 and the gate voltage bootstrapping switch BSW4 are opened in a sampling stage and closed in a holding stage; the MOS switch SW1, the MOS switch S2 and the MOS switch S3 are closed in the sampling phase and open in the holding phase.
6. The 1.25GHz broadband self-biasing low power sample-and-hold circuit of claim 5, wherein when the sample-and-hold circuit is in the sampling phase, there are:
the gate voltage bootstrapping switch BSW1 and the gate voltage bootstrapping switch BSW2 are closed, the gate voltage bootstrapping switch BSW3 and the gate voltage bootstrapping switch BSW4 are opened, an input signal VP and an input signal VM are respectively connected with a left polar plate of the sampling capacitor Cs1 and a left polar plate of the sampling capacitor Cs2, and at the moment, the input signal is sampled to the left polar plate of the sampling capacitor; meanwhile, the MOS switch SW1, the MOS switch S2 and the MOS switch S3 are closed, the input end of the fully differential operational amplifier AMP is connected with the output end, and the output end outputs the common mode level V CM 。
7. The 1.25GHz broadband self-biasing low power sample-and-hold circuit of claim 5, wherein when the sample-and-hold circuit is in the hold phase, there are:
the gate voltage bootstrapping switch BSW1 and the gate voltage bootstrapping switch BSW2 are opened, the gate voltage bootstrapping switch BSW3 and the gate voltage bootstrapping switch BSW4 are closed, the left polar plate of the sampling capacitor Cs1 is connected with the output signal VOM, and the left polar plate of the sampling capacitor Cs2 is connected with the output signal VOP; meanwhile, the MOS switch SW1, the MOS switch S2 and the MOS switch S3 are turned off, the fully differential operational amplifier AMP is in an amplified state, and the output terminal outputs a hold level.
8. The 1.25GHz broadband self-bias low-power-consumption sample hold circuit of claim 1, wherein the MOS transistor M1 and the MOS transistor M2 adopt a self-bias technology, and the circuit power consumption is reduced by saving bias current.
9. The 1.25GHz broadband self-bias low-power-consumption sample-and-hold circuit of claim 1, wherein the MOS switch S1, the MOS switch S2, and the MOS switch S3 are NMOS transistors or PMOS transistors.
CN202210910174.6A 2022-07-29 2022-07-29 1.25GHz broadband self-bias low-power-consumption sample hold circuit Active CN115378433B (en)

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Publication number Priority date Publication date Assignee Title
CN101277112A (en) * 2008-05-15 2008-10-01 复旦大学 Low-power consumption assembly line a/d converter by sharing operation amplifier
CN101980446A (en) * 2010-11-25 2011-02-23 复旦大学 High-performance low-power consumption pipeline analogue-to-digital converter
CN103095302A (en) * 2012-12-19 2013-05-08 天津大学 Sampling holding circuit applied to high-speed high-precision circuit
CN106160743A (en) * 2016-07-06 2016-11-23 电子科技大学 A kind of boot-strapped switch circuit for sampling hold circuit
CN107370487A (en) * 2017-07-18 2017-11-21 中国电子科技集团公司第二十四研究所 A kind of boot-strapped switch circuit based on NMOS tube

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101277112A (en) * 2008-05-15 2008-10-01 复旦大学 Low-power consumption assembly line a/d converter by sharing operation amplifier
CN101980446A (en) * 2010-11-25 2011-02-23 复旦大学 High-performance low-power consumption pipeline analogue-to-digital converter
CN103095302A (en) * 2012-12-19 2013-05-08 天津大学 Sampling holding circuit applied to high-speed high-precision circuit
CN106160743A (en) * 2016-07-06 2016-11-23 电子科技大学 A kind of boot-strapped switch circuit for sampling hold circuit
CN107370487A (en) * 2017-07-18 2017-11-21 中国电子科技集团公司第二十四研究所 A kind of boot-strapped switch circuit based on NMOS tube

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