CN103095302A - Sampling holding circuit applied to high-speed high-precision circuit - Google Patents
Sampling holding circuit applied to high-speed high-precision circuit Download PDFInfo
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- CN103095302A CN103095302A CN2012105556927A CN201210555692A CN103095302A CN 103095302 A CN103095302 A CN 103095302A CN 2012105556927 A CN2012105556927 A CN 2012105556927A CN 201210555692 A CN201210555692 A CN 201210555692A CN 103095302 A CN103095302 A CN 103095302A
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Abstract
The invention discloses a sampling holding circuit applied to a high-speed high-precision circuit. The sampling holding circuit comprises a full-differential type operational amplifier, two sampling capacitors Cs, two sampling switches S1 and five selective switches and a low-pass filter circuit formed by a resistor R1 and a capacitor C1. The full-differential type operational amplifier is a gain enhancement folding cascade full-differential type operational amplifier, a sampling switch S1 is a grid voltage bootstrap switch, connected structures of the positive end and the negative end of the full-differential type operational amplifier are completely same, and a signal input end passes through the low-pass filter circuit to be connected with a lower pole plate of the sampling capacitors Cs through the sampling switches S1. A selective switch S3 is connected with the lower pole plate of the sampling capacitors Cs and the output end of the full-differential type operational amplifier. An upper pole plate of the sampling capacitors Cs is connected with the input end of the full-differential type operational amplifier, a selective switch S4 is connected with upper pole plates of the two sampling capacitors Cs, and a selective switch S2 is connected with the input end and the output end of the full-differential type operational amplifier. The sampling holding circuit can achieve sampling holding of the input signals in the high-speed high-precision circuit.
Description
Technical field
The present invention relates to data collecting field, particularly a kind of analog signal and digital signal transfer unit.
Background technology
Sampling hold circuit is in the analogue signal processing field extensive use, particularly in analog signal and digital signal change-over circuit, need the front end input voltage signal to be gathered, and keep a period of time, for subsequent conditioning circuit, signal is processed, require the sampling hold circuit can fast reaction, sampling and maintenance precision are enough high, can satisfy the requirement of whole Circuits System, and the retention time long enough, the linearity is good.
Traditional sampling hold circuit, as shown in Figure 1, normally by an operational amplifier, a sampling capacitance, a sampling switch, two selector switches form, and its work is divided into two stages, is controlled by a two phase clock.Wherein, the phase I, switch S 1 and switch S 2 conductings, switch S 3 is closed, and circuit is in sample phase, and sampling capacitance Cs samples to input voltage signal.Second stage, switch S 1 and switch S 2 are closed, switch S 3 conductings, circuit is in the maintenance stage, sampling capacitance Cs upset, output sampled value.
The major part relevant with sampling precision and sample rate has:
Sampling switch, perfect switch should close resistance break for infinitely great, and conducting resistance is zero.The conducting resistance of switch size, and the linearity can cause very large impact to input voltage signal causes signal amplitude that the sampling capacitance sampling obtains not or produces second harmonic.
Sampling capacitance, the size of sampling capacitance can affect sample rate and precision, and sampling capacitance is too small, can cause charge discharging resisting larger on the impact of sampled signal amplitude, and sampling capacitance is excessive, and sample rate can't meet the demands.
Operational amplifier, when sampling hold circuit was in Holdover mode, the output voltage error that is caused by the limited DC current gain of amplifier was:
Wherein, A is the DC current gain of amplifier.The gain of operational amplifier and bandwidth can affect the precision of sampling.
Traditional sampling hold circuit, the deficiency of existence is mainly reflected in following several:
(1) because circuit adopts single-ended structure, its output voltage swing is little, and the common-mode signal impact is large, is subject to the second harmonic impact.
(2) be not connected low-pass filter circuit between traditional sampling holding circuit, input voltage signal and sampling switch, input voltage signal is vulnerable to rear end drive circuit impact, produces transient peak.
(3) sampling switch often adopts MOS switch or cmos switch, and conducting resistance is large, and changes with the input voltage signal amplitude.The variation of conducting resistance has determined that the sampling hold circuit output voltage sets up the speed difference, produces the different voltages of setting up precision on sampling capacitance, has even-order harmonic in output voltage and disturbs, and reduces the SNDR(Spurious Free Dynamic Range of sampling hold circuit).
(4) the common folded common source and common grid operational amplifier of the normal employing of traditional sampling holding circuit, the amplifier DC current gain is less, realizes that precision is limited.
Summary of the invention
For above-mentioned prior art, the invention provides a kind of sampling hold circuit that is applied to the high-speed, high precision circuit, sampling hold circuit of the present invention is in the high-speed, high precision circuit, can realize the sampling to input voltage signal, simultaneously, can keep a period of time to sampled signal, facilitate back-end circuit that this signal is further processed.
In order to solve the problems of the technologies described above, a kind of sampling hold circuit that is applied to the high-speed, high precision circuit of the present invention, comprise a full differential operational amplifier, two sampling capacitance Cs, two sampling switch S1 and five selector switch S2, S3 and S4, the low-pass filter circuit that is consisted of by resistance R 1 and capacitor C 1; Described full differential operational amplifier is gain enhancement mode folded common source and common grid full differential operational amplifier; The structure that full differential operational amplifier positive-negative input end is connected is identical, signal input part is connected with sampling switch S1 and selector switch S3 by low-pass filter circuit, the other end of sampling switch S1 connects the bottom crown of sampling capacitance Cs, and selector switch S3 realizes being connected of sampling capacitance Cs bottom crown and full differential operational amplifier output terminal; The top crown of sampling capacitance Cs connects the positive-negative input end of selector switch S2 and selector switch S4 and full differential operational amplifier, described selector switch S4 realizes two connections between sampling capacitance Cs top crown, being connected between selector switch S3 consists of the input of full differential operational amplifier and exports;
described sampling switch S1 is the Bootstrap switch, comprises 5 capacitor C 2, C3, C4, C5 and C6,2 resistance R 2 and R3,8 NMOS pipes MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8,4 PMOS pipes MP1, MP2, MP3, MP4, wherein: NMOS pipe MN1 connects power vd D and capacitor C 2 top crowns, for capacitor C 2 provides the charging path, capacitor C 2 top crowns are connected with the grid of NMOS pipe MN2 and MN3, in order to control the open and close of NMOS pipe MN2 and MN3, the bottom crown of capacitor C 2 is connected with clock signal clk, NMOS pipe MN2 connects the top crown of power vd D and capacitor C 3, the top crown of while capacitor C 3 also is connected MN1 with NMOS with resistance R 2 grid is connected, the bottom crown of capacitor C 3 connects the drain electrode of NMOS pipe MN7, the grid of NMOS pipe MN7 connects clock control signal CLK, the source electrode of NMOS pipe MN7 is connected with ground GND, the grid of PMOS pipe MP2 connects clock control signal CLK_, the source electrode of PMOS pipe MP2 is connected missing of MP2 and is connected respectively power vd D and capacitor C 6 top crowns with PMOS, the charging path of capacitor C 6 is provided, the top crown of capacitor C 6 is connected with the grid of PMOS pipe MP3 simultaneously, in order to control the open and close of PMOS pipe MP3, capacitor C 6 bottom crowns connect clock control signal CLK, the leakage of NMOS pipe MN3, the top crown that source electrode connects respectively power vd D and capacitor C 4, the bottom crown of capacitor C 4 connect the drain electrode of NMOS pipe MN8 and the source electrode of NMOS pipe MN5, capacitor C 5 top crowns are connected the MN4 grid and are connected with NMOS with resistance R 3, leakage, the source electrode of NMOS pipe MN4 connect respectively the grid of NMOS pipe MN5, MN6, drain electrode and the clock control signal CLK_ of PMOS pipe MP3, substrate and the source electrode of PMOS pipe MP3 are connected together, and are connected to the top crown of capacitor C 4, the source electrode of the drain electrode of NMOS pipe MN5 and NMOS pipe MN6 connects together, and meets input voltage signal VIN, and wherein NMOS pipe MN6 as switching tube, is connected with sampling capacitance Cs bottom crown,
Described sampling capacitance Cs samples to input voltage signal VIN, and sampling capacitance Cs top crown electric charge is Q
Bottom=-CsVIN; After sampling finished, at first selector switch S2 and selector switch S4 low level closed, and selector switch S1 postpones to close after blink, and selector switch S3 opens simultaneously, and circuit enters Holdover mode; Sampling capacitance Cs bottom crown and full differential operational amplifier output short circuit, sampling capacitance Cs top crown electric charge is Q
Bottom=-CsVIN; At Holdover mode, Q
Bottom=-CsVOUT, output voltage signal VOUT equates with input voltage signal VIN.
Compared with prior art, the invention has the beneficial effects as follows:
The whole fully differential structure that adopts of sampling hold circuit of the present invention as shown in Figure 2, has larger output voltage swing, and can effectively suppress the common-mode signal of circuit, reduces the circuit even-order harmonic distortion.The sampling hold circuit front end, resistance R 1 in Fig. 2 and capacitor C 1 consist of passive network, input at sampling hold circuit forms a low pass filter, to filtering with the unmatched high-frequency signal of input voltage signal, can effectively reduce the transient peak by output drive source impact generation, simultaneously, little electric capacity in parallel can provide dynamic charge, effectively raises the precision of sampling hold circuit.Sampling switch in circuit, the S1 in Fig. 2 adopts the Bootstrap switch, and structure effectively raises the gate source voltage of switching tube as shown in Figure 3, makes it reach supply voltage VDD, obviously reduces conducting resistance, has improved sample rate and precision.In addition, the switching tube gate source voltage remains unchanged, and conducting resistance does not change with input voltage signal, has effectively reduced the interference of even-order harmonic to signal.The full differential operational amplifier that adopts in circuit is gain enhancement mode folded common source and common grid operational amplifier, shown in Figure 5, realized the stack of dual-stage amplifier gain, obtained higher DC current gain, satisfy circuit to high-precision requirement, design simultaneously corresponding common mode feedback circuit, shown in Figure 8, guaranteed the stability of operational amplifier work.Sampling hold circuit of the present invention can be realized 50MSPS, the minimum voltage 0.12mv that differentiates, and the example that is applied as with in production line analog-digital converter can realize the 50M sample rate, full accuracy can reach 14.
Description of drawings
Fig. 1 is traditional sampling hold circuit schematic diagram;
Fig. 2 is sampling hold circuit schematic diagram of the present invention;
Fig. 3 is Bootstrap construction of switch schematic diagram in the present invention;
Fig. 4 is that in the present invention, the Bootstrap switch is controlled the clock generation circuit schematic diagram;
Fig. 5 is gain enhancement mode folded common source and common grid full differential operational amplifier structural representation in the present invention;
Fig. 6 is gain enhancement mode folded common source and common grid full differential operational amplifier A 1 partial circuit figure in the present invention;
Fig. 7 is gain enhancement mode folded common source and common grid full differential operational amplifier A 2 partial circuit figure in the present invention;
Fig. 8 is switched-capacitor CMFB circuit diagram in the present invention;
Fig. 9 is the clock timing diagram that in the present invention, sampling capacitance is sampled to input voltage signal.
Embodiment
Below in conjunction with embodiment, the present invention is described in further detail.
As shown in Figure 2, a kind of sampling hold circuit that is applied to the high-speed, high precision circuit of the present invention, it is characterized in that, comprise a full differential operational amplifier, two sampling capacitance Cs, two sampling switch S1 and two S2 of five selector switches, two S3, S4 and two low-pass filter circuits that consisted of by resistance R 1 and capacitor C 1; Described full differential operational amplifier is gain enhancement mode folded common source and common grid full differential operational amplifier; The structure that sampling hold circuit full differential operational amplifier positive-negative input end of the present invention is connected is identical, take full differential operational amplifier one end case input end connecting structure as example, signal input part is connected with sampling switch S1 and selector switch S3 by low-pass filter circuit, the other end of sampling switch S1 connects the bottom crown of sampling capacitance Cs, and selector switch S3 realizes being connected of sampling capacitance Cs bottom crown and full differential operational amplifier output terminal; The top crown of sampling capacitance Cs connects the input of selector switch S2 and selector switch S4 and full differential operational amplifier, selector switch S4 realizes two connections between sampling capacitance Cs top crown, and selector switch S3 consists of being connected between full differential operational amplifier input and output.
As shown in Figure 2, described sampling capacitance Cs samples to input voltage signal VIN, and sampling capacitance Cs top crown electric charge is Q
Bottom=-CsVIN; After sampling finished, at first selector switch S2 and selector switch S4 closed, and selector switch S1 postpones to close after blink, and selector switch S3 opens simultaneously, and circuit enters Holdover mode; Sampling capacitance Cs bottom crown is connected with the full differential operational amplifier output terminal, and sampling capacitance Cs top crown electric charge is Q
Bottom=-CsVIN, at Holdover mode, owing to there is no resistive path between sampling capacitance Cs top crown and ground, on sampling capacitance Cs top crown, electric charge is constant.Therefore, Q
Bottom=-CsVOUT=-CsVIN, that is, VOUT=VIN, output voltage signal equate with input voltage signal, complete sampling and keep function.
shown in Figure 3, described sampling switch S1 is the Bootstrap switch, comprises 5 capacitor C 2, C3, C4, C5 and C6,2 resistance R 2 and R3,8 NMOS pipes MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8,4 PMOS pipes MP1, MP2, MP3, MP4, wherein: NMOS pipe MN1 connects power vd D and capacitor C 2 top crowns, for capacitor C 2 provides the charging path, capacitor C 2 top crowns are connected with the grid of NMOS pipe MN2 and MN3, in order to control the open and close of NMOS pipe MN2 and MN3, the bottom crown of capacitor C 2 is connected with clock signal clk, NMOS pipe MN2 connects the top crown of power vd D and capacitor C 3, the top crown of while capacitor C 3 also is connected MN1 with NMOS with resistance R 2 grid is connected, the bottom crown of capacitor C 3 connects the drain electrode of NMOS pipe MN7, the grid of NMOS pipe MN7 connects clock control signal CLK, the source electrode of NMOS pipe MN7 is connected with ground GND, the grid of PMOS pipe MP2 connects clock control signal CLK_, the source electrode of PMOS pipe MP2 is connected missing of MP2 and is connected respectively power vd D and capacitor C 6 top crowns with PMOS, the charging path of capacitor C 6 is provided, the top crown of capacitor C 6 is connected with the grid of PMOS pipe MP3 simultaneously, in order to control the open and close of PMOS pipe MP3, capacitor C 6 bottom crowns connect clock control signal CLK, the leakage of NMOS pipe MN3, the top crown that source electrode connects respectively power vd D and capacitor C 4, the bottom crown of capacitor C 4 connect the drain electrode of NMOS pipe MN8 and the source electrode of NMOS pipe MN5, capacitor C 5 top crowns are connected the MN4 grid and are connected with NMOS with resistance R 3, leakage, the source electrode of NMOS pipe MN4 connect respectively the grid of NMOS pipe MN5, MN6, drain electrode and the clock control signal CLK_ of PMOS pipe MP3, substrate and the source electrode of PMOS pipe MP3 are connected together, and are connected to the top crown of capacitor C 4, the source electrode of the drain electrode of NMOS pipe MN5 and NMOS pipe MN6 connects together, and meets input voltage signal VIN, and wherein NMOS pipe MN6 as switching tube, is connected with sampling capacitance Cs bottom crown.
As shown in Figure 3, under the clock signal controlling, when supposing beginning, clock signal clk is high level, and CLK_ is low level, and capacitor C 2 bottom crowns connect the CLK signal, capacitor C 2 top crown voltages can instantaneous being lifted be 2VDD, NMOS pipe MN2 and the conducting of MN3 pipe charge for capacitor C 3, C4 top crown, and capacitor C 4 top crown voltages are VDD.PMOS pipe MP2 conducting, capacitor C 6 Shang Xia polar plate voltage be VDD, PMOS pipe MP3 ends.Capacitor C 5 top crown voltages are reduced to VDD gradually from 2VDD, during this period, NMOS pipe MN4 conducting always, the CLK_ signal is managed MN4 by NMOS and is transferred to NMOS pipe MN5 and MN6 grid, NMOS pipe MN5 and MN6 cut-off, the VIN input voltage signal can not charge to sampling capacitance Cs, and this moment, circuit was in Holdover mode.
when the CLK signal changes low level into, CLK_ becomes high level, capacitor C 2 top crown voltages are VDD, NMOS pipe MN2 and MN3 conducting, PMOS pipe MP1 conducting, capacitor C 3 bottom crowns are charged to VDD, the capacitor C 3 temporary transient liftings of top crown voltage are 2VDD, PMOS pipe MP2 cut-off, on capacitor C 6, bottom crown is VSS, PMOS pipe MP3 conducting, NMOS pipe MN8 cut-off, capacitor C 4 top crown voltages are still temporarily VDD, NMOS pipe MN4 conducting, the CLK_ high level signal manages by NMOS the grid that MN4 transfers to NMOS pipe MN5 and MN6, NMOS pipe MN5 and MN6 conducting, input voltage signal VIN manages MN5 by NMOS and transfers to capacitor C 4 bottom crowns, capacitor C 4 top crowns become VDD+VIN, top crown voltage is by the PMOS pipe MP3 of conducting, pass NMOS pipe MN5 and MN6 grid back, NMOS pipe MN6 grid voltage becomes VDD+VIN, the gate source voltage Vgs=VDD+VIN-VIN=VDD of NMOS pipe MN6.Formula by conducting resistance
(wherein Ron is conducting resistance, and unit is Ω, and μ is the metal-oxide-semiconductor channel mobility, and unit is cm
2/ V/s, C
oxBe the gate oxide electric capacity of unit are, unit is fF/um
2, Vgs is gate source voltage, and unit is V, and Vth is threshold voltage, unit is V).
Can draw, NMOS pipe conducting resistance Ron remains unchanged, and due to Vgs=VDD, NMOS pipe conducting resistance Ron keeps minimum value, satisfies Circuits System to the requirement of sampling switch.The open and close of capacitor C 5 top crown voltage control NMOS pipe MN4, the source electrode of NMOS pipe MN4 connects clock signal, can guarantee in the maintenance stage, and NMOS pipe MN5 and MN6 keep closed condition.Resistance R 2 and R3 charging circuit also can effectively prevent the higher-order of oscillation, protection metal-oxide-semiconductor grid.NMOS pipe MN6 conducting resistance in the Bootstrap switch does not change with the amplitude of input voltage signal, and remain minimum value, in the input voltage signal change procedure, the conducting resistance of NMOS pipe can be controlled at about 10 Ω, the conducting resistance variation is controlled in 2 Ω.Because bulk effect can affect threshold voltage, the non-ideal factors such as parasitic capacitance existence can cause the conducting resistance of switching tube with input voltage signal, small variation to occur, and still, the performance of NMOS pipe can satisfy the requirement of high-speed, high precision sampling hold circuit.
Sampling hold circuit of the present invention, sampling switch S1 is higher to the requirement of clock, the clock generation circuit that in the present invention, the Bootstrap switch adopts as shown in Figure 4, master clock CK (being the θ 1 in Fig. 9) is when signal produces inversion signal by inverter, time delay due to inverter, may cause CK_ signal and CK_ signal to arrive the asynchronism(-nization) of control switch, impact.Adopt Fig. 4 circuit, the CK signal at the CLK_ that produces through inverter and the CLK signal that produces by two inverters, can guarantee that CLK and CLK_ are basically identical time of delay by a cmos transmission gate like this, can effectively avoid sampled value to get uncertain.
sampling hold circuit of the present invention, described full differential operational amplifier is gain enhancement mode folded common source and common grid full differential operational amplifier, as shown in Figure 5, wherein the A1 part-structure in this operational amplifier and A2 part-structure provide in Fig. 6 and Fig. 7 respectively, and wherein A1 part-structure and A2 part-structure are respectively as the folded common source and common grid amplifier of input pipe and the folded common source and common grid amplifier take PMOS as input pipe with NMOS, the output of A1 part-structure is connected to the grid of the pipe MP9 of PMOS in operational amplifier and MP10, the output of A2 part-structure is connected to the grid of the pipe MN9 of NMOS in operational amplifier and MN10, in Fig. 5, IN+ and IN-are inputs, VCMFB is common-mode feedback voltage, VOUT+ and VOUT-are outputs, VBP, VBPA1, VBPA2, VCPA1, VCPA2 is the bias voltage of PMOS pipe, VBNA1, VBNA2, VCNA1, VCNA2 is NMOS pipe bias voltage, the full differential operational amplifier of said structure can have been eliminated the gain error of even-order effectively, than single-ended amplifier, error is less.This full differential operational amplifier adopts the PMOS pipe as input pipe, and noise that can step-down amplifier guarantees that noise is minimum for the impact of signal conversion accuracy.
Full differential operational amplifier in the present invention needs common mode feedback circuit, and to guarantee the stable of amplifier, what common mode feedback circuit adopted is the switched-capacitor CMFB circuit, as shown in Figure 8.In figure, VCMFB is common-mode feedback output, and VOUT+ and VOUT-are the amplifier positive-negative output ends, and VBIAS is bias voltage, and VCMREF is output common mode level standard value, and CLK1 and CLK2 are the control switch clock signals, and wherein high level is opened, and low level disconnects.
When CLK1 is high level, when CLK2 is low level, have: Q=2C8* (VBIAS-VCMREF); When CLK1 is low level, when CLK2 is high level, have: Q=2C7*(VCMFB-VCM), (wherein VCM=(VOUT++VOUT-)/2); Therefore finally obtain: VCMFB=VCM+(C8/C7) * (VBIAS-VCMREF).When the VCM increase, VCMFB also follows increase, because VCMFB as bias voltage, regulates the grid voltage of NMOS pipe MN11 and MN12, causes VCM to descend again, realizes the effect of stabilizing amplifier output common mode level.
Fig. 9 is sampling hold circuit work clock sequential of the present invention, and wherein Ф 1 is the sequential of controlling sampling switch S1, and Ф 2, Ф 3, Ф 4 are respectively the sequential of controlling corresponding selector switch S2, S3, S4, and CLK1 and CLK2 are the sequential of controlling common mode feedback circuit.
Under Fig. 9 sequencing control, the course of work of sampling hold circuit of the present invention is as follows: switching sequence Ф 1, Ф 2, Ф 4 high level, switching sequence Ф 3 is low level, sampling switch S1 conducting, circuit is in sampling configuration, Cs samples to input voltage signal by sampling capacitance, and sampling capacitance top crown electric charge is Q
Bottom=-CsVIN.After sampling finished, switching sequence Ф 1, Ф 2, Ф 4 became low level, and switching sequence Ф 3 becomes high level, at first selector switch S2 and selector switch S4 close, sampling switch S1 postpones to close after blink, and selector switch S3 opens simultaneously, and circuit enters Holdover mode.Sampling capacitance Cs bottom crown is connected with the output of full differential operational amplifier, and sampling capacitance Cs top crown electric charge is Q
Bottom=-CsVIN, at Holdover mode, owing to there is no resistive path between sampling capacitance Cs top crown and ground, on sampling capacitance Cs top crown, electric charge is constant.Therefore, Q
Bottom=-CsVOUT=-CsVIN, that is, VOUT=VIN, output voltage signal equate with input voltage signal, so far complete sampling and keep function.
Although top invention has been described in conjunction with figure; but the present invention is not limited to above-mentioned embodiment; above-mentioned embodiment is only schematic; rather than restrictive; those of ordinary skill in the art is under enlightenment of the present invention; in the situation that do not break away from aim of the present invention, can also make a lot of distortion, within these all belong to protection of the present invention.
Claims (1)
1. sampling hold circuit that is applied to the high-speed, high precision circuit, it is characterized in that, comprise a full differential operational amplifier, two sampling capacitance Cs, two sampling switch S1 and five selector switch S2, S3, S4, the low-pass filter circuit that is consisted of by resistance R 1 and capacitor C 1; Described full differential operational amplifier is gain enhancement mode folded common source and common grid full differential operational amplifier; The structure that full differential operational amplifier positive-negative input end is connected is identical, signal input part is connected with sampling switch S1 and selector switch S3 by low-pass filter circuit, the other end of sampling switch S1 connects the bottom crown of sampling capacitance Cs, and selector switch S3 realizes being connected of sampling capacitance Cs bottom crown and full differential operational amplifier output terminal; The top crown of sampling capacitance Cs connects the input of selector switch S2 and selector switch S4 and full differential operational amplifier, selector switch S4 realizes two connections between sampling capacitance Cs top crown, and selector switch S3 connects full differential operational amplifier input and output;
described sampling switch S1 is the Bootstrap switch, comprises 5 capacitor C 2, C3, C4, C5 and C6,2 resistance R 2 and R3,8 NMOS pipes MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8,4 PMOS pipes MP1, MP2, MP3, MP4, wherein: NMOS pipe MN1 connects power vd D and capacitor C 2 top crowns, for capacitor C 2 provides the charging path, capacitor C 2 top crowns are connected with the grid of NMOS pipe MN2 and MN3, in order to control the open and close of NMOS pipe MN2 and MN3, the bottom crown of capacitor C 2 is connected with clock signal clk, NMOS pipe MN2 connects the top crown of power vd D and capacitor C 3, the top crown of while capacitor C 3 also is connected MN1 with NMOS with resistance R 2 grid is connected, the bottom crown of capacitor C 3 connects the drain electrode of NMOS pipe MN7, the grid of NMOS pipe MN7 connects clock control signal CLK, the source electrode of NMOS pipe MN7 is connected with ground GND, the grid of PMOS pipe MP2 connects clock control signal CLK_, the source electrode of PMOS pipe MP2 is connected missing of MP2 and is connected respectively power vd D and capacitor C 6 top crowns with PMOS, the charging path of capacitor C 6 is provided, the top crown of capacitor C 6 is connected with the grid of PMOS pipe MP3 simultaneously, in order to control the open and close of PMOS pipe MP3, capacitor C 6 bottom crowns connect clock control signal CLK, the leakage of NMOS pipe MN3, the top crown that source electrode connects respectively power vd D and capacitor C 4, the bottom crown of capacitor C 4 connect the drain electrode of NMOS pipe MN8 and the source electrode of NMOS pipe MN5, capacitor C 5 top crowns are connected the MN4 grid and are connected with NMOS with resistance R 3, leakage, the source electrode of NMOS pipe MN4 connect respectively the grid of NMOS pipe MN5, MN6, drain electrode and the clock control signal CLK_ of PMOS pipe MP3, substrate and the source electrode of PMOS pipe MP3 are connected together, and are connected to the top crown of capacitor C 4, the source electrode of the drain electrode of NMOS pipe MN5 and NMOS pipe MN6 connects together, and meets input voltage signal VIN, and wherein NMOS pipe MN6 as switching tube, is connected with sampling capacitance Cs bottom crown,
Described sampling capacitance Cs samples to input voltage signal VIN, and sampling capacitance Cs top crown electric charge is Q
Bottom=-CsVIN; After sampling finished, at first selector switch S2 and selector switch S4 closed, and selector switch S1 postpones to close after blink, and selector switch S3 opens simultaneously, and circuit enters Holdover mode; Sampling capacitance Cs bottom crown is connected with the full differential operational amplifier output terminal, and sampling capacitance Cs top crown electric charge is Q
Bottom=-CsVIN; At Holdover mode, Q
Bottom=-CsVOUT, output voltage signal VOUT equates with input voltage signal VIN.
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