CN108777579A - Boot-strapped switch - Google Patents

Boot-strapped switch Download PDF

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Publication number
CN108777579A
CN108777579A CN201811042575.4A CN201811042575A CN108777579A CN 108777579 A CN108777579 A CN 108777579A CN 201811042575 A CN201811042575 A CN 201811042575A CN 108777579 A CN108777579 A CN 108777579A
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China
Prior art keywords
nmos tube
tube
switch
grid
pmos
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Granted
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CN201811042575.4A
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CN108777579B (en
Inventor
宋树祥
庞中秋
张泽伟
岑明灿
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Guangxi Normal University
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Guangxi Normal University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H03K17/6874—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor in a symmetrical configuration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0614—Continuously compensating for, or preventing, undesired influence of physical parameters of harmonic distortion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The invention discloses boot-strapped switch, it is related to Analogical Circuit Technique field, including the first capacitance and multiple metal-oxide-semiconductors, metal-oxide-semiconductor includes the first PMOS tube, the first NMOS tube, the second NMOS tube, the second PMOS tube, third PMOS tube, third NMOS tube, the 4th NMOS tube, the 5th NMOS tube, the 6th NMOS tube, bootstrapped switch and substrate switch, and substrate switch is connect with bootstrapped switch.The present invention on bootstrapped switch by accessing substrate switch, that is the 7th NMOS tube and the 8th NMOS tube, so that in sampling, the grid potential of bootstrapped switch is consistent with substrate electric potential, so bulk effect in metal-oxide-semiconductor second-order effect can be reduced, harmonic distortion is reduced, while ensure that the linearity of sampling switch SW, the precision for improving sampling switch circuit substantially reduces influence of the switched linear to ADC precision.

Description

Boot-strapped switch
Technical field
The present invention relates to Analogical Circuit Technique field more particularly to boot-strapped switch.
Background technology
With the rapid growth of progress and the communication and multimedia market of integrated circuit processing technique, Digital Signal Processing Technology is also grown rapidly and is widely used in every field.Digital signal have strong antijamming capability, be easily integrated, Small power consumption, comprehensive advantage at low cost, therefore more and more analog signal processings are gradually replaced by digital signal technique.So And the signals such as light, heat, sound, electricity, magnetic of nature are all analog quantitys, in order to enable these analog signals by digital display circuit Reason, needs that continuous analog signal is converted to discrete digital signal in time by these, and analog-digital converter (Analog To Digital Converter, ADC) it is exactly the module for realizing the function.As the key interface of analogue and digital circuit, ADC is most important to the performance of entire mixed-signal system.By controlling the closure of switch and turning off to realize in SAR ADC Samplings and holding of the ADC to input signal, switch can introduce gain error there are non-ideal factor, DC maladjustment and non-linear Error, influences the accuracy and speed of sample circuit, and the precision that the decline of sampling circuit samples precision will have a direct impact on, so It in SAR ADC design processes, to select to influence sample circuit precision smaller sampling switch, meet SAR ADC systems and set Meter requires.
Traditional boot-strapped switch circuit structure as shown in Figure 1, be made of sampling switch SW and Bootstrap circuit, Middle boot-strapped switch includes capacitance C1 and metal-oxide-semiconductor M1~M9, its working principle is that：
(1) when circuit is in sample phase, CLK is high level, M2 conductings, M5 grounded-grids, so that M5 conductings, are raised The grid voltage of M6, SW, M3 and M4 cut-offs, M9 conductings, sampling switch SW are closed, and since the total electrical charge stored in C1 is constant, C1 is connected to The grid grade of the grid source electrode of SW, SW is raised to VDD+Vin, and the gate-source voltage of SW is VDD.
(2) when circuit is in the holding stage, CLK is low level, and M1, M3 and M4 are connected, and M5 grids meet VDD, and M5 ends, M9 ends, and sampling switch SW is disconnected, and charges to VDD to capacitance C1 by M3 and M4, the electricity of C1*VDD is stored in capacitance C1. Capacitance C1 and sampling switch SW separation, the drain electrode of SW and source electrode are grounded by M3, M7 and M8 respectively, to discharge.
The conducting resistance of sampling switch is
Wherein, μnFor carrier mobility, CoxFor sampling switch pipe unit area gate capacitance, W/L is the wide length of sampling switch Than VGSFor sampling switch gate source voltage, VTH0For switching tube on state threshold voltage, VSBPotential difference is served as a contrast for switching tube source, γ is body Effect coefficient.
Using boot-strapped switch circuit, switch gate source voltage V is improvedGSNon-linear distortion caused by variation, but its Have ignored the V caused by bulk effectTH0The linear problem that brings of variation.
Invention content
In view of this, the object of the present invention is to provide boot-strapped switch, substrate is connected by the grid in sampling switch Switch, to reduce bulk effect.
The present invention solves above-mentioned technical problem by following technological means：Boot-strapped switch, including the first capacitance and more A metal-oxide-semiconductor, the metal-oxide-semiconductor include the first PMOS tube, the first NMOS tube, the second NMOS tube, the second PMOS tube, third PMOS tube, Third NMOS tube, the 4th NMOS tube, the 5th NMOS tube, the 6th NMOS tube, bootstrapped switch and substrate switch, the first PMOS It manages, the source electrode of the second PMOS tube is all connected with operating voltage VDD, the leakage of drain electrode the first NMOS tube of connection of first PMOS tube The grid of pole, first PMOS tube and the first NMOS tube is all connected with the first clock signal clk, the source electrode of first NMOS tube Connect the drain electrode of the second NMOS tube, the grid connection second clock signal CLK- of second NMOS tube, the second clock letter Number CLK- is the inversion signal of the first clock signal clk, the source electrode ground connection of second NMOS tube；
The drain electrode of second PMOS tube connects the top crown of the first capacitance, the bottom crown and the first NMOS of first capacitance The source electrode of pipe connects, and the grid of second PMOS tube connects the drain electrode of the 4th NMOS tube, and the grid of the 4th NMOS tube connects Operating voltage VDD is met, the source electrode of the 4th NMOS tube connects the drain electrode of the 5th NMOS tube, and the source electrode of the 5th NMOS tube connects The grid on ground, the 5th NMOS tube meets second clock signal CLK-；
The drain electrode of second PMOS tube is also connect with the source electrode of third PMOS tube, the drain electrode connection of the third PMOS tube The drain electrode of 4th NMOS tube, the grid of the third PMOS tube connect the drain electrode of the first PMOS tube, the grid of the third PMOS tube Pole connects the drain electrode of third NMOS tube；
The source electrode of the third NMOS tube is connect with the source electrode of the first NMOS tube, the grid and the 6th of the third NMOS tube The grid of NMOS tube connects；
The grid of 6th NMOS tube is also connected with the drain electrode of the 4th NMOS tube, the source electrode connection of the 6th NMOS tube the The source electrode of three NMOS tubes, the source electrode of the drain electrode connection bootstrapped switch of the 6th NMOS tube；
The source electrode of the bootstrapped switch connects input voltage vin, and the drain electrode connection power supply of the bootstrapped switch exports VOUT, The grid of the bootstrapped switch connects the grid of the 6th NMOS tube；
Substrate switch is connected on the grid of the bootstrapped switch, the substrate switch includes the 7th NMOS tube and the 8th NMOS tube, the grid of the bootstrapped switch connect the grid of the 8th NMOS tube, and the substrate of the bootstrapped switch connects the 8th NMOS The source electrode of pipe, the source electrode of the drain electrode connection bootstrapped switch of the 8th NMOS tube, the source electrode connection the 7th of the 8th NMOS tube The drain electrode of NMOS tube；
The grid of 7th NMOS tube connects second clock signal CLK-, the source electrode ground connection of the 7th NMOS tube.
The course of work of the present invention is as follows：
1) when first clock signal clk is high level, the CMOS boot-strapped switch circuit is in sampling rank Section, the first NMOS tube conducting, the third PMOS tube grounded-grid are raised so that the third PMOS tube is connected The third NMOS tube, the 6th NMOS tube, the grid voltage of the 8th NMOS tube and bootstrapped switch, second NMOS tube and the 2nd PMOS Pipe ends, and the 6th NMOS tube conducting, the sampling switch is closed, and the 8th NMOS tube conducting, first capacitance connects It is connected to the grid source electrode of bootstrapped switch, since the total electrical charge stored in first capacitance is constant, the grid grade electricity of the bootstrapped switch Pressure is raised to VDD+Vin, and the gate-source voltage of the bootstrapped switch is VDD.
2) when first clock signal clk is low level, the CMOS boot-strapped switch circuit, which is in, keeps rank Section, first PMOS tube, the second NMOS tube and the conducting of the second PMOS tube, the third PMOS tube grid meet operating voltage VDD, Third PMOS tube cut-off, the 6th NMOS tube cut-off, the sampling switch disconnect, and pass through second NMOS tube and the Two PMOS tube are to the first capacitor charging to operating voltage VDD, and the capacitance of first capacitance is F, then in first capacitance The electricity for storing F*VDD, since the third PMOS tube is ended, first capacitance and sampling switch separation, the sampling The source electrode of switch is grounded by second NMOS tube, grid is grounded by the 4th NMOS tube and the 5th NMOS tube, to discharge.
Beneficial effects of the present invention：The present invention on bootstrapped switch by accessing substrate switch, i.e. the 7th NMOS tube and the Eight NMOS tubes so that in sampling, grid potential and the substrate electric potential of bootstrapped switch are consistent, so can reduce metal-oxide-semiconductor Bulk effect in second-order effect reduces harmonic distortion, while ensure that the linearity of sampling switch SW, improves sampling switch electricity The precision on road substantially reduces influence of the switched linear to ADC precision.
Description of the drawings
Fig. 1 is the schematic diagram of traditional boot-strapped switch circuit；
Fig. 2 is boot-strapped switch figure of the embodiment of the present invention；
Fig. 3 is clock signal, input/output signal simulation waveform in boot-strapped switch of the embodiment of the present invention.
Specific implementation mode
Below with reference to the drawings and specific embodiments, the present invention is described in detail：
As Figure 2-3, boot-strapped switch, including the first capacitance C1 and multiple metal-oxide-semiconductors, metal-oxide-semiconductor include the first PMOS Pipe M1, the first NMOS tube M2, the second NMOS tube M3, the second PMOS tube M4, third PMOS tube M5, third NMOS tube M6, the 4th NMOS tube M7, the 5th NMOS tube M8, the 6th NMOS tube M9, bootstrapped switch SW and substrate switch, the first PMOS tube M1, the 2nd PMOS The source electrode of pipe M4 is all connected with the drain electrode of the first NMOS tube M2 of drain electrode connection of operating voltage VDD, the first PMOS tube M1, the first PMOS The grid of pipe M1 and the first NMOS tube M2 are all connected with the first clock signal clk, and the source electrode of the first NMOS tube M2 connects the 2nd NMOS The grid of the drain electrode of pipe M3, the second NMOS tube M3 connects second clock signal CLK-, and second clock signal CLK- is the first clock The inversion signal of signal CLK, the source electrode ground connection of the second NMOS tube M3；
The drain electrode of second PMOS tube M4 connects the top crown of the first capacitance C1, the bottom crown and the first NMOS tube of the first capacitance C1 The source electrode of M2 connects, and the grid of the second PMOS tube M4 connects the drain electrode of the 4th NMOS tube M7, the grid connection of the 4th NMOS tube M7 The source electrode of operating voltage VDD, the 4th NMOS tube M7 connect the drain electrode of the 5th NMOS tube M8, and the source electrode of the 5th NMOS tube M8 is grounded, The grid of 5th NMOS tube M8 meets second clock signal CLK-；
The drain electrode of second PMOS tube M4 is also connect with the source electrode of third PMOS tube M5, the drain electrode of third PMOS tube M5 connection the The drain electrode of four NMOS tube M7, the grid of third PMOS tube M5 connect the drain electrode of the first PMOS tube M1, the grid of third PMOS tube M5 Connect the drain electrode of third NMOS tube M6；
The source electrode of third NMOS tube M6 is connect with the source electrode of the first NMOS tube M2, the grid and the 6th of third NMOS tube M6 The grid of NMOS tube M9 connects；
The grid of 6th NMOS tube M9 is also connected with the drain electrode of the 4th NMOS tube M7, and the source electrode of the 6th NMOS tube M9 connects third The source electrode of NMOS tube M6, the source electrode of the drain electrode connection bootstrapped switch SW of the 6th NMOS tube M9；
The source electrode of bootstrapped switch SW connects input voltage vin, and the drain electrode connection power supply of bootstrapped switch SW exports VOUT, bootstrapping The grid of switch SW connects the grid of the 6th NMOS tube M9；
Substrate switch is connected on the grid of bootstrapped switch SW, substrate switch includes the 7th NMOS tube M10 and the 8th NMOS The grid of pipe M11, bootstrapped switch SW connect the grid of the 8th NMOS tube M11, and the substrate of bootstrapped switch SW connects the 8th NMOS tube The source electrode of M11, the source electrode of the drain electrode connection bootstrapped switch SW of the 8th NMOS tube M11, the source electrode connection the 7th of the 8th NMOS tube M11 The drain electrode of NMOS tube M10；
The source electrode ground connection of grid connection second clock the signal CLK-, the 7th NMOS tube M10 of 7th NMOS tube M10.
The course of work of the present invention is as follows：
1) when the first clock signal clk is high level, CMOS boot-strapped switch circuits are in sample phase, and first NMOS tube M2 conducting, third PMOS tube M5 grounded-grids so that the M5 conductings of third PMOS tube, raise third NMOS tube M6, The grid voltage of 6th NMOS tube M9, the 8th NMOS tube M11 and bootstrapped switch SW, the second NMOS tube M3 and the second PMOS tube M4 cut-offs, 6th NMOS tube M9 conductings, sampling switch SW are closed, and the 8th NMOS tube M11 conductings, the first capacitance C1 is connected to bootstrapped switch SW Grid source electrode, since the total electrical charge stored in the first capacitance C1 is constant, the grid step voltage of bootstrapped switch SW is raised to VDD+Vin, The gate-source voltage of bootstrapped switch SW is VDD.
2) when the first clock signal clk is low level, CMOS boot-strapped switch circuits are in the holding stage, and first PMOS tube M1, the second NMOS tube M3 and the second PMOS tube M4 conductings, third PMOS tube M5 grids connect operating voltage VDD, third PMOS tube M5 cut-offs, the 6th NMOS tube M9 cut-offs, sampling switch SW are disconnected, are given by the second NMOS tube M3 and the second PMOS tube M4 The capacitance that first capacitance C1 charges to operating voltage VDD, the first capacitance C1 is F, then stores F*VDD's in the first capacitance C1 Electricity, since third PMOS tube M5 ends, the first capacitance C1 and sampling switch SW separation, the source electrode of sampling switch SW pass through second NMOS tube M3 ground connection, grid are by the 4th NMOS tube M7 and the 5th NMOS tube M8 ground connection, to discharge.
The present invention on bootstrapped switch by accessing substrate switch, i.e. the 7th NMOS tube and the 8th NMOS tube so that is adopting When sample, grid potential and the substrate electric potential of bootstrapped switch are consistent, so bulk effect in metal-oxide-semiconductor second-order effect can be reduced, Harmonic distortion is reduced, while ensure that the linearity of sampling switch SW, the precision of sampling switch circuit is improved, greatly reduces Influence of the switched linear to ADC precision.
The above examples are only used to illustrate the technical scheme of the present invention and are not limiting, although with reference to preferred embodiment to this hair It is bright to be described in detail, it will be understood by those of ordinary skill in the art that, it can modify to technical scheme of the present invention Or equivalent replacement should all cover the claim in the present invention without departing from the objective and range of technical solution of the present invention In range.Technology that the present invention is not described in detail, shape, construction part are known technology.

Claims (3)

1. boot-strapped switch, which is characterized in that including the first capacitance (C1) and multiple metal-oxide-semiconductors, the metal-oxide-semiconductor includes first PMOS tube (M1), the first NMOS tube (M2), the second NMOS tube (M3), the second PMOS tube (M4), third PMOS tube (M5), third NMOS tube (M6), the 4th NMOS tube (M7), the 5th NMOS tube (M8), the 6th NMOS tube (M9), bootstrapped switch (SW) and substrate are opened Close, first PMOS tube (M1), the second PMOS tube (M4) source electrode be all connected with operating voltage VDD, first PMOS tube (M1) drain electrode connects the drain electrode of the first NMOS tube (M2), and first PMOS tube (M1) and the grid of the first NMOS tube (M2) are equal Connecting the first clock signal clk, the source electrode of first NMOS tube (M2) connects the drain electrode of the second NMOS tube (M3), and described second The grid of NMOS tube (M3) connects second clock signal CLK-, and the second clock signal CLK- is the first clock signal clk Inversion signal, the source electrode ground connection of second NMOS tube (M3)；
The drain electrode of second PMOS tube (M4) connects the top crown of the first capacitance (C1), the bottom crown of first capacitance (C1) with The source electrode of first NMOS tube (M2) connects, and the grid of second PMOS tube (M4) connects the drain electrode of the 4th NMOS tube (M7), institute The grid connection operating voltage VDD of the 4th NMOS tube (M7) is stated, the source electrode of the 4th NMOS tube (M7) connects the 5th NMOS tube (M8) grid of drain electrode, the source electrode ground connection of the 5th NMOS tube (M8), the 5th NMOS tube (M8) connects second clock letter Number CLK-；
The drain electrode of second PMOS tube (M4) is also connect with the source electrode of third PMOS tube (M5), the third PMOS tube (M5) The drain electrode of drain electrode the 4th NMOS tube (M7) of connection, the grid of the third PMOS tube (M5) connect the leakage of the first PMOS tube (M1) Pole, the drain electrode of the grid connection third NMOS tube (M6) of the third PMOS tube (M5)；
The source electrode of the third NMOS tube (M6) is connect with the source electrode of the first NMOS tube (M2), the grid of the third NMOS tube (M6) Pole is connect with the grid of the 6th NMOS tube (M9)；
The grid of 6th NMOS tube (M9) is also connected with the drain electrode of the 4th NMOS tube (M7), the source of the 6th NMOS tube (M9) Pole connects the source electrode of third NMOS tube (M6), the source electrode of the drain electrode connection bootstrapped switch (SW) of the 6th NMOS tube (M9)；
The source electrode of the bootstrapped switch (SW) connects input voltage vin, the drain electrode connection power supply output of the bootstrapped switch (SW) VOUT, the grid of the bootstrapped switch (SW) connect the grid of the 6th NMOS tube (M9)；
Be connected with substrate switch on the grid of the bootstrapped switch (SW), substrate switch include the 7th NMOS tube (M10) and 8th NMOS tube (M11), the grid of the bootstrapped switch (SW) connect the grid of the 8th NMOS tube (M11), the bootstrapped switch (SW) substrate connects the source electrode of the 8th NMOS tube (M11), the drain electrode connection bootstrapped switch (SW) of the 8th NMOS tube (M11) Source electrode, the source electrode of the 8th NMOS tube (M11) connects the drain electrode of the 7th NMOS tube (M10)；
The grid of 7th NMOS tube (M10) connects second clock signal CLK-, and the source electrode of the 7th NMOS tube (M10) connects Ground.
2. boot-strapped switch according to claim 1, which is characterized in that when first clock signal clk is high electricity Usually, the CMOS boot-strapped switch circuit is in sample phase, the first NMOS tube (M2) conducting, the 3rd PMOS (M5) grounded-grid is managed, so that the third PMOS tube (M5) is connected, raises the third NMOS tube (M6), the 6th NMOS The grid voltage of pipe (M9), the 8th NMOS tube (M11) and bootstrapped switch (SW), second NMOS tube (M3) and the second PMOS tube (M4) Cut-off, the 6th NMOS tube (M9) conducting, the sampling switch (SW) are closed, and the 8th NMOS tube (M11) conducting is described First capacitance (C1) is connected to the grid source electrode of bootstrapped switch (SW), not due to the middle total electrical charge stored of first capacitance (C1) Become, the grid step voltage of the bootstrapped switch (SW) is raised to VDD+Vin, and the gate-source voltage of the bootstrapped switch (SW) is VDD.
3. boot-strapped switch according to claim 2, which is characterized in that when first clock signal clk is low electricity Usually, the CMOS boot-strapped switch circuit is in the holding stage, first PMOS tube (M1), the second NMOS tube (M3) and Second PMOS tube (M4) is connected, and third PMOS tube (M5) grid meets operating voltage VDD, and the third PMOS tube (M5) is cut Only, the 6th NMOS tube (M9) cut-off, the sampling switch (SW) disconnect, and pass through second NMOS tube (M3) and second PMOS tube (M4) charges to operating voltage VDD to the first capacitance (C1), and the capacitance of first capacitance (C1) is F, then described The electricity that F*VDD is stored in first capacitance (C1), due to the third PMOS tube (M5) end, first capacitance (C1) and Sampling switch (SW) detaches, and the source electrode of the sampling switch (SW) is grounded by second NMOS tube (M3), grid passes through the Four NMOS tubes (M7) and the 5th NMOS tube (M8) ground connection, to discharge.
CN201811042575.4A 2018-09-07 2018-09-07 Grid voltage bootstrapping switch Active CN108777579B (en)

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CN110635791A (en) * 2019-09-06 2019-12-31 重庆邮电大学 Grid voltage bootstrap sampling switch circuit adopting mirror image structure
CN110635791B (en) * 2019-09-06 2023-03-31 重庆邮电大学 Grid voltage bootstrap sampling switch circuit adopting mirror image structure
CN111245413A (en) * 2020-01-20 2020-06-05 电子科技大学 High-speed high-linearity grid voltage bootstrap switch circuit
CN111245413B (en) * 2020-01-20 2023-05-26 电子科技大学 High-speed high-linearity grid voltage bootstrap switch circuit
CN113206659A (en) * 2021-05-10 2021-08-03 西安电子科技大学重庆集成电路创新研究院 High-speed high-linearity grid voltage bootstrap switch for pipeline ADC
CN113206659B (en) * 2021-05-10 2022-05-10 西安电子科技大学重庆集成电路创新研究院 High-speed high-linearity grid voltage bootstrap switch for pipeline ADC
CN113726321A (en) * 2021-09-06 2021-11-30 联合微电子中心有限责任公司 Bootstrap switch circuit and analog-to-digital converter
CN113726321B (en) * 2021-09-06 2023-09-22 联合微电子中心有限责任公司 Bootstrap switch circuit and analog-to-digital converter

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