CN100464504C - A sampling device for analog signal - Google Patents
A sampling device for analog signal Download PDFInfo
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- CN100464504C CN100464504C CNB2006101623151A CN200610162315A CN100464504C CN 100464504 C CN100464504 C CN 100464504C CN B2006101623151 A CNB2006101623151 A CN B2006101623151A CN 200610162315 A CN200610162315 A CN 200610162315A CN 100464504 C CN100464504 C CN 100464504C
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Abstract
The disclosed sampling device for analog signal comprises a sampling hold circuit and an offset circuit to turn on or off transistor in last circuit. Wherein, when turning on the transistor, keeping the potential difference between the control electrode of transistor and the first electrode as constant for high linear sampling; when turning off the transistor, holding the sample signal.
Description
Technical field
The present invention relates to the analog signal Sampling techniques, particularly a kind of sampling device for analog signal.
Background technology
To analog signal sampling is to realize signal digitalized prerequisite, in the prior art, generally adopts complementary metal oxide semiconductors (CMOS) pipe (MOS, Metal Oxide Semiconductor), capacitor and operational amplifier to form sample circuit.Fig. 1 is the basic structure schematic diagram of existing sample circuit, and as shown in Figure 1, this sample circuit comprises: four switch sw1, sw2, sw3, sw4, two capacitor C
s, C
iAnd an operational amplifier A, general, the current potential of reference signal REF is 1/2nd of a used operational amplifier A power supply high level, and switch sw1 generally selects P channel MOS tube (PMOS pipe) for use, takes place effectively to prevent the clamper phenomenon.When clock signal PH1 is 1 (high level as 2.5V, 3V, 3.3V, 5V, in order to state conveniently, is selected 5V for use as high level), when clock signal PH2 is 0 (low level is as OV), switch sw1, sw3 closure, and sw2, sw4 disconnect, and at this moment, input signal V
InBy sw1, reference signal REF by sw3 to capacitor C
sThe two ends charging, capacitor C
iThe value that then keeps last time; When clock signal PH2 is 1, clock signal PH1 is 0 o'clock, switch sw2, sw4 closure, and sw1, sw3 disconnect, and at this moment, capacitor C
sThe electric charge that remains on node n2 has been passed to capacitor C by sw4
i, form the action of an integration, finish signals sampling.
But sample circuit shown in Figure 1 requires input signal V
InTo be common mode electrical level with reference signal REF level (2.5V), and real input signal V
InGenerally be to be the common-mode point of signal level with 0V, therefore need be to input signal V
InCarry out some and handle, increased the complexity of sample circuit.If direct input signal V
InBecause switch sw1 is the PMOS pipe among Fig. 1, its grid incoming clock signal, source electrode inserts input signal, drain electrode is as output, therefore, be added in the minimum 0V (the clock signal level switches) of being of gate voltage current potential on the PMOS pipe between low level 0V and high level 5V, when input signal is lower than PMOS pipe cut-in voltage | V
t| the time, will cause switch to be in off-state, can not be to input signal V
InSample.
Application number is that 02131732.1 patent application discloses a kind of scheme to the analog signal sample conversion that is lower than potential minimum in the circuit, it is the improvement project that can not propose the analog signal sampling that is lower than PMOS pipe cut-in voltage at sample circuit shown in Figure 1, as shown in Figure 2, Fig. 2 is the implementation method schematic diagram to the analog signal sample circuit that is lower than potential minimum in the circuit.
This analog signal sample circuit shown in Figure 2 comprises: biasing circuit is set, produces two level, make the PMOS pipe be in conducting or off-state in the corresponding time period.
The control of switch SW 1 subject clock signal CK, when clock signal CK was 1, switch SW 1 closure made that gate pmos utmost point G point current potential is the 2V that presets, at this moment, input signal V no matter
InBe in (1V～+ what value in 1V), PMOS manages not can conducting, capacitor C
sKeep last value; When clock signal CK is 0, switch SW 1 disconnects, the current potential at capacitor C 1 one end node n1 places is reduced to 0V by 5V, because capacitor C 1 does not does not discharge and recharge path, therefore capacitor C 1 both end voltage can not be suddenlyd change, make gate pmos utmost point G point current potential reduce to-3V, and can keep long period of time, as input signal V by 2V
InGreater than (3V+|V
t|) time, PMOS manages conducting, to capacitor C
sCharging, output signal V
o=V
In, finish sampling to analog signal, that is to say, can finish the negative voltage in the certain limit promptly greater than (3V+|V
t|) sampling.Here, V
tBe PMOS pipe cut-in voltage.
Therefore when analog signal sample circuit shown in Figure 2 was sampled, PMOS managed conducting, and the voltage potential perseverance is-3V that voltage potential is V on the source electrode on its grid
In, the potential difference of source electrode and grid is (3-V
In), because the conducting resistance of PMOS pipe is relevant with the potential difference of source grid, thus the sampled signal V that causes this analog signal sample circuit to be exported
oThe linearity is relatively poor.
Summary of the invention
In view of this, main purpose of the present invention is to provide a kind of sampling device for analog signal, can improve the linearity of sampled signal.
For achieving the above object, the invention provides a kind of sampling device for analog signal, this device comprises: sampling hold circuit and biasing circuit, wherein,
Sampling hold circuit comprises control utmost point input, the first electrode input and second electrode output; Control utmost point input receives the first output signal V of auto bias circuit
G, the first electrode input receiving inputted signal VIN, and to coming the first output signal V of auto bias circuit
GAnd input signal VIN compares: if the first output signal V
GWith the difference absolute value of input signal VIN cut-in voltage greater than sampling hold circuit | V
t|, VIN samples to input signal, and second electrode output is exported the second output signal Vo; Otherwise the second output signal Vo of second electrode output output kept the level in a last moment;
Biasing circuit comprises signal input part, the first reference signal input, the second reference signal input, first clock signal input terminal, second clock signal input part and control output end;
Signal input part receiving inputted signal VIN, the first reference signal input receives with reference to high level signal VDD, the second reference signal input receives reference low level signal VSS, first clock signal input terminal receives the first clock signal Ph1, the second clock signal input part receives second clock signal Ph2, and under the first clock signal Ph1 and second clock signal Ph2 control, the first output signal V is exported in the control output end
GGive sampling hold circuit.
Preferably, described biasing circuit comprises: switch SW 1, SW2 and SW3 and capacitor C
i, wherein,
Switch SW 1 is attempted by in the circuit with switch SW 2, and switch SW 1 first termination is received with reference to high level signal VDD, second end and capacitor C
iFirst end link to each other; Switch SW 2 first terminations are received reference low level signal VSS, second end and capacitor C
iFirst end link to each other;
First termination as the signal input part of biasing circuit of switch SW 3 is received input signal VIN, second end and the capacitor C of the output of the described biasing circuit of conduct of switch SW 3
iSecond end link to each other;
The conducting and the disconnection of first clock signal Ph1 while control switch SW1 and switch SW 3, conducting and the disconnection of second clock signal Ph2 control switch SW2;
Capacitor C
iSecond end export the first output signal V as the output of biasing circuit
G
Preferably, described sampling hold circuit comprises PMOS pipe and capacitor C
s
The source electrode receiving inputted signal VIN of PMOS pipe, drain electrode and capacitor C
sAn end link to each other, export the second output signal Vo, the control utmost point receives the first output signal V of auto bias circuit
G
Capacitor C
sOther end ground connection.
Preferably, described is 1.8V or 2.5V or 3V or 3.3V or 5V with reference to high level signal VDD current potential; Described reference low level signal VSS current potential is 0V.
When the first clock signal Ph1 is 1, second clock signal Ph2 is 0, at this moment, switch SW 1 and switch SW 3 closures, switch SW 2 disconnects capacitor C
iThe input current potential is the current potential with reference to high level signal VDD, and the output current potential is the current potential of input signal VIN, and the grid potential of PMOS pipe is the current potential of input signal VIN, source potential also is the current potential of input signal VIN, potential difference is 0 between the grid source, and the PMOS pipe is in off-state, capacitor C
sThe level that keeps a moment, the second output signal Vo is in hold mode;
When the first clock signal Ph1 by 1 become 0, when second clock signal Ph2 is 0, switch SW 1, SW2, SW3 disconnect capacitor C
iTwo ends keep the level in a moment, and potential difference is 0 between the gate pmos source, is in off-state, capacitor C
sThe level that was keeping a last moment, the second output signal Vo is in hold mode;
When the first clock signal Ph1 be 0, when second clock signal Ph2 becomes 1 by 0, switch SW 1, SW3 disconnect, switch SW 2 closures, capacitor C
iThe input current potential becomes 0 by 1, capacitor C
iCurrent potential that the output current potential is pulled to input signal VIN and potential difference with reference to the current potential of high level signal VDD, the gate pmos electrode potential is the current potential of input signal VIN and potential difference with reference to the current potential of high level signal VDD, and source potential is the current potential of input signal VIN, potential difference is the current potential of negative reference high level signal VDD between the gate pmos source, PMOS manages conducting, to capacitor C
sCharge, simultaneously input signal VIN is sampled, the second output signal Vo of output equals input signal VIN;
When the first clock signal Ph1 be 0, when second clock signal Ph2 becomes 0 by 1, switch SW 1, SW2, SW3 disconnect, capacitor C
iTwo ends keep the level in a moment, and potential difference still is in conducting state for the current potential of negative reference high level signal VDD between the gate pmos source, continue capacitor C
sCharge, simultaneously input signal VIN is sampled, the second output signal Vo of output equals input signal VIN;
Then, the first clock signal Ph1 by 0 become 1, second clock signal Ph2 is 0, so moves in circles, and finishes sampling and maintenance to analog signal.
As seen from the above technical solutions, sampling device for analog signal provided by the invention, by biasing circuit is set, make that transistor is in conducting or off-state in the corresponding time period in the sampling hold circuit: when transistor during in conducting state, potential difference keeps constant between the transistor controls utmost point and first electrode, do not change, realize high linearity sampling the input analog signal with input voltage signal; When transistor during, the sampled signal of high linearity is kept in off-state.Apparatus of the present invention have been finished the high linearity sampling process to analog signal, and, to being lower than the analog signal of power cathode voltage, also realized the sampling of high linearity.
Apparatus of the present invention can be used as the prime of high-resolution analog signal to digital signal converter, particularly have great importance in the application of ammeter measured chip.
Description of drawings
Fig. 1 is the basic structure schematic diagram of existing sample circuit;
Fig. 2 is the implementation method schematic diagram to the analog signal sample circuit that is lower than potential minimum in the circuit;
Fig. 3 is a sampling device for analog signal structural representation of the present invention;
Fig. 4 is based on the structural representation of the preferred embodiment of Fig. 3.
Embodiment
Core concept of the present invention is: biasing circuit is set, make that transistor is in conducting or off-state in the corresponding time period in the sampling hold circuit: when transistor during in conducting state, potential difference keeps constant between the transistor controls utmost point and first electrode, do not change, realize high linearity sampling the input analog signal with input voltage signal; When transistor during, the sampled signal of high linearity is kept in off-state.
For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in further detail below in conjunction with the accompanying drawings and the specific embodiments.
Fig. 3 is a sampling device for analog signal structural representation of the present invention, and as shown in Figure 3, this device comprises sampling hold circuit 32 and biasing circuit 31, and has provided the signal of clock signal, and each element circuit is described below:
Sampling hold circuit 32, control utmost point input receives the first output signal V of auto bias circuit 31
G, the first electrode input receiving inputted signal VIN, and to coming the first output signal V of auto bias circuit 31
GAnd input signal VIN compares: if the first output signal V
GWith the absolute value of the difference of input signal VIN cut-in voltage greater than sampling hold circuit | V
t|, sampling hold circuit is sampled to input signal VIN, and second electrode output is exported the second output signal Vo; Otherwise the second output signal Vo of second electrode output output kept the level in a last moment.
Biasing circuit 31, signal input part receiving inputted signal VIN, the first reference signal input receives with reference to high level signal VDD, the second reference signal input receives reference low level signal VSS, first clock signal input terminal receives the first clock signal Ph1, the second clock signal input part receives second clock signal Ph2, and under the first clock signal Ph1 and second clock signal Ph2 control, exports the first output signal V
GGive sampling hold circuit 32.
The operation principle of device shown in Figure 3 is:
When the first clock signal Ph1 effective, when second clock signal Ph2 is invalid, the first reference signal input and signal input part conducting, the second reference signal input disconnects, the control output end of biasing circuit 31 and signal input part conducting, the first output signal V of output
G=VIN, at this moment, the input signal of sampling hold circuit 32 control utmost point inputs is V
G, the input signal of the first electrode input is VIN, the potential difference of the control utmost point and first electrode is that the second output signal Vo of 0, the second electrode output keeps the level in a moment;
When the first clock signal Ph1 invalid, when second clock signal Ph2 was effective, the first reference signal input and signal input part disconnected, the second reference signal input conducting, the control output end of biasing circuit 31 and signal input part disconnect, the first output signal V of biasing circuit 31 outputs
GBe pulled to (VIN-VDD+VSS), at this moment, the input signal of sampling hold circuit 32 control utmost point inputs is (VIN-VDD+VSS), the input signal of the first electrode input still is VIN, the potential difference of the control utmost point and first electrode is (VDD+VSS), the second output signal Vo=VIN of second electrode output is to analog signal sampling.
Fig. 4 is based on the structural representation of the preferred embodiment of Fig. 3, and as shown in Figure 4, this sampling device for analog signal comprises sampling hold circuit 31 and biasing circuit 32, and has provided the signal of clock signal.
Wherein, sampling hold circuit 32 is used for input signal VIN is sampled and keeps, and comprises transistor 401 and capacitor C
s, the first electrode receiving inputted signal VIN of transistor 401, second electrode and capacitor C
sAn end link to each other, the control utmost point receives the first output signal V of auto bias circuit 31
G
Capacitor C
sOther end ground connection.
In the present embodiment, transistor 401 is PMOS pipes, and the grid of PMOS pipe is the control utmost point, and source electrode is first electrode, and drain electrode is second electrode.
Biasing circuit 32 comprises switch SW 1, switch SW 2, switch SW 3 and capacitor C
i
Switch SW 1 is attempted by in the circuit with switch SW 2, and switch SW 1 one terminations are received with reference to high level signal VDD, the other end and capacitor C
iAn end link to each other; Switch SW 2 receives reference low level signal VSS, the other end and capacitor C
iAn end link to each other; Termination as the signal input part of biasing circuit of switch SW 3 is received input signal VIN, the other end and the capacitor C as the output of biasing circuit of switch SW 3
iThe other end link to each other.
The conducting and the disconnection of first clock signal Ph1 while control switch SW1 and switch SW 3, conducting and the disconnection of second clock signal Ph2 control switch SW2.
Capacitor C
iThe other end as the output of biasing circuit export the first output signal V
G
In this example, can be 1.8V or 2.5V with reference to high level signal VDD current potential, also can be 3V or 3.3V or 5V, with reference to the size of high level signal VDD current potential influence the analog signal negative voltage sample range (right＜-VDD+|V
t| analog signal can not sample), in actual applications, the current potential with reference to high level signal VDD can be set as required, usually, reference low level signal VSS current potential is 0V.It is 1 o'clock that the first clock signal Ph1 is set, switch SW 1 and switch SW 3 are effective, promptly be in closure state, second clock signal Ph2 is 1 o'clock, and switch SW 2 is effective, certainly, in actual use, it is 0 o'clock that the first clock signal Ph1 also can be set, and switch SW 1 and switch SW 3 are effective, second clock signal Ph2 is 0 o'clock, and switch SW 2 is effective.
When the first clock signal Ph1 be 1, when second clock signal Ph2 is 0, switch SW 1 and switch SW 3 closures, switch SW 2 disconnects, capacitor C
iThe input current potential is VDD, and the output current potential is VIN, and the gate pmos electrode potential is VIN, and source potential also is VIN, and potential difference is 0 between the grid source, and the PMOS pipe is in off-state, capacitor C
sThe level that was keeping a last moment, the second output signal Vo of drain electrode output is in hold mode.
When the first clock signal Ph1 by 1 become 0, when second clock signal Ph2 is 0, switch SW 1, SW2, SW3 disconnect capacitor C
iIt is that the input current potential is VDD that two ends keep the level in a moment, and the output current potential is VIN, and potential difference is 0V between the gate pmos source, is in off-state, capacitor C
sThe level that was keeping a last moment, the second output signal Vo of drain electrode output is in hold mode.
When the first clock signal Ph1 be 0, when second clock signal Ph2 becomes 1 by 0, switch SW 1, SW3 disconnect, switch SW 2 closures, capacitor C
iThe input current potential becomes 0 by 1 and promptly drops to 0V by VDD, because capacitor C
iThe voltage at two ends can not suddenly change, and makes capacitor C
iThe output current potential is pulled to (VIN-VDD), and the gate pmos electrode potential is (VIN-VDD), and source potential is VIN, and potential difference is that (VDD), PMOS manages conducting, to capacitor C between the grid source
sCharge, simultaneously input signal VIN is sampled, the second output signal Vo=VIN of drain electrode output, finish sampling to analog signal, and, because potential difference between the grid source (VDD) keeps constant, does not change with input voltage VIN, not only can finish for the negative supply voltage in the certain limit promptly greater than (VDD+|V
t|) the sampling of voltage, and, make sampled signal linearity height.
When the first clock signal Ph1 be 0, when second clock signal Ph2 becomes 0 by 1, switch SW 1, SW2, SW3 disconnect, capacitor C
iTwo ends keep the level in a moment, i.e. capacitor C
iThe input current potential is 0, and the output current potential is (VIN-VDD), and potential difference is-VDD between the gate pmos source, still is in conducting state, continues capacitor C
sCharge, the second output signal Vo=VIN of drain electrode output simultaneously continues sampling.
Afterwards, the first clock signal Ph1 by 0 become 1, second clock signal Ph2 is 0, so move in circles, sampling and maintenance have just been finished to analog signal, simultaneously, also can carry out the sampling of high linearity, in the ammeter measured chip, can be used as the prime of the analog signal of high-resolution and high linearity to digital signal converter to the analog signal that is lower than power cathode voltage.
More than lift preferred embodiment; the purpose, technical solutions and advantages of the present invention are further described; institute is understood that; the above only is preferred embodiment of the present invention; not in order to restriction the present invention; within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (5)
1. a sampling device for analog signal is characterized in that, this device comprises: sampling hold circuit and biasing circuit, wherein,
Sampling hold circuit comprises control utmost point input, the first electrode input and second electrode output; Control utmost point input receives the first output signal V from described biasing circuit
G, the first electrode input receiving inputted signal VIN, and to the first output signal V from described biasing circuit
GAnd described input signal VIN compares: if the described first output signal V
GWith the difference absolute value of described input signal VIN cut-in voltage greater than described sampling hold circuit | V
t|, described input signal VIN to be sampled, described second electrode output is exported the second output signal Vo; Otherwise the described second output signal Vo of described second electrode output output kept the level in a last moment;
Biasing circuit comprises signal input part, the first reference signal input, the second reference signal input, first clock signal input terminal, second clock signal input part and control output end;
Signal input part receives described input signal VIN, the first reference signal input receives with reference to high level signal VDD, the second reference signal input receives reference low level signal VSS, first clock signal input terminal receives the first clock signal Ph1, the second clock signal input part receives second clock signal Ph2, and under described first clock signal Ph1 and described second clock signal Ph2 control, the described first output signal V is exported in the control output end
GGive described sampling hold circuit.
2. device as claimed in claim 1 is characterized in that, described biasing circuit comprises: switch SW 1, SW2 and SW3 and capacitor C
i, wherein,
Switch SW 1 is attempted by in the circuit with switch SW 2, and described switch SW 1 first termination is received described with reference to high level signal VDD, second end and described capacitor C
iFirst end link to each other; Described switch SW 2 first terminations are received described reference low level signal VSS, second end and described capacitor C
iFirst end link to each other;
First termination of the signal input part of the described biasing circuit of conduct of switch SW 3 is received described input signal VIN, second end of the output of the described biasing circuit of conduct of switch SW 3 and described capacitor C
iSecond end link to each other;
The first clock signal Ph1 controls the conducting and the disconnection of described switch SW 1 and switch SW 3 simultaneously, and second clock signal Ph2 controls the conducting and the disconnection of described switch SW 2;
Described capacitor C
iSecond end export the described first output signal V as the output of described biasing circuit
G
3. device as claimed in claim 1 or 2 is characterized in that, described sampling hold circuit comprises PMOS pipe and capacitor C
s
The source electrode of PMOS pipe receives described input signal VIN, drain electrode and described capacitor C
sAn end link to each other, export the described second output signal Vo, the control utmost point receives the first output signal V from described biasing circuit
G,
Described capacitor C
sOther end ground connection.
4. device as claimed in claim 2 is characterized in that, described is 1.8V or 2.5V or 3V or 3.3V or 5V with reference to high level signal VDD current potential; Described reference low level signal VSS current potential is 0V.
5. device as claimed in claim 2 is characterized in that:
When the described first clock signal Ph1 is 1, described second clock signal Ph2 is 0, at this moment, described switch SW 1 and switch SW 3 closures, described switch SW 2 disconnects described capacitor C
iThe input current potential is the current potential with reference to high level signal VDD, the output current potential is the current potential of input signal VIN, the grid potential of described PMOS pipe is the current potential of input signal VIN, source potential also is the current potential of input signal VIN, potential difference is 0 between the grid source, described PMOS pipe is in off-state, described capacitor C
sThe level that keeps a moment, the described second output signal Vo is in hold mode;
When the described first clock signal Ph1 by 1 become 0, when described second clock signal Ph2 is 0, described switch SW 1, SW2, SW3 disconnect described capacitor C
iTwo ends keep the level in a moment, and potential difference is 0 between described gate pmos source, is in off-state, described capacitor C
sThe level that was keeping a last moment, the described second output signal Vo is in hold mode;
When the described first clock signal Ph1 be 0, when described second clock signal Ph2 becomes 1 by 0, described switch SW 1, SW3 disconnect, described switch SW 2 closures, described capacitor C
iThe input current potential becomes 0 by 1, described capacitor C
iCurrent potential that the output current potential is pulled to input signal VIN and potential difference with reference to the current potential of high level signal VDD, current potential that described gate pmos electrode potential is input signal VIN and potential difference with reference to the current potential of high level signal VDD, and source potential is the current potential of input signal VIN, potential difference is the current potential of negative reference high level signal VDD between described gate pmos source, the conducting of described PMOS pipe is to described capacitor C
sCharge, simultaneously described input signal VIN is sampled, the described second output signal Vo of output equals input signal VIN;
When the described first clock signal Ph1 be 0, when described second clock signal Ph2 becomes 0 by 1, described switch SW 1, SW2, SW3 disconnect, described capacitor C
iTwo ends keep the level in a moment, and potential difference still is in conducting state for the current potential of negative reference high level signal VDD between described gate pmos source, continue capacitor C
sCharge, simultaneously described input signal VIN is sampled, the described second output signal Vo of output equals input signal VIN;
Then, the described first clock signal Ph1 by 0 become 1, described second clock signal Ph2 is 0, so moves in circles, and finishes sampling and maintenance to analog signal.
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|---|---|---|---|
| CNB2006101623151A CN100464504C (en) | 2006-12-11 | 2006-12-11 | A sampling device for analog signal |
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|---|---|---|---|
| CNB2006101623151A CN100464504C (en) | 2006-12-11 | 2006-12-11 | A sampling device for analog signal |
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| CN100464504C true CN100464504C (en) | 2009-02-25 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010149060A1 (en) * | 2009-06-26 | 2010-12-29 | 北京中星微电子有限公司 | Analog signal sampling circuit and switching circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2330741A3 (en) * | 2009-12-03 | 2014-09-17 | Nxp B.V. | Switch-body PMOS switch with switch-body dummies |
| CN102098034B (en) * | 2009-12-15 | 2014-07-30 | 北京中星微电子有限公司 | Bootstrap sampling circuit |
| CN104052459B (en) * | 2014-06-06 | 2017-08-25 | 华为技术有限公司 | A kind of sample circuit and the method for sampling |
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| US5872469A (en) * | 1996-04-05 | 1999-02-16 | Analog Devices, Inc. | Switched capacitor circuit adapted to store charge on a sampling capacitor related to a sample for an analog signal voltage and to subsequently transfer such stored charge |
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| CN1485988A (en) * | 2002-09-23 | 2004-03-31 | 珠海炬力集成电路设计有限公司 | Method for sampling and transforming analog signal below lowest electric potential in a circuit |
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|---|---|---|---|---|
| CN1088032A (en) * | 1992-11-04 | 1994-06-15 | Rca·汤姆森许可公司 | Switched capacitor D/A converter |
| US5872469A (en) * | 1996-04-05 | 1999-02-16 | Analog Devices, Inc. | Switched capacitor circuit adapted to store charge on a sampling capacitor related to a sample for an analog signal voltage and to subsequently transfer such stored charge |
| CN1482741A (en) * | 2002-06-18 | 2004-03-17 | 模拟设备股份有限公司 | High-insulation switch capacitor structure |
| CN1485988A (en) * | 2002-09-23 | 2004-03-31 | 珠海炬力集成电路设计有限公司 | Method for sampling and transforming analog signal below lowest electric potential in a circuit |
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