CN101587753B - Analog signal sampling circuit and switch capacitance circuit - Google Patents
Analog signal sampling circuit and switch capacitance circuit Download PDFInfo
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- CN101587753B CN101587753B CN200910087802.XA CN200910087802A CN101587753B CN 101587753 B CN101587753 B CN 101587753B CN 200910087802 A CN200910087802 A CN 200910087802A CN 101587753 B CN101587753 B CN 101587753B
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Abstract
The present invention provides an analog signal sampling circuit capable of enabling the circuit to have high linearity, meanwhile, the processing of signal less than the minimum voltage in the circuit can be implemented. The analog signal sampling circuit can generate the constant voltage by arranging the voltage constant module as a voltage between gate source poles when the PMOSFET tube of the switch tube is conductive, the voltage between the grid and the source pole can be kept constant without changing with the variation of the input signal when the PMSFET tube is in the conducting state, the conductive electric resistance of the PMOSFET tube can not change following with the variation of the input signal, at last the PMOSFET has constant conductive electric resistance, the signal distortion through the PMOSFET tube is smaller, the high linearity sampling can be implemented. The invention also provides a switch capacitance circuit.
Description
Technical field
The present invention relates to electronic technology field, particularly relate to a kind of simulating signal sample circuit and a kind of switched-capacitor circuit.
Background technology
Switched-capacitor circuit (Switched Capacitor Circuit) is the switch that controlled by subject clock signal and capacitor is the circuit of basic composition; Utilize the storage of electric charge and shift the various processing capacities realized signal.In side circuit, sometimes can not meet the demands with the circuit that switch and capacitor are basic comprising, combine with amplifier or operational amplifier, comparer etc. so switched-capacitor circuit is normal, to realize generation, the conversion of electric signal and to process.
In common simulating signal sample circuit, sampling hold circuit realizes the various processing capacities to signal with MOS switched-capacitor circuit usually exactly, such as, and the sample circuit shown in Fig. 1.Common CMOS technology, the operating voltage that chip uses is minimum is 0V, is up to 5V (different according to technique, to also have 2.5V, 3.3V, 1.8V etc., for convenience of description, after this all represent ceiling voltage with 5V).Described sample circuit is made up of jointly four interrupteur SW 1, SW2, SW3, SW4 and two electric capacity Cs, Cint and an operational amplifier A 1, and the circuit comprising described interrupteur SW 1, SW2, SW3, SW4 and electric capacity Cs belongs to above-mentioned switched-capacitor circuit.In order to obtain maximum signal amplitude, the current potential of REF is generally the half of ceiling voltage, and (be called common mode electrical level, for fully differential signal, common mode electrical level is exactly its middle level value.In order to make the signal amplitude of process maximum, often common mode electrical level can be selected at Vdd/2 place), i.e. 2.5V.Be used for driving the clock signal of described circuit also as shown in Figure 1.The principle of work of this circuit is: when clock signal PH1 is " 1 " (high level, 5V), interrupteur SW 1, SW3 conducting, and SW2, SW4 turn off, and sampled by input signal on Cs, Cint then remains the value of last time; When clock signal PH2 is " 1 ", interrupteur SW 2, SW4 conducting, SW1, SW3 turn off, and Cs capacitive transmission to Cint will realize integrating function.This circuit requirement take REF as the common mode electrical level of 2.5V as input signal.
In actual applications, if the common mode electrical level of input signal is 0V, now, above-mentioned sample circuit is by cisco unity malfunction.Because in CMOS sample circuit, sampling switch is normally managed by the PMOSFET of single P-type crystal pipe (PMOSFET), single N-type transistor (NMOSFET) or a pair complementation and NMOSFET pipe forms; When input signal is using 0 level as common mode electrical level, PMOSFET is managed, its grid voltage will be 0V, if applied signal voltage is less than 0V, then Vgs (gate source voltage) > Vth (Vth is the threshold voltage of PMOS, is negative value), now PMOSFET pipe is in cut-off state, can not conducting, cannot sample; For NMOSFET pipe, if input signal is using 0 level as common mode electrical level, can directly causes PN junction positively biased, make switch cisco unity malfunction.
Existing solution is: by arranging biasing circuit, produces control level, makes sampling switch be in turn-on and turn-off two states in the corresponding time period, can realize the sample conversion to the simulating signal lower than potential minimum in circuit.Such as, the circuit that publication number is CN 1964197A, publication date is a kind of sampling of the simulating signal lower than potential minimum in circuit disclosed in the Chinese patent on May 16th, 2007, as shown in Figure 2, in circuit, the forward voltage of sampling switch is Vgs=Va-Vdd-Vin (n) to schematic diagram; And for example, Authorization Notice No. is CN1266842C, authorized announcement date is a kind of sampling device for analog signal disclosed in the Chinese patent on July 26th, 2006, as shown in Figure 3, the sampling switch forward voltage of this device is Vgs=Vin (n-1)-Vdd-Vin (n) to structural representation.But, above-mentioned sample circuit, because the forward voltage (voltage namely between grid source electrode) of sampling switch is relevant with input signal, change along with input signal change, the conducting resistance of sampling switch is also changed with signal intensity, cause the signal after sampling to produce distortion, high linearity sampling can not be realized.
Summary of the invention
Technical matters to be solved by this invention is to provide a kind of simulating signal sample circuit and a kind of switched-capacitor circuit, and circuit can be made to have high linearity, meanwhile, can realize processing lower than the signal of minimum voltage in circuit.
In order to solve the problem, the invention discloses a kind of simulating signal sample circuit, comprising interrupteur SW 4, SW5, electric capacity Cs, Cint and operational amplifier A 1, wherein:
Interrupteur SW 4 controls by clock PH1, a terminated nodes n1, another termination reference voltage;
Interrupteur SW 5 controls by clock PH2, a terminated nodes n1, the inverting input of another termination operational amplifier A 1;
The in-phase input end of operational amplifier A 1 connects reference voltage, integrating capacitor Cint in parallel between inverting input and output terminal;
Electric capacity Cs is connected between node n1 and node n2 as sampling capacitance;
Described simulating signal sample circuit also comprises:
On-off circuit module U1, comprises conducting and controls submodule U11, voltage constant submodule and PMOSFET pipe SW1; Described conducting controls submodule U11 and is connected between node A and input signal, under clock PH1 controls, exports conductivity control signal g1 to node A; Voltage constant submodule, is connected between node A and input signal, under described conductivity control signal g1 controls, produces constant voltage, as voltage between the grid source electrode during SW1 conducting of PMOSFET pipe; The source electrode of PMOSFET pipe SW1 connects input signal, and grid meets node A, and drain electrode meets described node n2, under described conductivity control signal g1 controls, be in turn-on and turn-off two states.
On-off circuit module U2, comprises conducting and controls submodule U21 and PMOSFET pipe SW3; Between the grid that described conducting control submodule U21 is connected on PMOSFET pipe SW3 and ground wire, under clock PH2 controls, export the grid of conductivity control signal g2 to PMOSFET pipe SW3; The source ground line of PMOSFET pipe SW3, drain electrode meets described node n2, under described conductivity control signal g2 controls, be in turn-on and turn-off two states.
Preferably, described voltage constant submodule comprises PMOSFET pipe PM1, PM2, wherein: the drain and gate of PMOSFET pipe PM2 all connects with the source electrode of PMOSFET pipe PM1, and the source electrode of PMOSFET pipe PM2 connects with input signal; The drain and gate of PMOSFET pipe PM1 all connects with node A.
Preferably, described conducting controls submodule U11 and comprises PMOSFET pipe PM3, electric capacity C1, C2, a PMOSFET pipe SW2 and reverser, wherein: the input terminated clock PH1 of reverser, exports termination capacitor C2; The drain electrode of another termination PMOSFET pipe PM3 of electric capacity C2; The source electrode of PMOSFET pipe PM3 and grid all ground wires; The one terminated clock PH1 of electric capacity C1, another terminated nodes A; The drain electrode of interrupteur SW 2 meets node A, and source electrode connects input signal, and grid is received between electric capacity C2 and PMOSFET pipe PM3.
Wherein, described voltage constant submodule produces constant voltage, as voltage between the grid source electrode during SW1 conducting of PMOSFET pipe, makes the conducting resistance of PMOSFET pipe SW1 constant.
Preferably, described conducting controls submodule U21 and comprises electric capacity C3 and PMOSFET pipe PM4, wherein: a terminated clock PH2 of electric capacity C3, the grid of another termination interrupteur SW 3; The grid of PMOSFET pipe PM4 and source electrode all ground wires, drain electrode connects the grid of interrupteur SW 3.
Present invention also offers a kind of switched-capacitor circuit, comprising:
Conducting control module, is connected between node A and input signal, under controlling at clock PH1, exports conductivity control signal g1 to node A;
Voltage constant module, is connected between node A and input signal, under described conductivity control signal g1 controls, produces constant voltage, as voltage between the grid source electrode during SW1 conducting of PMOSFET pipe;
PMOSFET pipe SW1, source electrode connects input signal, and grid meets node A, drains as signal output part, under described conductivity control signal g1 controls, is in turn-on and turn-off two states.
Preferably, described voltage constant module comprises PMOSFET pipe PM1, PM2, wherein: the drain and gate of PMOSFET pipe PM2 all connects with the source electrode of PMOSFET pipe PM1, and the source electrode of PMOSFET pipe PM2 connects with input signal; The drain and gate of PMOSFET pipe PM1 all connects with node A.
Preferably, described conducting control module comprises PMOSFET pipe PM3, electric capacity C1, C2, a PMOSFET pipe SW2 and reverser, wherein: the input terminated clock PH1 of reverser, exports termination capacitor C2; The drain electrode of another termination PMOSFET pipe PM3 of electric capacity C2; The source electrode of PMOSFET pipe PM3 and grid all ground wires; The one terminated clock PH1 of electric capacity C1, another terminated nodes A; The drain electrode of interrupteur SW 2 meets node A, and source electrode connects input signal, and grid is received between electric capacity C2 and PMOSFET pipe PM3.
Wherein, described voltage constant module, produces constant voltage, as voltage between the grid source electrode during SW1 conducting of PMOSFET pipe, makes the conducting resistance of PMOSFET pipe SW1 constant.
Compared with prior art, the present invention has the following advantages:
First, the present invention is by arranging voltage constant module, produce constant voltage, as the voltage between grid source electrode when being used as the PMOSFET pipe conducting of switching tube, when PMOSFET pipe can be made to be in conducting state, voltages keep constant between grid and source electrode, do not change with the change of input signal, thus the conducting resistance of PMOSFET pipe is not also changed with the change of input signal, PMOSFET pipe is finally made to have constant conducting resistance, make the distorted signals through PMOSFET pipe very little, achieve high linearity sampling.
Secondly, the present invention is provided with conducting control module, and described conducting control module, under the control of clock, exports conductivity control signal, makes PMOSFET pipe be in turn-on and turn-off state respectively in the corresponding time period; When during the voltage of input signal is lower than circuit during minimum voltage, PMOSFET pipe also can normally, enables signal continue to export.
Therefore, the present invention can realize processing lower than the input signal of minimum voltage in circuit, and, make the process of circuit to signal have very high linearity.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of a kind of common simulating signal sample circuit in prior art;
Fig. 2 is the schematic diagram of a kind of simulating signal sample circuit lower than potential minimum in circuit in prior art;
Fig. 3 is the structural representation of a kind of sampling device for analog signal in prior art;
Fig. 4 is the structural drawing of a kind of simulating signal sample circuit described in the embodiment of the present invention one;
Fig. 5 is the preferred version schematic diagram of a kind of simulating signal sample circuit described in the embodiment of the present invention one;
Fig. 6 is the structural drawing of a kind of switched-capacitor circuit described in the embodiment of the present invention two;
Fig. 7 is the preferred version schematic diagram of a kind of switched-capacitor circuit described in the embodiment of the present invention two.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, and below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation.
Under normal circumstances, sampling is carried out to low voltage signal and uses PMOS, and the gate operational voltages of PMOS is 0.When applied signal voltage is lower than 0 level time, the voltage Vgs > Vthp (Vthp is the threshold voltage of PMOS, is negative value) between the grid of PMOS and source electrode.Now, PMOS just can not conducting.So need the grid voltage producing PMOS by arranging circuit, and described grid voltage lower than power cathode voltage, will make Vgs < Vthp, just can make PMOS conducting, realizes sampling.
For the signal after sampling, basic demand is that distortion (distortion) is very little, namely has high linearity.This just required within the sampling period, and the resistance value as the PMOS of sampling switch keeps constant.For PMOS, conduction resistance value when being in conducting state and the voltage Vgs between grid and source electrode are inversely proportional to.In existing sample circuit, the grid voltage of sampling switch is supply voltage (0 or VDD), and be fixed value, and source voltage being input signal, is unfixed; Therefore, the voltage between grid and source electrode changes with signal intensity, thus makes the conducting resistance of sampling switch be an amount with signal intensity.If realize high linearity sampling, just need to make the gate voltage of sampling switch also with signal intensity, thus make the voltage difference between the grid of sampling switch and source electrode constant, have nothing to do with input signal, thus reach high linearity sampling.
The present invention proposes based on above-mentioned principle just.
Embodiment one:
With reference to Fig. 4, show the structural drawing of a kind of simulating signal sample circuit described in embodiment.
Described in the present embodiment, simulating signal sample circuit comprises interrupteur SW 4, SW5, electric capacity Cs, Cint and operational amplifier A 1, wherein:
Interrupteur SW 4 controls by clock PH1, a terminated nodes n1, another termination reference voltage;
Interrupteur SW 5 controls by clock PH2, a terminated nodes n1, the inverting input of another termination operational amplifier A 1;
The in-phase input end of operational amplifier A 1 connects reference voltage, integrating capacitor Cint in parallel between inverting input and output terminal;
Electric capacity Cs is connected between node n1 and node n2 as sampling capacitance;
Described simulating signal sample circuit also comprises:
On-off circuit module U41, comprises conducting and controls submodule U411, voltage constant submodule U412 and PMOSFET pipe SW1; Described conducting controls submodule U411 and is connected between node A and input signal, under clock PH1 controls, exports conductivity control signal g1 to node A; Voltage constant submodule U412, is connected between node A and input signal, under described conductivity control signal g1 controls, produces constant voltage, as voltage between the grid source electrode during SW1 conducting of PMOSFET pipe; The source electrode of PMOSFET pipe SW1 connects input signal, and grid meets node A, and drain electrode meets described node n2, under described conductivity control signal g1 controls, be in turn-on and turn-off two states.
On-off circuit module U42, comprises conducting and controls submodule U421 and PMOSFET pipe SW3; Between the grid that described conducting control submodule U421 is connected on PMOSFET pipe SW3 and ground wire, under clock PH2 controls, export the grid of conductivity control signal g2 to PMOSFET pipe SW3; The source ground line of PMOSFET pipe SW3, drain electrode meets described node n2, under described conductivity control signal g2 controls, be in turn-on and turn-off two states.
For simulating signal sample circuit described in the present embodiment, be used for driving circuit clock signal also as shown in Figure 4.The principle of work of described circuit is as follows:
On-off circuit module U41 and interrupteur SW 4 control by clock PH1, and input signal accesses from on-off circuit module U41, and in a time period of clock PH1, on-off circuit module U41 outputs to node n2 described input signal, and interrupteur SW 4 is in conducting state; Now, if on-off circuit module U2PMOSFET pipe SW3 and interrupteur SW 5 are all in off state, then the described input signal at node n2 place will be sampled on electric capacity Cs.Within another time period of clock PH1, on-off circuit module U41 does not export described input signal, and interrupteur SW 4 is in off state, now, if the PMOSFET pipe SW3 in on-off circuit module U42 and interrupteur SW 5 are all in conducting state, then signal electric capacity Cs obtained through over-sampling can transmit to electric capacity Cint.
In described process of sampling to input signal, conducting in on-off circuit module U41 controls submodule U411, controls by described clock PH1, correspondingly the time period exports conductivity control signal g1 to node A; When described conductivity control signal g1 makes PMOSFET pipe SW1 be in conducting state, described voltage constant submodule U412 is by voltage constant for generation one between node A and the source electrode of PMOSFET pipe SW1, this voltage is the voltage between the grid of PMOSFET pipe SW1 and source electrode, is the forward voltage of PMOSFET pipe SW1.PMOSFET pipe SW1 is when forward voltage is constant, and conducting resistance also will be constant value.
On-off circuit module U42 and interrupteur SW 4 control by clock PH2, in a time period of clock PH2, conducting control submodule U421 in on-off circuit module U42 sends control signal g2 makes PMOSFET pipe SW3 turn off, and now interrupteur SW 5 also turns off, and electric capacity Cint kept the level of a upper time period.In another time period of clock PH2, described conducting control submodule U421 sends control signal g2 makes PMOSFET pipe SW3 conducting, now interrupteur SW 5 also conducting, if the PMOSFET pipe SW1 in on-off circuit module U41 and interrupteur SW 4 are all in off state, the Signal transmissions then electric capacity Cs obtained through over-sampling is on cint, realize integrating function, Vout=Cs/Cint*Vin.
As can be seen from above-mentioned principle of work, a kind of simulating signal sample circuit of the present invention, can realize the analog signal sampling lower than potential minimum in circuit, and, owing to carrying out in the process of sampling, the forward voltage of sampling switch (PMOSFET pipe SW1) is constant, makes the conducting resistance of described sampling switch constant, can not change with the change of input signal, so high linearity sampling can be realized.
The invention will be further described for the following content of the present embodiment.
With reference to Fig. 5, it is a kind of described in the present embodiment preferred version schematic diagram of simulating signal sample circuit.As shown in Figure 5:
Preferably, described voltage constant submodule U412 specifically comprises PMOSFET pipe PM1, PM2, wherein:
The drain and gate of PMOSFET pipe PM2 all connects with the source electrode of PMOSFET pipe PM1, and the source electrode of PMOSFET pipe PM2 connects with input signal;
The drain and gate of PMOSFET pipe PM1 all connects with node A.
Usually, if metal-oxide-semiconductor grid and drain electrode are connected together, this connection connects, because its performance is similar to a diode diode.
Preferably, described conducting controls submodule U411 and specifically comprises PMOSFET pipe PM3, electric capacity C1, C2, a PMOSFET pipe SW2 and reverser, wherein:
The input terminated clock PH1 of reverser, exports termination capacitor C2; The drain electrode of another termination PMOSFET pipe PM3 of electric capacity C2; The source electrode of PMOSFET pipe PM3 and grid all ground wires;
The one terminated clock PH1 of electric capacity C1, another terminated nodes A; The drain electrode of interrupteur SW 2 meets node A, and source electrode connects input signal, and grid is received between electric capacity C2 and PMOSFET pipe PM3.
Preferably, described conducting controls submodule U421 and specifically comprises electric capacity C3 and PMOSFET pipe PM4, wherein:
The one terminated clock PH2 of electric capacity C3, the grid of another termination interrupteur SW 3;
The grid of PMOSFET pipe PM4 and source electrode all ground wires, drain electrode connects the grid of interrupteur SW 3.
In the preferred version of described simulating signal sample circuit, PMOSFET pipe PM1, PM2 that voltage constant submodule comprises, forward voltage Vgs=-2Vth (Vth is the threshold voltage of PMOSFET pipe) when being in conducting state for making sampling switch PMOSFET pipe SW1 is steady state value; Conducting controls submodule U411 and U421, is in conducting or off state for control PMOSFET pipe SW1 and PMOSFET pipe SW3 in the corresponding time period.Detailed process is as follows:
For on-off circuit module U42, the principle of work that described conducting controls submodule U421 is as follows:
For convenience of analyzing, before initialization circuit is started working, the electric charge on electric capacity C3 is 0.When clock PH2 becomes " 1 " from " 0 ", the moment into " 1 " is connect, because the electric charge on electric capacity C3 can not be undergone mutation, so the voltage at Fig. 5 interior joint C place at the input end of clock of on-off circuit module U42, the i.e. grid voltage of PMOSFET pipe SW3, also becomes " 1 "; Now, PMOSFET pipe PM4 forward conduction.PMOSFET pipe PM4 forward conduction makes the voltage at node C place be clamped at Vth place, thus the voltage difference on electric capacity C3 is (Vdd-Vth), and PMOSFET pipe SW3 is turned off.When clock PH2 becomes " 0 " again by " 1 ", connect the moment into " 0 " at the input end of clock of on-off circuit module U42, for ensureing that the electric charge on electric capacity C3 is not undergone mutation, so the voltage at node C place can become (Vth-Vdd), now PMOSFET pipe PM4 is reverse-biased, can not conducting; And PMOSFET pipe SW3 conducting.
For on-off circuit module U41, principle of work and the conducting of described conducting control submodule U411 control submodule U421 roughly the same.When clock PH1 becomes " 1 " from " 0 ", PMOSFET pipe SW2 conducting, the voltage at Fig. 5 interior joint A place, namely the grid voltage of PMOSFET pipe SW1 is Vin (n-1), and the voltage difference on electric capacity C1 is (Vdd-Vin (n-1)).When clock PH1 becomes " 0 " by " 1 ", SW2 turns off.Become the moment of " 0 " at clock PH1, the voltage at node A place becomes (Vin (n-1)-Vdd); Now, the PMOSFET pipe PM1 in described voltage constant submodule, PM2 all positively biased conductings, the voltage at node A place is finally clamped at (Vin (n)-2Vth), and PMOSFET pipe SW1 opens.And for PMOSFET pipe SW1, voltage difference Vgs=Vin (n)-2Vth-Vin (n)=-2Vth between the grid at node A place and the source electrode of input signal end is constant.
Can find out, the forward voltage of PMOSFET pipe SW1 is constant, and therefore, the conducting resistance of PMOSFET pipe SW1 is also constant, is a constant had nothing to do with signal.Thus, the high linearity sampling to input simulating signal can be realized.Meanwhile, because conducting controls the forward voltage that submodule U411 and U421 can produce PMOSFET pipe SW1 and PMOSFET pipe SW3, this circuit can realize sampling to lower than the signal of minimum voltage in circuit.
Embodiment two:
The present embodiment will be described in detail to a kind of switched-capacitor circuit of the present invention.
Switched-capacitor circuit uses MOS technique usually, technological process is fairly simple, and is easy to large-scale integrated, develops faster so obtain at electronic technology field, be widely used in various integrated circuit, as filtering circuit, integrating circuit and sample circuit etc.At present, more and more higher to the accuracy requirement of signal transacting in integrated circuit, therefore, also more and more higher to the requirement of switched-capacitor circuit in practical application, especially to the linearity of circuit.Sometimes, also require also can process the input signal lower than minimum voltage in circuit.
Switched-capacitor circuit of the present invention, by arranging voltage constant module, can make the voltage value constant between the grid of switch when conducting and source electrode, thus making conducting resistance constant, making whole circuit have the higher linearity; By arranging conducting control module, described switched-capacitor circuit can be made to process lower than the input signal of minimum voltage in circuit.
With reference to Fig. 6, it is the structural drawing of a kind of switched-capacitor circuit described in the present embodiment.Described switched-capacitor circuit comprises:
Conducting control module U61, is connected between node A and input signal, under controlling at clock PH1, exports conductivity control signal g1 to node A;
Voltage constant module U62, is connected between node A and input signal, under described conductivity control signal g1 controls, produces constant voltage, as voltage between the grid source electrode during SW1 conducting of PMOSFET pipe;
PMOSFET pipe SW1, source electrode connects input signal, and grid meets node A, drains as signal output part, under described conductivity control signal g1 controls, is in turn-on and turn-off two states.
Described conducting control module U61, controls by described clock PH1, exports conductivity control signal g1 to node A, the turn-on and turn-off of control PMOSFET pipe SW1 in correspondingly time period; When PMOSFET pipe SW1 is in conducting state, described voltage constant module U62 produces a constant voltage between node A and the source electrode of PMOSFET pipe SW1, this voltage is the voltage between the grid of PMOSFET pipe SW1 and source electrode, is the forward voltage of PMOSFET pipe SW1.PMOSFET pipe SW1 is when forward voltage is constant, and conducting resistance also will be constant value.
With reference to Fig. 7, it is the preferred version schematic diagram of a kind of switched-capacitor circuit described in the present embodiment.
Preferably, described voltage constant module U61 comprises PMOSFET pipe PM1, PM2, wherein:
The drain and gate of PMOSFET pipe PM2 all connects with the source electrode of PMOSFET pipe PM1, and source electrode connects with input signal;
The drain and gate of PMOSFET pipe PM1 all connects with node A.
Preferably, described conducting control module U62 comprises PMOSFET pipe PM3, electric capacity C1, C2, a PMOSFET pipe SW2 and reverser, wherein:
The input terminated clock PH1 of reverser, exports termination capacitor C2; The drain electrode of another termination PMOSFET pipe PM3 of electric capacity C2; The source electrode of PMOSFET pipe PM3 and grid all ground wires;
The one terminated clock PH1 of electric capacity C1, another terminated nodes A; The drain electrode of interrupteur SW 2 meets node A, and source electrode connects input signal, and grid is received between electric capacity C2 and PMOSFET pipe PM3.
In sum, a kind of simulating signal sample circuit proposed by the invention and a kind of switched-capacitor circuit, by arranging voltage constant module, the forward voltage of the PMOSFET pipe used as switch and input signal can be made to have nothing to do, do not change with input signal change, thus make the conducting resistance of described switch constant, circuit can be made to have the feature of high linearity; Meanwhile, by arranging the conducting control module of described switch, circuit can be made to process lower than the input signal of potential minimum in circuit.
In embodiment in this instructions, what each embodiment stressed is the difference with other embodiments, between each embodiment identical similar part mutually see.
Above to a kind of simulating signal sample circuit provided by the present invention and a kind of switched-capacitor circuit, be described in detail, apply specific case herein to set forth principle of the present invention and embodiment, the explanation of above embodiment just understands method of the present invention and core concept thereof for helping; Meanwhile, for one of ordinary skill in the art, according to thought of the present invention, all will change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (9)
1. a simulating signal sample circuit, comprises interrupteur SW 4, SW5, electric capacity Cs, Cint and operational amplifier A l, wherein:
Interrupteur SW 4 controls by clock PHl, a terminated nodes n1, another termination reference voltage;
Interrupteur SW 5 controls by clock PH2, a terminated nodes n1, the inverting input of another termination operational amplifier A l;
The in-phase input end of operational amplifier A l connects reference voltage, integrating capacitor Cint in parallel between inverting input and output terminal;
Electric capacity Cs is connected between node n1 and node n2 as sampling capacitance;
It is characterized in that, described simulating signal sample circuit also comprises:
On-off circuit module U1, comprises conducting and controls submodule U11, voltage constant submodule and PMOSFET pipe SW1; Described conducting controls submodule U11 and is connected between node A and input signal, under clock PH1 controls, exports conductivity control signal g1 to node A; Voltage constant submodule, is connected between node A and input signal, under described conductivity control signal g1 controls, produces constant voltage, as voltage between the grid source electrode during SW1 conducting of PMOSFET pipe; The source electrode of PMOSFET pipe SW1 connects input signal, and grid meets node A, and drain electrode meets described node n2, under described conductivity control signal g1 controls, be in turn-on and turn-off two states;
On-off circuit module U2, comprises conducting and controls submodule U21 and PMOSFET pipe SW3; Between the grid that described conducting control submodule U21 is connected on PMOSFET pipe SW3 and ground wire, under clock PH2 controls, export the grid of conductivity control signal g2 to PMOSFET pipe SW3; The source ground line of PMOSFET pipe SW3, drain electrode meets described node n2, under described conductivity control signal g2 controls, be in turn-on and turn-off two states.
2. circuit according to claim 1, is characterized in that, described voltage constant submodule comprises PMOSFET pipe PM1, PM2, wherein:
The drain and gate of PMOSFET pipe PM2 all connects with the source electrode of PMOSFET pipe PM1, and the source electrode of PMOSFET pipe PM2 connects with input signal;
The drain and gate of PMOSFET pipe PM1 all connects with node A.
3. circuit according to claim 1, is characterized in that, described conducting controls submodule U11 and comprises PMOSFET pipe PM3, electric capacity C1, C2, a PMOSFET pipe SW2 and reverser, wherein:
The input terminated clock PH1 of reverser, exports termination capacitor C2; The drain electrode of another termination PMOSFET pipe PM3 of electric capacity C2; The source electrode of PMOSFET pipe PM3 and grid all ground wires;
The one terminated clock PH1 of electric capacity C1, another terminated nodes A; The drain electrode of interrupteur SW 2 meets node A, and source electrode connects input signal, and grid is received between electric capacity C2 and PMOSFET pipe PM3.
4. circuit according to claim 1 and 2, is characterized in that, described voltage constant submodule produces constant voltage, as voltage between the grid source electrode during SW1 conducting of PMOSFET pipe, makes the conducting resistance of PMOSFET pipe SW1 constant.
5. circuit according to claim 1, is characterized in that, described conducting controls submodule U21 and comprises electric capacity C3 and PMOSFET pipe PM4, wherein:
The one terminated clock PH2 of electric capacity C3, the grid of another termination interrupteur SW 3;
The grid of PMOSFET pipe PM4 and source electrode all ground wires, drain electrode connects the grid of interrupteur SW 3.
6. a switched-capacitor circuit, is characterized in that, comprising:
Conducting control module, is connected between node A and input signal, under controlling at clock PH1, exports conductivity control signal g1 to node A;
Voltage constant module, is connected between node A and input signal, under described conductivity control signal g1 controls, produces constant voltage, as voltage between the grid source electrode during SW1 conducting of PMOSFET pipe; Wherein, described conducting control module and voltage constant wired in parallel are connected between node A and input signal;
PMOSFET pipe SW1, source electrode connects input signal, and grid meets node A, drains as signal output part, under described conductivity control signal g1 controls, is in turn-on and turn-off two states.
7. circuit according to claim 6, is characterized in that, described voltage constant module comprises PMOSFET pipe PM1, PM2, wherein:
The drain and gate of PMOSFET pipe PM2 all connects with the source electrode of PMOSFET pipe PM1, and the source electrode of PMOSFET pipe PM2 connects with input signal;
The drain and gate of PMOSFET pipe PM1 all connects with node A.
8. circuit according to claim 6, is characterized in that, described conducting control module comprises PMOSFET pipe PM3, electric capacity C1, C2, a PMOSFET pipe SW2 and reverser, wherein:
The input terminated clock PH1 of reverser, exports termination capacitor C2; The drain electrode of another termination PMOSFET pipe PM3 of electric capacity C2; The source electrode of PMOSFET pipe PM3 and grid all ground wires;
The one terminated clock PH1 of electric capacity C1, another terminated nodes A; The drain electrode of interrupteur SW 2 meets node A, and source electrode connects input signal, and grid is received between electric capacity C2 and PMOSFET pipe PM3.
9. the circuit according to claim 6 or 7, is characterized in that, described voltage constant module, produces constant voltage, as voltage between the grid source electrode during SW1 conducting of PMOSFET pipe, makes the conducting resistance of PMOSFET pipe SW1 constant.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910087802.XA CN101587753B (en) | 2009-06-26 | 2009-06-26 | Analog signal sampling circuit and switch capacitance circuit |
| PCT/CN2010/074394 WO2010149060A1 (en) | 2009-06-26 | 2010-06-24 | Analog signal sampling circuit and switching circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN200910087802.XA CN101587753B (en) | 2009-06-26 | 2009-06-26 | Analog signal sampling circuit and switch capacitance circuit |
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| CN101587753A CN101587753A (en) | 2009-11-25 |
| CN101587753B true CN101587753B (en) | 2014-12-31 |
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| WO (1) | WO2010149060A1 (en) |
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| CN101587753B (en) * | 2009-06-26 | 2014-12-31 | 北京中星微电子有限公司 | Analog signal sampling circuit and switch capacitance circuit |
| CN102098034B (en) * | 2009-12-15 | 2014-07-30 | 北京中星微电子有限公司 | Bootstrap sampling circuit |
| CN102185569B (en) * | 2011-04-07 | 2017-07-07 | 北京中星微电子有限公司 | A kind of output-stage circuit of class-D amplifier |
| US8816887B2 (en) * | 2012-09-21 | 2014-08-26 | Analog Devices, Inc. | Sampling circuit, a method of reducing distortion in a sampling circuit, and an analog to digital converter including such a sampling circuit |
| CN103336159A (en) * | 2013-06-25 | 2013-10-02 | 西安电子科技大学 | Analog signal isolating circuit based on rotary capacitor |
| CN105577137B (en) * | 2014-10-10 | 2019-05-10 | 瑞昱半导体股份有限公司 | For automatically correcting the transmission line drive circuit of impedance matching |
| CN110098836B (en) * | 2018-01-31 | 2024-03-01 | 长沙泰科阳微电子有限公司 | MDAC structure suitable for assembly line ADC |
| CN108696270B (en) * | 2018-05-24 | 2022-02-01 | 上海艾为电子技术股份有限公司 | Analog switch circuit |
| CN108512536B (en) * | 2018-07-10 | 2023-11-28 | 上海艾为电子技术股份有限公司 | Analog switch with constant on-resistance |
| CN111245218B (en) * | 2020-01-14 | 2021-09-17 | 北京集创北方科技股份有限公司 | Switch control circuit, multi-path selection switch circuit and control method thereof |
| CN111953323B (en) * | 2020-07-28 | 2022-05-31 | 北京中星微电子有限公司 | Circuit for signal acquisition |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1841490A (en) * | 2005-03-29 | 2006-10-04 | 夏普株式会社 | Sample-hold circuit and semiconductor device |
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| US6522187B1 (en) * | 2001-03-12 | 2003-02-18 | Linear Technology Corporation | CMOS switch with linearized gate capacitance |
| JP2007019861A (en) * | 2005-07-07 | 2007-01-25 | Matsushita Electric Ind Co Ltd | Analog switching circuit and constant current generation circuit |
| KR100693819B1 (en) * | 2005-07-14 | 2007-03-12 | 삼성전자주식회사 | Circuit and method of track and hold |
| CN100464504C (en) * | 2006-12-11 | 2009-02-25 | 北京中星微电子有限公司 | A sampling device for analog signal |
| CN101587753B (en) * | 2009-06-26 | 2014-12-31 | 北京中星微电子有限公司 | Analog signal sampling circuit and switch capacitance circuit |
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| CN1841490A (en) * | 2005-03-29 | 2006-10-04 | 夏普株式会社 | Sample-hold circuit and semiconductor device |
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