CN101587753A - A kind of simulating signal sample circuit and a kind of switched-capacitor circuit - Google Patents
A kind of simulating signal sample circuit and a kind of switched-capacitor circuit Download PDFInfo
- Publication number
- CN101587753A CN101587753A CN 200910087802 CN200910087802A CN101587753A CN 101587753 A CN101587753 A CN 101587753A CN 200910087802 CN200910087802 CN 200910087802 CN 200910087802 A CN200910087802 A CN 200910087802A CN 101587753 A CN101587753 A CN 101587753A
- Authority
- CN
- China
- Prior art keywords
- pmosfet pipe
- pmosfet
- voltage
- capacitor
- pipe
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 title claims abstract description 83
- 238000005070 sampling Methods 0.000 claims abstract description 36
- 238000000034 method Methods 0.000 abstract description 7
- 238000010586 diagram Methods 0.000 description 7
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 230000035772 mutation Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
- G11C27/02—Sample-and-hold arrangements
- G11C27/024—Sample-and-hold arrangements using a capacitive memory element
- G11C27/026—Sample-and-hold arrangements using a capacitive memory element associated with an amplifier
Landscapes
- Electronic Switches (AREA)
- Measuring Volume Flow (AREA)
Abstract
The invention provides a kind of simulating signal sample circuit, can make circuit have high linearity, simultaneously, can realize handling being lower than in the circuit signal of minimum voltage.Described simulating signal sample circuit is by being provided with the voltage constant module, produce constant voltage, voltage between the grid source electrode when managing conducting as the PMOSFET that is used as switching tube, in the time of making the PMOSFET pipe be in conducting state, it is constant that voltage between grid and the source electrode keeps, the variation with input signal does not change, thereby the conducting resistance of PMOSFET pipe is not also changed with the variation of input signal, finally make the PMOSFET pipe have constant conducting resistance, make the distorted signals of process PMOSFET pipe very little, realized the high linearity sampling.The present invention also provides a kind of switched-capacitor circuit.
Description
Technical field
The present invention relates to electronic technology field, particularly relate to a kind of simulating signal sample circuit and a kind of switched-capacitor circuit.
Background technology
Switched-capacitor circuit (Switched Capacitor Circuit) is that switch and the capacitor controlled by subject clock signal are the circuit of basic composition; Utilize the storage of electric charge and shift the various processing capacities that realize signal.In side circuit, be that the circuit of basic comprising can not meet the demands with switch and capacitor sometimes, combine with amplifier exclusive disjunction amplifier, comparer etc. so switched-capacitor circuit is normal, with generation, conversion and the processing of realization electric signal.
In common simulating signal sample circuit, sampling hold circuit is exactly to realize various processing capacities to signal with the MOS switched-capacitor circuit usually, for example, and sample circuit shown in Figure 1.Common CMOS technology, the operating voltage that chip uses is minimum to be 0V, is up to 5V (according to the technology difference, also have 2.5V, 3.3V, 1.8V etc., for convenience of description, after this all represent ceiling voltage with 5V).Described sample circuit is made of jointly four switch SW 1, SW2, SW3, SW4 and two capacitor C s, Cint and an operational amplifier A 1, belongs to above-mentioned switched-capacitor circuit comprising the circuit of described switch SW 1, SW2, SW3, SW4 and capacitor C s.In order to obtain maximum signal amplitude, the current potential of REF is generally half of ceiling voltage, and (be called common mode electrical level, for the fully differential signal, common mode electrical level is exactly level value in the middle of it.In order to make the signal amplitude maximum of processing, often common mode electrical level can be chosen in the Vdd/2 place), i.e. 2.5V.The clock signal that is used for driving described circuit also as shown in Figure 1.The principle of work of this circuit is: clock signal PH1 be " 1 " (high level, in the time of 5V), switch SW 1, SW3 conducting, SW2, SW4 turn-off, and input signal is sampled on the Cs, Cint is then keeping the value of last time; When clock signal PH2 is " 1 ", switch SW 2, SW4 conducting, SW1, SW3 turn-off, thereby the Cs capacitive transmission is gone up the realization integrating function to Cint.This circuit requirement is the common mode electrical level of 2.5V as input signal with REF.
In actual applications, if the common mode electrical level of input signal is 0V, at this moment, above-mentioned sample circuit is with cisco unity malfunction.Because in the CMOS sample circuit, sampling switch normally is made up of the PMOSFET pipe and the NMOSFET pipe of single P transistor npn npn (PMOSFET), single N transistor npn npn (NMOSFET) or a pair of complementation; When input signal is with 0 level during as common mode electrical level, manage for PMOSFET, its grid voltage will be 0V, if applied signal voltage is less than 0V, Vgs (gate source voltage)＞Vth (Vth is the threshold voltage of PMOS pipe, is negative value) then, this moment, the PMOSFET pipe was in cut-off state, can not conducting, can't sample; For NMOSFET pipe, if input signal be with 0 level as common mode electrical level, can directly cause PN junction positively biased, make the switch cisco unity malfunction.
Existing solution is: by biasing circuit is set, produce control level, make sampling switch be in the turn-on and turn-off two states in the corresponding time period, can realize being lower than the sample conversion of the simulating signal of potential minimum in the circuit.For example, publication number is CN 1964197A, open day was the disclosed a kind of circuit that is lower than the simulating signal sampling of potential minimum in the circuit of Chinese patent on May 16th, 2007, synoptic diagram as shown in Figure 2, the forward voltage of sampling switch is Vgs=Va-Vdd-Vin (n) in the circuit; And for example, Granted publication number is the disclosed a kind of sampling device for analog signal of Chinese patent on July 26th, 2006 for CN 1266842C, Granted publication day, structural representation as shown in Figure 3, the sampling switch forward voltage of this device is Vgs=Vin (n-1)-Vdd-Vin (n).Yet, above-mentioned sample circuit, because the forward voltage (being the voltage between the grid source electrode) of sampling switch is relevant with input signal, along with input signal changes and changes, make the conducting resistance of sampling switch also change with the signal variation, signal after causing sampling produces distortion, can not realize the high linearity sampling.
Summary of the invention
Technical matters to be solved by this invention provides a kind of simulating signal sample circuit and a kind of switched-capacitor circuit, can make circuit have high linearity, simultaneously, can realize handling being lower than in the circuit signal of minimum voltage.
In order to address the above problem, the invention discloses a kind of simulating signal sample circuit, comprise switch SW 4, SW5, capacitor C s, Cint and operational amplifier A 1, wherein:
Switch SW 4 is controlled by clock PH1, a terminated nodes n1, another termination reference voltage;
The in-phase input end of operational amplifier A 1 connects reference voltage, integrating capacitor Cint in parallel between inverting input and the output terminal;
Capacitor C s is connected between node n1 and the node n2 as sampling capacitance;
Described simulating signal sample circuit also comprises:
On-off circuit module U1 comprises conducting controlling sub U11, voltage constant submodule and PMOSFET pipe SW1; Described conducting controlling sub U11 is connected between node A and the input signal, and under clock PH1 control, g1 is to node A for output conducting control signal; The voltage constant submodule is connected between node A and the input signal, under described conducting control signal g1 control, produces constant voltage, voltage between the grid source electrode during as PMOSFET pipe SW1 conducting; The source electrode of PMOSFET pipe SW1 connects input signal, and grid meets node A, and drain electrode meets described node n2, is in the turn-on and turn-off two states under described conducting control signal g1 control.
On-off circuit module U2 comprises conducting controlling sub U21 and PMOSFET pipe SW3; Described conducting controlling sub U21 is connected between the grid and ground wire of PMOSFET pipe SW3, and under clock PH2 control, output conducting control signal g2 is to the grid of PMOSFET pipe SW3; The source ground line of PMOSFET pipe SW3, drain electrode meets described node n2, is in the turn-on and turn-off two states under described conducting control signal g2 control.
Preferably, described voltage constant submodule comprises PMOSFET pipe PM1, PM2, and wherein: the drain and gate of PMOSFET pipe PM2 all joins with the source electrode of PMOSFET pipe PM1, and source electrode and the input signal of PMOSFET pipe PM2 join; The drain and gate of PMOSFET pipe PM1 all joins with node A.
Preferably, described conducting controlling sub U11 comprises PMOSFET pipe PM3, capacitor C 1, C2, and PMOSFET pipe SW2 and a reverser, wherein: the input termination clock PH1 of reverser, output termination capacitor C 2; The drain electrode of another termination PMOSFET pipe PM3 of capacitor C 2; The source electrode of PMOSFET pipe PM3 and grid be ground wire all; One termination clock PH1 of capacitor C 1, another terminated nodes A; The drain electrode of switch SW 2 meets node A, and source electrode connects input signal, and grid is received between capacitor C 2 and the PMOSFET pipe PM3.
Wherein, described voltage constant submodule produces constant voltage, and voltage between the grid source electrode during as PMOSFET pipe SW1 conducting makes the conducting resistance of PMOSFET pipe SW1 constant.
Preferably, described conducting controlling sub U21 comprises capacitor C 3 and PMOSFET pipe PM4, wherein: a termination clock PH2 of capacitor C 3, the grid of another termination switch SW 3; The grid of PMOSFET pipe PM4 and source electrode be ground wire all, and drain electrode connects the grid of switch SW 3.
The present invention also provides a kind of switched-capacitor circuit, comprising:
The conducting control module is connected between node A and the input signal, is used under clock PH1 control, and g1 is to node A for output conducting control signal;
The voltage constant module is connected between node A and the input signal, under described conducting control signal g1 control, produces constant voltage, voltage between the grid source electrode during as PMOSFET pipe SW1 conducting;
PMOSFET manages SW1, and source electrode connects input signal, and grid meets node A, and drain electrode under described conducting control signal g1 control, is in the turn-on and turn-off two states as signal output part.
Preferably, described voltage constant module comprises PMOSFET pipe PM1, PM2, and wherein: the drain and gate of PMOSFET pipe PM2 all joins with the source electrode of PMOSFET pipe PM1, and source electrode and the input signal of PMOSFET pipe PM2 join; The drain and gate of PMOSFET pipe PM1 all joins with node A.
Preferably, described conducting control module comprises PMOSFET pipe PM3, capacitor C 1, C2, and PMOSFET pipe SW2 and a reverser, wherein: the input termination clock PH1 of reverser, output termination capacitor C 2; The drain electrode of another termination PMOSFET pipe PM3 of capacitor C 2; The source electrode of PMOSFET pipe PM3 and grid be ground wire all; One termination clock PH1 of capacitor C 1, another terminated nodes A; The drain electrode of switch SW 2 meets node A, and source electrode connects input signal, and grid is received between capacitor C 2 and the PMOSFET pipe PM3.
Wherein, described voltage constant module produces constant voltage, and voltage between the grid source electrode during as PMOSFET pipe SW1 conducting makes the conducting resistance of PMOSFET pipe SW1 constant.
Compared with prior art, the present invention has the following advantages:
At first, the present invention is by being provided with the voltage constant module, produce constant voltage, voltage between the grid source electrode when managing conducting as the PMOSFET that is used as switching tube, in the time of making the PMOSFET pipe be in conducting state, it is constant that voltage between grid and the source electrode keeps, the variation with input signal does not change, thereby the conducting resistance of PMOSFET pipe is not also changed with the variation of input signal, finally make the PMOSFET pipe have constant conducting resistance, make the distorted signals of process PMOSFET pipe very little, realized the high linearity sampling.
Secondly, the present invention is provided with the conducting control module, and described conducting control module is under the control of clock, and output conducting control signal makes the PMOSFET pipe be in the turn-on and turn-off state respectively in the corresponding time period; When the voltage of input signal was lower than in the circuit minimum voltage, the PMOSFET pipe also can normally, makes signal can continue output.
Therefore, the present invention can realize handling being lower than in the circuit input signal of minimum voltage, and, make circuit have very high linearity to Signal Processing.
Description of drawings
Fig. 1 is the circuit diagram of a kind of common simulating signal sample circuit in the prior art;
Fig. 2 is a kind of synoptic diagram that is lower than the simulating signal sample circuit of potential minimum in the circuit in the prior art;
Fig. 3 is the structural representation of a kind of sampling device for analog signal in the prior art;
Fig. 4 is the structural drawing of the embodiment of the invention one described a kind of simulating signal sample circuit;
Fig. 5 is the preferred version synoptic diagram of the embodiment of the invention one described a kind of simulating signal sample circuit;
Fig. 6 is the structural drawing of the embodiment of the invention two described a kind of switched-capacitor circuits;
Fig. 7 is the preferred version synoptic diagram of the embodiment of the invention two described a kind of switched-capacitor circuits.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the present invention is further detailed explanation below in conjunction with the drawings and specific embodiments.
Generally, low voltage signal sampled use the PMOS pipe, and the grid operating voltage of PMOS pipe is 0.When applied signal voltage is lower than 0 level, the grid of PMOS pipe and the voltage Vgs＞Vthp between the source electrode (Vthp is the threshold voltage of PMOS pipe, is negative value).At this moment, the PMOS pipe just can not conducting.So need be by the grid voltage that circuit produces the PMOS pipe be set, and described grid voltage will be lower than power cathode voltage, makes Vgs＜Vthp, just can make the conducting of PMOS pipe, realizes sampling.
For the signal after the sampling, basic demand is that distortion (distortion) is very little, promptly has high linearity.This just required in the sampling period, kept constant as the resistance value of the PMOS pipe of sampling switch.For the PMOS pipe, the voltage Vgs between conduction resistance value when being in conducting state and grid and the source electrode is inversely proportional to.In the existing sample circuit, the grid voltage of sampling switch is supply voltage (0 or VDD), be fixed value, and source voltage is input signal, is unfixed; Therefore, the voltage voltage between grid and the source electrode changes with signal, is an amount that changes with signal thereby make the conducting resistance of sampling switch.If realize the high linearity sampling, the gate voltage of sampling switch is also changed with signal, thereby make the grid of sampling switch and the voltage difference between the source electrode constant, irrelevant with input signal, sample thereby reach high linearity.
The present invention just is being based on above-mentioned principle and is proposing.
Embodiment one:
With reference to Fig. 4, show the structural drawing of the described a kind of simulating signal sample circuit of embodiment.
The described simulating signal sample circuit of present embodiment comprises switch SW 4, SW5, capacitor C s, Cint and operational amplifier A 1, wherein:
Switch SW 4 is controlled by clock PH1, a terminated nodes n1, another termination reference voltage;
The in-phase input end of operational amplifier A 1 connects reference voltage, integrating capacitor Cint in parallel between inverting input and the output terminal;
Capacitor C s is connected between node n1 and the node n2 as sampling capacitance;
Described simulating signal sample circuit also comprises:
On-off circuit module U41 comprises conducting controlling sub U411, voltage constant submodule U412 and PMOSFET pipe SW1; Described conducting controlling sub U411 is connected between node A and the input signal, and under clock PH1 control, g1 is to node A for output conducting control signal; Voltage constant submodule U412 is connected between node A and the input signal, under described conducting control signal g1 control, produces constant voltage, voltage between the grid source electrode during as PMOSFET pipe SW1 conducting; The source electrode of PMOSFET pipe SW1 connects input signal, and grid meets node A, and drain electrode meets described node n2, is in the turn-on and turn-off two states under described conducting control signal g1 control.
On-off circuit module U42 comprises conducting controlling sub U421 and PMOSFET pipe SW3; Described conducting controlling sub U421 is connected between the grid and ground wire of PMOSFET pipe SW3, and under clock PH2 control, output conducting control signal g2 is to the grid of PMOSFET pipe SW3; The source ground line of PMOSFET pipe SW3, drain electrode meets described node n2, is in the turn-on and turn-off two states under described conducting control signal g2 control.
For the described simulating signal sample circuit of present embodiment, be used for driving circuit clock signal also as shown in Figure 4.The principle of work of described circuit is as follows:
On-off circuit module U41 and switch SW 4 are controlled by clock PH1, and input signal inserts from on-off circuit module U41, and in the time period of clock PH1, on-off circuit module U41 outputs to node n2 to described input signal, and switch SW 4 is in conducting state; At this moment, if on-off circuit module U2PMOSFET pipe SW3 and switch SW 5 all are in off state, then the described input signal at node n2 place will be sampled on the capacitor C s.In another time period of clock PH1, on-off circuit module U41 does not export described input signal, and switch SW 4 is in off state, at this moment, if pipe SW3 of the PMOSFET among the on-off circuit module U42 and switch SW 5 all are in conducting state, then the last signal that obtains through over-sampling of capacitor C s can transmit to capacitor C int.
In the described process that input signal is sampled, the conducting controlling sub U411 among the on-off circuit module U41 is controlled by described clock PH1, at the output conducting of time period correspondingly control signal g1 to node A; When described conducting control signal g1 makes PMOSFET pipe SW1 be in conducting state, described voltage constant submodule U412 will produce a constant voltage between the source electrode of node A and PMOSFET pipe SW1, this voltage is the grid of PMOSFET pipe SW1 and the voltage between the source electrode, is the forward voltage of PMOSFET pipe SW1.PMOSFET pipe SW1 is when forward voltage is constant, and conducting resistance also will be constant value.
On-off circuit module U42 and switch SW 4 are controlled by clock PH2, in the time period of clock PH2, conducting controlling sub U421 among the on-off circuit module U42 sends control signal g2 turn-offs PMOSFET pipe SW3, and this moment, switch SW 5 was also turn-offed, and capacitor C int kept the level of a last time period.In another time period of clock PH2, described conducting controlling sub U421 sends control signal g2 and makes PMOSFET pipe SW3 conducting, the also conducting of switch SW 5 this moment, if pipe SW1 of the PMOSFET among the on-off circuit module U41 and switch SW 4 all are in off state, then the last signal that obtains through over-sampling of capacitor C s is transferred on the cint, realize integrating function, Vout=Cs/Cint*Vin.
By above-mentioned principle of work as can be seen, a kind of simulating signal sample circuit of the present invention, can realize being lower than the analog signal sampling of potential minimum in the circuit, and, because in the process of sampling, the forward voltage of sampling switch (PMOSFET manages SW1) is constant, makes that the conducting resistance of described sampling switch is constant, can not change, so can realize the high linearity sampling with the variation of input signal.
The following content of present embodiment is with the invention will be further described.
With reference to Fig. 5, be the preferred version synoptic diagram of the described a kind of simulating signal sample circuit of present embodiment.As shown in Figure 5:
Preferably, described voltage constant submodule U412 specifically comprises PMOSFET pipe PM1, PM2, wherein:
The drain and gate of PMOSFET pipe PM2 all joins with the source electrode of PMOSFET pipe PM1, and source electrode and the input signal of PMOSFET pipe PM2 join;
The drain and gate of PMOSFET pipe PM1 all joins with node A.
Usually, if metal-oxide-semiconductor grid and drain electrode are connected together, this connection connects diode, because its performance classes is similar to a diode.
Preferably, described conducting controlling sub U411 specifically comprises PMOSFET pipe PM3, capacitor C 1, C2, and PMOSFET pipe SW2 and a reverser, wherein:
The input termination clock PH1 of reverser, output termination capacitor C 2; The drain electrode of another termination PMOSFET pipe PM3 of capacitor C 2; The source electrode of PMOSFET pipe PM3 and grid be ground wire all;
One termination clock PH1 of capacitor C 1, another terminated nodes A; The drain electrode of switch SW 2 meets node A, and source electrode connects input signal, and grid is received between capacitor C 2 and the PMOSFET pipe PM3.
Preferably, described conducting controlling sub U421 specifically comprises capacitor C 3 and PMOSFET pipe PM4, wherein:
One termination clock PH2 of capacitor C 3, the grid of another termination switch SW 3;
The grid of PMOSFET pipe PM4 and source electrode be ground wire all, and drain electrode connects the grid of switch SW 3.
In the preferred version of described simulating signal sample circuit, PMOSFET pipe PM1, PM2 that the voltage constant submodule comprises, forward voltage Vgs=-2Vth (Vth is the threshold voltage of PMOSFET pipe) when being used to make sampling switch PMOSFET pipe SW1 be in conducting state is steady state value; Conducting controlling sub U411 and U421 are used to control PMOSFET pipe SW1 and PMOSFET pipe SW3 is in conducting or off state in the corresponding time period.Detailed process is as follows:
For on-off circuit module U42, the principle of work of described conducting controlling sub U421 is as follows:
Analyze for convenient, before initialization circuit was started working, the electric charge on the capacitor C 3 was 0.When clock PH2 becomes " 1 " by " 0 ", connect moment at the input end of clock of on-off circuit module U42, because the electric charge on the capacitor C 3 can not undergo mutation, so the voltage at node C place among Fig. 5 into " 1 ", be the grid voltage of PMOSFET pipe SW3, also become " 1 "; At this moment, PMOSFET pipe PM4 forward conduction.PMOSFET pipe PM4 forward conduction makes the voltage at node C place be clamped at the Vth place, thereby the voltage difference on the capacitor C 3 is (Vdd-Vth), and PMOSFET pipe SW3 is turned off.When clock PH2 becomes " 0 " again by " 1 ", connect moment into " 0 " at the input end of clock of on-off circuit module U42, do not undergo mutation for guaranteeing the electric charge on the capacitor C 3, the voltage at node C place can become (Vth-Vdd) so, this moment, PMOSFET pipe PM4 was anti-inclined to one side, can not conducting; And PMOSFET pipe SW3 conducting.
For on-off circuit module U41, the principle of work of described conducting controlling sub U411 and conducting controlling sub U421 are roughly the same.When clock PH1 becomes " 1 " by " 0 ", PMOSFET pipe SW2 conducting, the voltage at node A place among Fig. 5, promptly the grid voltage of PMOSFET pipe SW1 is Vin (n-1), and the voltage difference on the capacitor C 1 is (Vdd-Vin (n-1)).When clock PH1 became " 0 " by " 1 ", SW2 turn-offed.Become moment of " 0 " at clock PH1, the voltage at node A place becomes (Vin (n-1)-Vdd); At this moment, the PMOSFET pipe PM1 in the described voltage constant submodule, all positively biased conductings of PM2, the voltage at node A place finally is clamped at (Vin (n)-2Vth), PMOSFET pipe SW1 unlatching.And for PMOSFET pipe SW1, the voltage difference Vgs=Vin (n) between the grid at node A place and the source electrode of input signal end-2Vth-Vin (n)=-2Vth is a constant.
As can be seen, the forward voltage of PMOSFET pipe SW1 is a constant, and therefore, the conducting resistance of PMOSFET pipe SW1 is a constant also, is a constant that has nothing to do with signal.Thereby, can realize high linearity sampling to the input simulating signal.Simultaneously, because conducting controlling sub U411 and U421 can produce the forward voltage of PMOSFET pipe SW1 and PMOSFET pipe SW3, this circuit can be realized sampling to being lower than in the circuit signal of minimum voltage.
Embodiment two:
Present embodiment will be elaborated to a kind of switched-capacitor circuit of the present invention.
Switched-capacitor circuit uses MOS technology usually, technological process is fairly simple, and be easy to integrated on a large scale, so obtained faster development at electronic technology field, be widely used in the various integrated circuit, as filtering circuit, integrating circuit and sample circuit etc.At present, the accuracy requirement to signal Processing in the integrated circuit is more and more higher, and therefore, the requirement to switched-capacitor circuit in the practical application is also more and more higher, especially to the linearity requirement of circuit.Sometimes, also require also can handle to the input signal that is lower than minimum voltage in the circuit.
Switched-capacitor circuit of the present invention by the voltage constant module is set, can makes grid and magnitude of voltage source electrode between of switch when conducting constant, thereby make conducting resistance constant, makes entire circuit have higher linearity; By the conducting control module is set, described switched-capacitor circuit is handled to being lower than in the circuit input signal of minimum voltage.
With reference to Fig. 6, be the structural drawing of the described a kind of switched-capacitor circuit of present embodiment.Described switched-capacitor circuit comprises:
Conducting control module U61 is connected between node A and the input signal, is used under clock PH1 control, and g1 is to node A for output conducting control signal;
Voltage constant module U62 is connected between node A and the input signal, under described conducting control signal g1 control, produces constant voltage, voltage between the grid source electrode during as PMOSFET pipe SW1 conducting;
PMOSFET manages SW1, and source electrode connects input signal, and grid meets node A, and drain electrode under described conducting control signal g1 control, is in the turn-on and turn-off two states as signal output part.
Described conducting control module U61 is controlled by described clock PH1, and to node A, control PMOSFET manages the turn-on and turn-off of SW1 at the output conducting of time period correspondingly control signal g1; When PMOSFET pipe SW1 is in conducting state, described voltage constant module U62 produces a constant voltage between the source electrode of node A and PMOSFET pipe SW1, this voltage is the grid of PMOSFET pipe SW1 and the voltage between the source electrode, is the forward voltage of PMOSFET pipe SW1.PMOSFET pipe SW1 is when forward voltage is constant, and conducting resistance also will be constant value.
With reference to Fig. 7, be the preferred version synoptic diagram of the described a kind of switched-capacitor circuit of present embodiment.
Preferably, described voltage constant module U61 comprises PMOSFET pipe PM1, PM2, wherein:
The drain and gate of PMOSFET pipe PM2 all joins with the source electrode of PMOSFET pipe PM1, and source electrode and input signal join;
The drain and gate of PMOSFET pipe PM1 all joins with node A.
Preferably, described conducting control module U62 comprises PMOSFET pipe PM3, capacitor C 1, C2, and PMOSFET pipe SW2 and a reverser, wherein:
The input termination clock PH1 of reverser, output termination capacitor C 2; The drain electrode of another termination PMOSFET pipe PM3 of capacitor C 2; The source electrode of PMOSFET pipe PM3 and grid be ground wire all;
One termination clock PH1 of capacitor C 1, another terminated nodes A; The drain electrode of switch SW 2 meets node A, and source electrode connects input signal, and grid is received between capacitor C 2 and the PMOSFET pipe PM3.
In sum, a kind of simulating signal sample circuit and a kind of switched-capacitor circuit proposed by the invention, by the voltage constant module is set, can make the forward voltage and the input signal of the PMOSFET pipe that uses as switch irrelevant, do not change with input signal, thereby make the conducting resistance of described switch constant, can make circuit have the characteristics of high linearity; Simultaneously, by the conducting control module of described switch is set, circuit is handled to being lower than in the circuit input signal of potential minimum.
Among the embodiment in this instructions, what each embodiment stressed all is and the difference of other embodiment that identical similar part is mutually referring to getting final product between each embodiment.
More than to a kind of simulating signal sample circuit provided by the present invention and a kind of switched-capacitor circuit, be described in detail, used specific case herein principle of the present invention and embodiment are set forth, the explanation of above embodiment just is used for helping to understand method of the present invention and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present invention, the part that all can change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (9)
1, a kind of simulating signal sample circuit comprises switch SW 4, SW5, capacitor C s, Cint and operational amplifier A l, wherein:
Switch SW 4 is controlled by clock PH1, a terminated nodes n1, another termination reference voltage;
Switch SW 5 is controlled by clock PH2, a terminated nodes n1, the inverting input of another termination operational amplifier A l;
The in-phase input end of operational amplifier A l connects reference voltage, integrating capacitor Cint in parallel between inverting input and the output terminal;
Capacitor C s is connected between node n1 and the node n2 as sampling capacitance;
It is characterized in that described simulating signal sample circuit also comprises:
On-off circuit module U1 comprises conducting controlling sub U11, voltage constant submodule and PMOSFET pipe SW1; Described conducting controlling sub U11 is connected between node A and the input signal, and under clock PH1 control, g1 is to node A for output conducting control signal; The voltage constant submodule is connected between node A and the input signal, under described conducting control signal g1 control, produces constant voltage, voltage between the grid source electrode during as PMOSFET pipe SW1 conducting; The source electrode of PMOSFET pipe SW1 connects input signal, and grid meets node A, and drain electrode meets described node n2, is in the turn-on and turn-off two states under described conducting control signal g1 control.
On-off circuit module U2 comprises conducting controlling sub U21 and PMOSFET pipe SW3; Described conducting controlling sub U21 is connected between the grid and ground wire of PMOSFET pipe SW3, and under clock PH2 control, output conducting control signal g2 is to the grid of PMOSFET pipe SW3; The source ground line of PMOSFET pipe SW3, drain electrode meets described node n2, is in the turn-on and turn-off two states under described conducting control signal g2 control.
2, circuit according to claim 1 is characterized in that, described voltage constant submodule comprises PMOSFET pipe PM1, PM2, wherein:
The drain and gate of PMOSFET pipe PM2 all joins with the source electrode of PMOSFET pipe PM1, and source electrode and the input signal of PMOSFET pipe PM2 join;
The drain and gate of PMOSFET pipe PM1 all joins with node A.
3, circuit according to claim 1 is characterized in that, described conducting controlling sub U11 comprises PMOSFET pipe PM3, capacitor C 1, C2, and PMOSFET pipe SW2 and a reverser, wherein:
The input termination clock PH1 of reverser, output termination capacitor C 2; The drain electrode of another termination PMOSFET pipe PM3 of capacitor C 2; The source electrode of PMOSFET pipe PM3 and grid be ground wire all;
One termination clock PH1 of capacitor C 1, another terminated nodes A; The drain electrode of switch SW 2 meets node A, and source electrode connects input signal, and grid is received between capacitor C 2 and the PMOSFET pipe PM3.
4, circuit according to claim 1 and 2 is characterized in that, described voltage constant submodule produces constant voltage, and voltage between the grid source electrode during as PMOSFET pipe SW1 conducting makes the conducting resistance of PMOSFET pipe SW1 constant.
5, circuit according to claim 1 is characterized in that, described conducting controlling sub U21 comprises capacitor C 3 and PMOSFET pipe PM4, wherein:
One termination clock PH2 of capacitor C 3, the grid of another termination switch SW 3;
The grid of PMOSFET pipe PM4 and source electrode be ground wire all, and drain electrode connects the grid of switch SW 3.
6, a kind of switched-capacitor circuit is characterized in that, comprising:
The conducting control module is connected between node A and the input signal, is used under clock PH1 control, and g1 is to node A for output conducting control signal;
The voltage constant module is connected between node A and the input signal, under described conducting control signal g1 control, produces constant voltage, voltage between the grid source electrode during as PMOSFET pipe SW1 conducting;
PMOSFET manages SW1, and source electrode connects input signal, and grid meets node A, and drain electrode under described conducting control signal g1 control, is in the turn-on and turn-off two states as signal output part.
7, circuit according to claim 6 is characterized in that, described voltage constant module comprises PMOSFET pipe PM1, PM2, wherein:
The drain and gate of PMOSFET pipe PM2 all joins with the source electrode of PMOSFET pipe PM1, and source electrode and the input signal of PMOSFET pipe PM2 join;
The drain and gate of PMOSFET pipe PM1 all joins with node A.
8, circuit according to claim 6 is characterized in that, described conducting control module comprises PMOSFET pipe PM3, capacitor C 1, C2, and PMOSFET pipe SW2 and a reverser, wherein:
The input termination clock PH1 of reverser, output termination capacitor C 2; The drain electrode of another termination PMOSFET pipe PM3 of capacitor C 2; The source electrode of PMOSFET pipe PM3 and grid be ground wire all;
One termination clock PH1 of capacitor C 1, another terminated nodes A; The drain electrode of switch SW 2 meets node A, and source electrode connects input signal, and grid is received between capacitor C 2 and the PMOSFET pipe PM3.
According to claim 6 or 7 described circuit, it is characterized in that 9, described voltage constant module produces constant voltage, voltage between the grid source electrode during as PMOSFET pipe SW1 conducting makes the conducting resistance of PMOSFET pipe SW1 constant.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910087802.XA CN101587753B (en) | 2009-06-26 | 2009-06-26 | Analog signal sampling circuit and switch capacitance circuit |
| PCT/CN2010/074394 WO2010149060A1 (en) | 2009-06-26 | 2010-06-24 | Analog signal sampling circuit and switching circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910087802.XA CN101587753B (en) | 2009-06-26 | 2009-06-26 | Analog signal sampling circuit and switch capacitance circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101587753A true CN101587753A (en) | 2009-11-25 |
| CN101587753B CN101587753B (en) | 2014-12-31 |
Family
ID=41371942
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910087802.XA Active CN101587753B (en) | 2009-06-26 | 2009-06-26 | Analog signal sampling circuit and switch capacitance circuit |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN101587753B (en) |
| WO (1) | WO2010149060A1 (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010149060A1 (en) * | 2009-06-26 | 2010-12-29 | 北京中星微电子有限公司 | Analog signal sampling circuit and switching circuit |
| CN102185569A (en) * | 2011-04-07 | 2011-09-14 | 北京中星微电子有限公司 | Output stage circuit of D-class amplifier |
| CN103336159A (en) * | 2013-06-25 | 2013-10-02 | 西安电子科技大学 | Analog signal isolating circuit based on rotary capacitor |
| CN103684461A (en) * | 2012-09-21 | 2014-03-26 | 美国亚德诺半导体公司 | Sampling circuit, method of reducing distortion in sampling circuit, and analog to digital converter including such sampling circuit |
| CN102098034B (en) * | 2009-12-15 | 2014-07-30 | 北京中星微电子有限公司 | Bootstrap sampling circuit |
| CN105577137A (en) * | 2014-10-10 | 2016-05-11 | 瑞昱半导体股份有限公司 | Transmission line driving circuit used for automatic correction of impedance matching |
| CN108512536A (en) * | 2018-07-10 | 2018-09-07 | 上海艾为电子技术股份有限公司 | A kind of analog switch with constant conduction resistance |
| CN108696270A (en) * | 2018-05-24 | 2018-10-23 | 上海艾为电子技术股份有限公司 | A kind of analog switching circuit |
| CN110098836A (en) * | 2018-01-31 | 2019-08-06 | 长沙泰科阳微电子有限公司 | A kind of MDAC structure suitable for pipeline ADC |
| CN111953323A (en) * | 2020-07-28 | 2020-11-17 | 北京中星微电子有限公司 | Circuit for signal acquisition |
| WO2021143450A1 (en) * | 2020-01-14 | 2021-07-22 | 北京集创北方科技股份有限公司 | Switch control circuit, multiplexer switch circuit and control method for multiplexer switch control circuit |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6522187B1 (en) * | 2001-03-12 | 2003-02-18 | Linear Technology Corporation | CMOS switch with linearized gate capacitance |
| JP2006279452A (en) * | 2005-03-29 | 2006-10-12 | Sharp Corp | Sample holding circuit and semiconductor device |
| JP2007019861A (en) * | 2005-07-07 | 2007-01-25 | Matsushita Electric Ind Co Ltd | Analog switching circuit and constant current generation circuit |
| KR100693819B1 (en) * | 2005-07-14 | 2007-03-12 | 삼성전자주식회사 | Circuit and method of track and hold |
| CN100464504C (en) * | 2006-12-11 | 2009-02-25 | 北京中星微电子有限公司 | A sampling device for analog signal |
| CN101587753B (en) * | 2009-06-26 | 2014-12-31 | 北京中星微电子有限公司 | Analog signal sampling circuit and switch capacitance circuit |
-
2009
- 2009-06-26 CN CN200910087802.XA patent/CN101587753B/en active Active
-
2010
- 2010-06-24 WO PCT/CN2010/074394 patent/WO2010149060A1/en active Application Filing
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010149060A1 (en) * | 2009-06-26 | 2010-12-29 | 北京中星微电子有限公司 | Analog signal sampling circuit and switching circuit |
| CN102098034B (en) * | 2009-12-15 | 2014-07-30 | 北京中星微电子有限公司 | Bootstrap sampling circuit |
| CN102185569A (en) * | 2011-04-07 | 2011-09-14 | 北京中星微电子有限公司 | Output stage circuit of D-class amplifier |
| CN102185569B (en) * | 2011-04-07 | 2017-07-07 | 北京中星微电子有限公司 | A kind of output-stage circuit of class-D amplifier |
| CN103684461A (en) * | 2012-09-21 | 2014-03-26 | 美国亚德诺半导体公司 | Sampling circuit, method of reducing distortion in sampling circuit, and analog to digital converter including such sampling circuit |
| CN103684461B (en) * | 2012-09-21 | 2017-01-04 | 美国亚德诺半导体公司 | Sample circuit, down-samples the method for distortion in circuit and includes the analog-digital converter of this sample circuit |
| CN103336159A (en) * | 2013-06-25 | 2013-10-02 | 西安电子科技大学 | Analog signal isolating circuit based on rotary capacitor |
| CN105577137A (en) * | 2014-10-10 | 2016-05-11 | 瑞昱半导体股份有限公司 | Transmission line driving circuit used for automatic correction of impedance matching |
| CN105577137B (en) * | 2014-10-10 | 2019-05-10 | 瑞昱半导体股份有限公司 | For automatically correcting the transmission line drive circuit of impedance matching |
| CN110098836B (en) * | 2018-01-31 | 2024-03-01 | 长沙泰科阳微电子有限公司 | MDAC structure suitable for assembly line ADC |
| CN110098836A (en) * | 2018-01-31 | 2019-08-06 | 长沙泰科阳微电子有限公司 | A kind of MDAC structure suitable for pipeline ADC |
| CN108696270A (en) * | 2018-05-24 | 2018-10-23 | 上海艾为电子技术股份有限公司 | A kind of analog switching circuit |
| CN108512536A (en) * | 2018-07-10 | 2018-09-07 | 上海艾为电子技术股份有限公司 | A kind of analog switch with constant conduction resistance |
| CN108512536B (en) * | 2018-07-10 | 2023-11-28 | 上海艾为电子技术股份有限公司 | Analog switch with constant on-resistance |
| WO2021143450A1 (en) * | 2020-01-14 | 2021-07-22 | 北京集创北方科技股份有限公司 | Switch control circuit, multiplexer switch circuit and control method for multiplexer switch control circuit |
| CN111953323A (en) * | 2020-07-28 | 2020-11-17 | 北京中星微电子有限公司 | Circuit for signal acquisition |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2010149060A1 (en) | 2010-12-29 |
| CN101587753B (en) | 2014-12-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101587753A (en) | A kind of simulating signal sample circuit and a kind of switched-capacitor circuit | |
| CN101001085B (en) | Signal sampling hold circuit | |
| CN102412824B (en) | Differential reference voltage buffer | |
| CN101692603B (en) | Gain bootstrap type C class reverser and application circuit thereof | |
| CN102195637A (en) | Transmission gate and semiconductor device | |
| CN103997326A (en) | Bootstrap switching circuit with constant on resistance | |
| US20120007660A1 (en) | Bias Current Generator | |
| CN104158526A (en) | Method of improving linearity of MOS (Metal Oxide Semiconductor) transistor analog switch and MOS transistor analog switch circuit | |
| CN102420594B (en) | A kind of comparator | |
| CN1700598B (en) | Semiconductor integrated circuit | |
| CN103888093A (en) | Common-mode level reset circuit for differential signals | |
| CN101964648B (en) | High-threshold value voltage comparison circuit consisting of high-precision low-voltage comparator | |
| CN108199701B (en) | High-speed CMOS transmission gate switch circuit | |
| US8471630B2 (en) | Fast settling reference voltage buffer and method thereof | |
| CN109582073B (en) | Half-period capacitance ratio programmable band-gap reference circuit | |
| CN203747798U (en) | Sampling switch circuit | |
| CN101976949A (en) | Anti-interference rapid current sampling circuit based on difference structure | |
| CN103762985A (en) | Sampling hold circuit | |
| CN212785316U (en) | Bootstrap switch structure without influencing service life of device | |
| CN114374388A (en) | Two-step-established bootstrap sampling switch circuit and integrated circuit | |
| CN108448893B (en) | Dynamic slope compensation circuit based on duty ratio | |
| CN114696810A (en) | Grid bootstrap switch circuit and control method thereof | |
| CN102447466B (en) | IO (Input/Output) circuit for accurate pull-down current | |
| CN112636758B (en) | Sampling hold circuit used in snapshot type readout circuit | |
| CN107505976A (en) | A kind of fully differential voltage buffer circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20210128 Address after: No. 607, 6th floor, shining building, 35 Xueyuan Road, Haidian District, Beijing 100083 Patentee after: BEIJING VIMICRO ARTIFICIAL INTELLIGENCE CHIP TECHNOLOGY Co.,Ltd. Address before: 100083, Haidian District, Xueyuan Road, Beijing No. 35, Nanjing Ning building, 16 floor Patentee before: Vimicro Corp. |
|
| TR01 | Transfer of patent right |