CN114374388A

CN114374388A - Two-step-established bootstrap sampling switch circuit and integrated circuit

Info

Publication number: CN114374388A
Application number: CN202210070538.4A
Authority: CN
Inventors: 周雄; 杨本能
Original assignee: Xinjuwei Technology Chengdu Co ltd
Current assignee: Xinjuwei Technology Chengdu Co ltd
Priority date: 2022-01-21
Filing date: 2022-01-21
Publication date: 2022-04-19

Abstract

The application discloses a bootstrap sampling switch circuit and an integrated circuit which are established in a two-step mode, the bootstrap sampling switch circuit and the integrated circuit comprise a bootstrap circuit and a switch circuit which are connected with each other, the bootstrap circuit comprises an NMOS tube Ms2, the switch circuit comprises an NMOS tube Ms1, the source end of Ms1 is connected with an output end Vout, the source end of Ms2, the drain end of Ms1 and an input end Vin are connected; further includes a first transmission gate switch T1 and a second transmission gate switch T2; one end of the first transmission gate switch T1 is connected with the source end of Ms2, and the other end is connected with a common-mode voltage Vcm; one end of the second transmission gate switch T2 is connected with the source end of Ms2, and the other end is connected with the input end Vin and the drain end of Ms 1; and a timing control circuit for generating the first sampling signal Clks, the short pulse Clkvcm controlling the first transfer gate switch T1, and the second sampling signal Clkvin controlling the second transfer gate switch T2, respectively. According to the invention, two-step establishment is realized by additionally arranging the first transmission gate switch T1 and the second transmission gate switch T2, so that the common-mode voltage Vcm can be ensured to be stable in the sampling process, and the linearity can be ensured not to be influenced.

Description

Two-step-established bootstrap sampling switch circuit and integrated circuit

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a sampling switch circuit, and particularly relates to a two-step-established bootstrap sampling switch circuit and an integrated circuit.

Background

An analog-to-digital converter is a circuit or device that converts an input analog signal into a digital signal. In the analog-to-digital conversion process, firstly, the analog signal input to the analog-to-digital converter is sampled by using a sample/hold circuit. Specifically, the input analog signal is sampled in a sampling period of the sampling clock, and after the sampling is completed, the sampled analog signal is held until the next sampling period.

High-precision sampling networks typically require the use of highly linear bootstrap sampling switches, which enable high spurious-free dynamic range (SFDR) and very low Total Harmonic Distortion (THD) performance. A common bootstrap switch is shown in fig. 1, which operates as follows: when the sampling is not performed, the voltages at the upper and lower ends of the bootstrap capacitor Cboost are reset to VDD and VSS, respectively. With sampling on (Clks low), the Vx node is charged to Vin. Due to the principle of charge conservation, the voltage difference between the upper end and the lower end of the bootstrap capacitor Cboost is kept unchanged, the voltage Vy is changed along with Vx and is pulled up or lowered by Vin, and then Vy = VDD + Vin. For the NMOS sampling tube, Ms1, the bootstrap circuit makes its turn-on voltage Vg follow the source input signal Vs, and changes to the same extent, so that Vgs ≈ VDD is substantially constant (normally, the parasitic capacitance of some MOS transistors on the circuit node will make the voltage slightly smaller than VDD). The bootstrap voltage ensures that the equivalent impedance Ron, s1 of the MOS tube switch in the linear region does not change along with the change of the amplitude of the input signal, and the time constant of Ron, s1 Cs is relatively constant, so that the establishing precision is relatively consistent in the specified sampling time, and the linearity is high. This characteristic is significantly better than NMOS or PMOS switches alone, and also better than transmission gate switches (CMOS transmission gates).

When the bootstrap sampling switch and the preceding stage differential active module are cascaded, a simplified schematic diagram is shown in fig. 2. The preceding stage circuit here may be a differential amplifier, a buffer, a residual amplifier, an integrator, a filter, and the like. Bootstrap switches can guarantee a good linearity, but also introduce a problem that is often easily neglected. Since the Vx node (shown in detail in FIG. 1) needs to be charged from VSS to Vin each time a sample is taken, the input signal needs to provide a charging current, which causes Vop and Von to drop to VSS at the same time at the instant that the sampling switch MS2 is turned on (shown in detail in FIG. 3). In some low power consumption application scenarios, the driving capability of the front stage is not large, and this process will cause the common mode drop of (Vop + Von)/2 to be significant, reaching the volt level. This phenomenon has a significant effect on the common-mode stability of the front-stage differential circuit, from which the common-mode feedback circuit can recover over a long period of time. Common mode instability can cause a reduction in the linearity of the lower stage sampling circuit. In order to speed up the recovery process, the common mode is already stable at the next sampling, which requires a larger power consumption overhead on the relevant branches of the common mode feedback.

Disclosure of Invention

In order to solve the problems existing in the prior bootstrap switch technology, the application provides a bootstrap sampling switch circuit and an integrated circuit which are established in a two-step manner, and the bootstrap sampling switch circuit and the integrated circuit are used for pertinently solving the problem that the prior bootstrap switch causes obvious influence on the common mode stability of a preceding stage differential circuit, the common mode feedback circuit needs to be recovered from the state after a long time, and the problem that the linearity of a lower stage sampling circuit is reduced due to the common mode instability.

In order to achieve the above purpose, the core of the technical scheme adopted by the invention is that a bootstrap capacitor Cboost in a bootstrap circuit keeps a common-mode voltage Vcm stable in the reset-charging process, thereby ensuring that the linearity of a sampling circuit is not affected. Based on the conception of the invention, the invention adopts the specific technical scheme that:

a bootstrap sampling switch circuit established in a two-step mode comprises a bootstrap circuit and a switch circuit which are connected with each other, wherein the bootstrap circuit comprises an NMOS tube Ms2, the switch circuit comprises an NMOS tube Ms1, the source end of the Ms1 is connected with an output end Vout, and the source end of the Ms2, the drain end of the Ms1 and an input end Vin are connected; further includes a first transmission gate switch T1 and a second transmission gate switch T2; one end of the first transmission gate switch T1 is connected with the source end of Ms2, and the other end is connected with a common-mode voltage Vcm; one end of the second transmission gate switch T2 is connected with the source end of Ms2, and the other end is connected with the input end Vin and the drain end of Ms 1; and a timing control circuit for generating the first sampling signal Clks, the short pulse Clkvcm controlling the first transfer gate switch T1, and the second sampling signal Clkvin controlling the second transfer gate switch T2, respectively.

As one of the specific design schemes of the transmission gate T1/T2, the application provides one of the possible preferred schemes: the first transmission gate switch T1 and the second transmission gate switch T2 are arranged in the same structure and are respectively composed of a first NOT gate, a PMOS transistor M3 and an NMOS transistor M4; the source end of the NMOS transistor M4 is connected with the drain end of the PMOS transistor M3 to form a first connection end, the drain end of the NMOS transistor M4 is connected with the source end of the PMOS transistor M3 to form a second connection end, the gate end of the NMOS transistor M4 is simultaneously connected with the first NOT gate input end and the first sampling signal Clks, and the first NOT gate output end is connected with the gate end of the PMOS transistor.

In order to realize accurate sampling, preferably, the timing control circuit comprises a clock signal unit for generating an original clock Clk0, wherein Clk0 is connected with a second not gate and a third not gate in sequence, and the output end of the second not gate or the input end of the third not gate is used as Clks; original Clk0 and Clk0 are respectively used as two input ends of a NAND gate after being delayed by td, the output end of the NAND gate is sequentially connected with a fourth NOT gate, a fifth NOT gate and a sixth NOT gate, and the output end of the sixth NOT gate is used as Clkvm; and the output end of the third not gate, the output end of the fourth not gate or the input end of the fifth not gate are used as two input ends of the exclusive-or gate, and are sequentially connected with the seventh not gate and the eighth not gate, and the output end of the eighth not gate is used as a second sampling signal Clkvin.

An integrated circuit comprising all circuits combined with the above two-step built bootstrap sampling switch circuit.

Has the advantages that:

according to the invention, two-step establishment is realized by additionally arranging the first transmission gate switch T1 and the second transmission gate switch T2, the voltage is established in the first step by the common-mode voltage Vcm, and then the input voltage Vin/Vip is established, so that when Ms2 is switched on, the output voltage Von/Vop cannot drop to VSS at the same time to lower the output common-mode voltage Vcm, thereby ensuring that the common-mode voltage Vcm is kept stable in the sampling process and ensuring that the linearity is not influenced.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without inventive exercise.

Fig. 1 is a conventional bootstrap sampling switch (bootstrap switch) circuit.

Fig. 2 is a schematic diagram of a sampling circuit for a differential active module.

Fig. 3 is an output waveform of fig. 2.

Fig. 4 is a circuit diagram of a bootstrapped sampling switch of the present invention.

Fig. 5 is the timing control circuit of fig. 4.

Fig. 6 is a control timing chart of the present invention.

FIG. 7 is a simulation waveform for nodes Vx and Vy in FIG. 4.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The preferred embodiment:

as shown in fig. 4, the two-step established bootstrap sampling switch circuit includes a bootstrap circuit and a switch circuit connected with each other, the bootstrap circuit includes an NMOS transistor Ms2, the switch circuit includes an NMOS transistor Ms1, a source terminal of Ms1 is connected to an output terminal Vout, a source terminal of Ms2, a drain terminal of Ms1 is connected to an input terminal Vin; further includes a first transmission gate switch T1 and a second transmission gate switch T2; one end of the first transmission gate switch T1 is connected with the source end of Ms2, and the other end is connected with a common-mode voltage Vcm; one end of the second transmission gate switch T2 is connected with the source end of Ms2, and the other end is connected with the input end Vin and the drain end of Ms 1; and a timing control circuit for generating the first sampling signal Clks, the short pulse Clkvcm controlling the first transfer gate switch T1, and the second sampling signal Clkvin controlling the second transfer gate switch T2, respectively. In this embodiment, the first pass gate switch T1 and the second pass gate switch T2 are configured in the same structure, and each of the first pass gate switch T1 and the second pass gate switch T2 is composed of a first not gate, a PMOS transistor M3, and an NMOS transistor M4; the source end of the NMOS transistor M4 is connected with the drain end of the PMOS transistor M3 to form a first connection end, the drain end of the NMOS transistor M4 is connected with the source end of the PMOS transistor M3 to form a second connection end, the gate end of the NMOS transistor M4 is simultaneously connected with the first NOT gate input end and the first sampling signal Clks, and the first NOT gate output end is connected with the gate end of the PMOS transistor.

The timing control circuit comprises a clock signal unit for generating an original clock Clk0, wherein the Clk0 is connected with a second NOT gate and a third NOT gate in sequence, and the output end of the second NOT gate or the input end of the third NOT gate is used as Clks; original Clk0 and Clk0 are respectively used as two input ends of a NAND gate after being delayed by td, the output end of the NAND gate is sequentially connected with a fourth NOT gate, a fifth NOT gate and a sixth NOT gate, and the output end of the sixth NOT gate is used as Clkvm; and the output end of the third not gate, the output end of the fourth not gate or the input end of the fifth not gate are used as two input ends of the exclusive-or gate, and are sequentially connected with the seventh not gate and the eighth not gate, and the output end of the eighth not gate is used as a second sampling signal Clkvin.

The working process and principle are as follows:

the Vx node is not directly connected to Vin at the beginning as in the prior bootstrap sampling switch, but is controlled by Clkvcm to be connected to a common-mode voltage Vcm first, and the Vx node is charged from VSS to the common-mode voltage Vcm, so that the required charging current is provided to the Vx node through Vcm, and therefore, the charging of the bootstrap capacitor Cboost is not from Vin/Vip as the prior bootstrap sampling switch. After a delay td the charging is complete, when the second transmission gate switch T2 is controlled by the second sampling signal Clkvin to be connected to Vin. In this process, T1 and Ms2, T2 and Ms2 are all in series relationship.

Compared with the existing bootstrap sampling switch circuit, the bootstrap sampling switch circuit has the following other differences: the conventional bootstrapped sampling switch is completed by only one clock phase, but the present embodiment is established by two steps, and a special dedicated phase control timing is required, as shown in fig. 5 and 6. It should be noted that the short pulse width td of Clkvcm is not a constant value, and can be adaptively adjusted according to different sampling speeds according to practical application. As shown in fig. 7, showing the waveforms of two key nodes Vx and Vy, it can be seen that Vx builds first from a voltage close to Vss to Vcm (VDD =3V, Vcm =1.5V in this embodiment), and then rises to Vin; similarly, Vy is also a waveform that is built up in two steps to the last VDD + Vin.

By using the bootstrap sampling circuit of this embodiment, the jitter of the output terminal of the amplifier can be reduced from the common mode jitter of about 1V in the prior art to the common mode jitter of tens mV, and the common mode problem caused by charging and discharging of the sampling switch circuit is basically eliminated.

The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A bootstrap sampling switch circuit established in two steps comprises a bootstrap circuit and a switch circuit which are connected with each other, wherein the bootstrap circuit comprises an NMOS tube Ms2, the switch circuit comprises an NMOS tube Ms1, the source end of Ms1 is connected with an output end Vout, the source end of Ms2, the drain end of Ms1 and an input end Vin are connected, and the bootstrap sampling switch circuit is characterized in that:

further includes a first transmission gate switch T1 and a second transmission gate switch T2; one end of the first transmission gate switch T1 is connected with the source end of Ms2, and the other end is connected with a common-mode voltage Vcm; one end of the second transmission gate switch T2 is connected with the source end of Ms2, and the other end is connected with the input end Vin and the drain end of Ms 1;

and a timing control circuit for generating the first sampling signal Clks, the short pulse Clkvcm controlling the first transfer gate switch T1, and the second sampling signal Clkvin controlling the second transfer gate switch T2, respectively.

2. The two-step setup bootstrapped sample switch circuit of claim 1, wherein: the first transmission gate switch T1 and the second transmission gate switch T2 are arranged in the same structure and are respectively composed of a first NOT gate, a PMOS transistor M3 and an NMOS transistor M4; the source end of the NMOS transistor M4 is connected with the drain end of the PMOS transistor M3 to form a first connection end, the drain end of the NMOS transistor M4 is connected with the source end of the PMOS transistor M3 to form a second connection end, the gate end of the NMOS transistor M4 is simultaneously connected with the first NOT gate input end and the first sampling signal Clks, and the first NOT gate output end is connected with the gate end of the PMOS transistor.

3. The two-step setup bootstrapped sample switch circuit of claim 1, wherein: the timing control circuit comprises a clock signal unit for generating an original clock Clk0, wherein the Clk0 is connected with a second NOT gate and a third NOT gate in sequence, and the output end of the second NOT gate or the input end of the third NOT gate is used as Clks; original Clk0 and Clk0 are respectively used as two input ends of a NAND gate after being delayed by td, the output end of the NAND gate is sequentially connected with a fourth NOT gate, a fifth NOT gate and a sixth NOT gate, and the output end of the sixth NOT gate is used as Clkvm; and the output end of the third not gate, the output end of the fourth not gate or the input end of the fifth not gate are used as two input ends of the exclusive-or gate, and are sequentially connected with the seventh not gate and the eighth not gate, and the output end of the eighth not gate is used as a second sampling signal Clkvin.

4. An integrated circuit, characterized in that: a bootstrapped sample switch circuit including the two-step setup of any of claims 1-3.