CN110943726A - Multi-channel multi-stage parallel ultra-high-speed sample hold circuit - Google Patents
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Abstract
The invention relates to a multi-channel multi-stage parallel superspeed sampling and holding circuit which is characterized by comprising m two-stage sampling circuits which are connected in parallel, wherein each two-stage sampling circuit comprises a first-stage sampling and holding circuit, a buffer and a second-stage sampling and holding circuit, and the first-stage sampling and holding circuit carries out primary sampling on an input signal according to a first-stage clock signal to generate a first-stage sampling signal; n buffers and second-stage sample-and-hold circuits connected in series are connected to the output end of the first-stage sample-and-hold circuit in parallel; the second-stage sampling holding circuit carries out second sampling on the first-stage sampling signal according to a second-stage clock signal to generate a second-stage sampling signal, and the second-stage sampling signal is transmitted to the analog-to-digital converter at the rear end; the first-stage sample-and-hold circuit and the second-stage sample-and-hold circuit realize the interleaving of m multiplied by n channels, wherein m and n are integers which are more than or equal to 2. The circuit of the invention greatly reduces the mismatch degree between channels and improves the sampling speed and precision.
Description
Technical Field
The invention belongs to the technical field of analog-to-digital converters, and particularly relates to a multi-channel multi-level parallel ultrahigh-speed sampling and holding circuit.
Background
An analog-to-digital converter is a tool for converting an analog signal into a digital signal, is used as an interface between an analog technology and a digital technology, is widely applied to the fields of industrial control, radar, communication, consumer electronics and the like, and plays an important role in information technology. With the continuous improvement of integrated circuit manufacturing processes and the introduction of new materials, digital signal processing technology is continuously advancing, and thus higher requirements are put on the speed of analog-to-digital converters.
For example, in an interface for optical communication or the like, an ultra-high-speed analog-to-digital converter is required to process an obtained analog signal, and one of the most common methods for increasing the speed of the analog-to-digital converter is to use a plurality of analog-to-digital converters in parallel. The structure is called a Time-interleaved analog-to-digital converter (Time-interleaved ADC), and a multi-channel Time-domain interleaved analog-to-digital converter is widely studied as the most promising ultra-high-speed analog-to-digital converter.
The sample-and-hold circuit, as the most front-end module of the time-domain interleaved analog-to-digital converter, often has a precision that determines the precision of the whole analog-to-digital converter, and in addition, the highest sampling rate of the analog-to-digital converter is determined not only by the operating speed of the comparator but also by the speed of the sample-and-hold circuit, so it is very important to design a sample-and-hold circuit that can reduce the influence of clock skew caused by time-domain interleaving and has high precision.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a multi-channel multi-stage parallel superspeed sample-and-hold circuit. The technical problem to be solved by the invention is realized by the following technical scheme:
the invention provides a multi-channel multi-stage parallel superspeed sampling and holding circuit, which comprises m two-stage sampling circuits connected in parallel, wherein the two-stage sampling circuits comprise a first-stage sampling and holding circuit, a buffer and a second-stage sampling and holding circuit,
the first-stage sampling and holding circuit is used for sampling an input signal for one time according to a first-stage clock signal to generate a first-stage sampling signal;
the n buffers and the second-stage sample-and-hold circuit which are connected in series are connected to the output end of the first-stage sample-and-hold circuit in parallel;
the second-stage sampling holding circuit carries out second sampling on the first-stage sampling signal according to a second-stage clock signal to generate a second-stage sampling signal, and the second-stage sampling signal is transmitted to an analog-to-digital converter at the rear end;
the first-stage sample-and-hold circuit and the second-stage sample-and-hold circuit realize interleaving of m multiplied by n channels, wherein m and n are integers which are more than or equal to 2.
In one embodiment of the invention, the phase difference between the first-stage clock signals of the adjacent parallel first-stage sample-and-hold circuits is the reciprocal of the sampling frequency of the multichannel multistage parallel superspeed sample-and-hold circuit; and the phase difference between the second-stage clock signals of the adjacent parallel second-stage sampling and holding circuits is the reciprocal of the frequency of the first-stage clock signal of the preceding first-stage sampling and holding circuit.
In one embodiment of the present invention, the first stage sample-and-hold circuit includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, and a sixth MOS transistor, wherein,
the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the fifth MOS transistor and the sixth MOS transistor are NMOS transistors;
the drain electrode of the first MOS tube is used as a first input end of the first-stage sample-and-hold circuit, the source electrode of the first MOS tube is connected with the drain electrode of the second MOS tube, and the grid electrode of the first MOS tube inputs a first signal of the first-stage clock signal corresponding to the differential signal;
the drain electrode of the second MOS tube is connected with the source electrode of the second MOS tube, the source electrode of the second MOS tube is used as the first output end of the first-stage sample-and-hold circuit, and the grid electrode of the second MOS tube inputs a second signal of the first-stage clock signal corresponding to the differential signal;
the drain electrode of the third MOS tube is used as the second input end of the first-stage sample-and-hold circuit, the source electrode of the third MOS tube is connected with the drain electrode of the fourth MOS tube, and the grid electrode of the third MOS tube inputs the first signal of the first-stage clock signal corresponding to the differential signal;
the drain electrode of the fourth MOS tube is connected with the source electrode of the fourth MOS tube, the source electrode of the fourth MOS tube is used as the second output end of the first-stage sample-and-hold circuit, and the grid electrode of the fourth MOS tube inputs the corresponding differential signal of the first-stage clock signal; second signal of
The source electrode of the fifth MOS tube is connected with the drain electrode of the first MOS tube, the drain electrode of the fifth MOS tube is connected with the source electrode of the fourth MOS tube, and the grid electrode of the fifth MOS tube is connected with the grounding end;
and the source electrode of the sixth MOS tube is connected with the drain electrode of the third MOS tube, the drain electrode of the sixth MOS tube is connected with the source electrode of the second MOS tube, and the grid electrode of the sixth MOS tube is connected with the grounding end.
In one embodiment of the present invention, the input end of the buffer is connected to the corresponding output end of the first stage sample-and-hold circuit, the buffer includes a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, a first resistor, a second resistor, a third resistor, a first inductor, and a second inductor, wherein,
the seventh MOS transistor, the eighth MOS transistor, the ninth MOS transistor, and the tenth MOS transistor are PMOS transistors;
the source electrode of the seventh MOS tube is connected with a power supply voltage end, the drain electrode of the seventh MOS tube is connected with the source electrode of the ninth MOS tube, and the grid electrode of the seventh MOS tube is connected with a bias voltage end;
the source electrode of the eighth MOS tube is connected with the power supply voltage end, the drain electrode of the eighth MOS tube is connected with the source electrode of the tenth MOS tube, and the grid electrode of the eighth MOS tube is connected with the bias voltage end;
a grid electrode of the ninth MOS tube is used as a first input end of the buffer, and a drain electrode of the ninth MOS tube is used as a first output end of the buffer;
a grid electrode of the tenth MOS tube is used as a second input end of the buffer, and a drain electrode of the tenth MOS tube is used as a second output end of the buffer;
the first resistor is connected between the drain electrode of the seventh MOS tube and the drain electrode of the eighth MOS tube in series;
the second resistor and the first inductor are sequentially connected in series between the drain electrode of the ninth MOS tube and the grounding end;
the third resistor and the second inductor are sequentially connected in series between the drain of the tenth MOS transistor and the ground terminal.
In one embodiment of the invention, the second stage sample and hold circuit comprises a first sampling branch and a second sampling branch, wherein,
the input end of the first sampling branch circuit is connected with the first output end of the corresponding buffer, and the output end of the first sampling branch circuit is used as the first output end of the second-stage sampling and holding circuit;
the input end of the second sampling branch circuit is connected with the second output end of the corresponding buffer, and the output end of the second sampling branch circuit is used as the second output end of the second-stage sampling and holding circuit;
the circuit structures of the first sampling branch and the second sampling branch are the same.
In an embodiment of the present invention, the first sampling branch includes an eleventh MOS transistor, a twelfth MOS transistor, a thirteenth MOS transistor, a fourteenth MOS transistor, a fifteenth MOS transistor, a sixteenth MOS transistor, a seventeenth MOS transistor, an eighteenth MOS transistor, a nineteenth MOS transistor, a twentieth MOS transistor, a twenty-first MOS transistor, a twenty-second MOS transistor, a first capacitor, a second capacitor, and a third capacitor,
the fourteenth MOS tube and the sixteenth MOS tube are both PMOS tubes, and the rest are NMOS tubes;
the drain electrode of the eleventh MOS tube, the drain electrode of the twelfth MOS tube, the drain electrode of the thirteenth MOS tube, the source electrode of the fourteenth MOS tube and the grid electrode of the nineteenth MOS tube are all connected with a power supply voltage end;
the source electrode of the eleventh MOS tube is respectively connected with the grid electrode of the twelfth MOS tube and the grid electrode of the thirteenth MOS tube, the grid electrode of the eleventh MOS tube is connected with the source electrode of the twelfth MOS tube, and the source electrode of the thirteenth MOS tube is connected with the source electrode of the sixteenth MOS tube;
a grid electrode of the fourteenth MOS tube inputs a first signal of the second-stage clock signal corresponding to the differential signal, and a drain electrode of the fourteenth MOS tube is connected with a drain electrode of the fifteenth MOS tube, a grid electrode of the sixteenth MOS tube and a drain electrode of the seventeenth MOS tube respectively;
a grid electrode of the fifteenth MOS tube inputs a first signal of a corresponding differential signal of the second-level clock signal, a source electrode of the fifteenth MOS tube is respectively connected with a drain electrode of the twelfth MOS tube, a source electrode of the seventeenth MOS tube and a source electrode of the eighteenth MOS tube, and a drain electrode of the fifteenth MOS tube is respectively connected with a grid electrode of the sixteenth MOS tube and a drain electrode of the seventeenth MOS tube;
the grid electrode of the sixteenth MOS tube is connected with the drain electrode of the seventeenth MOS tube, and the drain electrode of the sixteenth MOS tube is respectively connected with the source electrode of the nineteenth MOS tube and the grid electrode of the twenty-first MOS tube;
the source electrode of the seventeenth MOS tube is connected with the source electrode of the eighteenth MOS tube, and the grid electrodes of the seventeenth MOS tube and the twenty-first MOS tube are respectively connected with the grid electrode of the eighteenth MOS tube and the grid electrode of the twenty-first MOS tube;
the source electrode of the eighteenth MOS tube is connected with the drain electrode of the twelfth MOS tube, the drain electrode of the eighteenth MOS tube is connected with the source electrode of the twenty-first MOS tube, and the drain electrode of the eighteenth MOS tube is used as the input end of the first sampling branch;
the drain electrode of the nineteenth MOS tube is connected with the source electrode of the twentieth MOS tube, the grid electrode of the twentieth MOS tube inputs the second signal of the corresponding differential signal of the second-level clock signal, and the drain electrode is connected with the ground terminal;
the drain of the twenty-first MOS transistor is used as the output end of the first sampling branch, the gate of the twenty-second MOS transistor inputs a second signal of the second-level clock signal, which corresponds to the differential signal, and the source is connected to the ground terminal;
the first capacitor is connected in series between the source electrode of the eleventh MOS transistor and the gate electrode of the twenty-second MOS transistor, the upper electrode plate of the second capacitor is connected with the source electrode of the twelfth MOS transistor, the lower electrode plate inputs a first signal of the second-stage clock signal corresponding to the differential signal, and the third capacitor is connected in series between the source electrode of the thirteenth MOS transistor and the drain electrode of the twenty-second MOS transistor.
Compared with the prior art, the invention has the beneficial effects that:
compared with the traditional sampling mode, the multi-channel multi-stage parallel superspeed sample-and-hold circuit can greatly reduce the mismatch degree among channels and improve the sampling speed and precision.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented in accordance with the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more clearly understood, the following preferred embodiments are described in detail with reference to the accompanying drawings.
Drawings
FIG. 1 is a block diagram of a multi-channel multi-stage parallel superspeed sample-and-hold circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a multi-channel multi-stage parallel superspeed sample-and-hold circuit according to an embodiment of the present invention;
FIG. 3 is a timing diagram of a multi-channel multi-stage parallel superspeed sample-and-hold circuit according to an embodiment of the present invention;
FIG. 4 is a circuit diagram of a first stage sample and hold circuit provided by an embodiment of the present invention;
FIG. 5 is a circuit diagram of a buffer provided by an embodiment of the present invention;
fig. 6 is a circuit diagram of a second stage sample-and-hold circuit according to an embodiment of the present invention.
Detailed Description
To further illustrate the technical means and effects of the present invention for achieving the predetermined objects, a multi-channel multi-stage parallel superspeed sample-and-hold circuit according to the present invention will be described in detail with reference to the accompanying drawings and the detailed description.
The foregoing and other technical matters, features and effects of the present invention will be apparent from the following detailed description of the embodiments, which is to be read in connection with the accompanying drawings. The technical means and effects of the present invention adopted to achieve the predetermined purpose can be more deeply and specifically understood through the description of the specific embodiments, however, the attached drawings are provided for reference and description only and are not used for limiting the technical scheme of the present invention.
Example one
Referring to fig. 1, fig. 1 is a block diagram of a multi-channel multi-stage parallel superspeed sample-and-hold circuit according to an embodiment of the present invention, and as shown in the figure, the multi-channel multi-stage parallel superspeed sample-and-hold circuit according to the embodiment of the present invention includes m two-stage sample-and-hold circuits 100 connected in parallel, each two-stage sample-and-hold circuit 100 includes a first-stage sample-and-hold circuit 1, a buffer 2, and a second-stage sample-and-hold circuit 3, where the first-stage sample-and-hold circuit 1 is configured to sample an input signal once according to a first; the n buffers 2 and the second-stage sample-and-hold circuit 3 which are connected in series are connected in parallel to the output end of the first-stage sample-and-hold circuit 1; the second-stage sampling holding circuit 3 performs secondary sampling on the first-stage sampling signal according to a second-stage clock signal to generate a second-stage sampling signal, and the second-stage sampling signal is transmitted to an analog-to-digital converter at the rear end; the first stage sample hold circuit 1 and the second stage sample hold circuit 3 realize the interleaving of m multiplied by n channels, wherein m and n are integers which are more than or equal to 2.
Referring to fig. 2 in combination, fig. 2 is a schematic diagram of a multichannel multi-stage parallel superspeed sample-and-hold circuit according to an embodiment of the present invention, where Si (i ═ 1 to m) respectively represents m first-stage sample-and-hold circuits 1, Sij (i ═ 1 to m, j ═ 1 to n) respectively represents m × n second-stage sample-and-hold circuits 3, n second-stage sample-and-hold circuits 3 are connected in parallel after each first-stage sample-and-hold circuit 1, and a buffer 2 is connected in series between the first-stage sample-and-hold circuit 1 and the second-stage sample-and-hold circuits 3. cki (i is 1 to m) represents first-stage clock signals corresponding to m first-stage sample-and-hold circuits 1, respectively, and ckij (i is 1 to m, j is 1 to n) represents second-stage clock signals corresponding to m × n second-stage sample-and-hold circuits 3, respectively. The multichannel multistage parallel superspeed sampling and holding circuit of the embodiment adopts an m multiplied by n two-stage sampling and holding circuit structure, the first stage adopts m superspeed single-tube sampling and holding switches, the second stage adopts parallel m multiplied by n buffers and m multiplied by n high-linearity bootstrap switches, and output voltage can be directly connected with an analog-to-digital converter connected with the rear end for use.
Further, in the present embodiment, the phase difference between the first-stage clock signals of the adjacent parallel first-stage sample-and-hold circuits 1 is the inverse of the sampling frequency of the multi-channel multi-stage parallel ultra-high speed sample-and-hold circuit; the phase difference between the second-stage clock signals of the adjacent parallel second-stage sample-and-hold circuits 3 is the reciprocal of the frequency of the first-stage clock signal of the preceding first-stage sample-and-hold circuit 1. Referring to fig. 3, fig. 3 is a timing diagram of a multi-channel multi-stage parallel ultra high speed sample-and-hold circuit according to an embodiment of the present invention, as shown in the figure, m first-stage sample-and-hold circuits 1 sample input signals first, and cki (i ═ 1 to m) has a strict phase difference therebetween, and the phase difference between two adjacent clock signals is the inverse of the sampling frequency of the multi-channel multi-stage parallel ultra high speed sample-and-hold circuit. N buffers 2 are connected in parallel behind each first-stage sample-and-hold circuit 1, one second-stage sample-and-hold circuit 3 is connected behind each buffer 2, the second-stage clock signals of the n second-stage sample-and-hold circuits 2 have strict phase difference, and the phase difference t between two adjacent clock signals between ck1j (j is 1 to n) is 1/ck 1. The phase difference of the reciprocal of the sampling frequency of the multi-channel multi-stage parallel ultra-high speed sample hold circuit is formed between m multiplied by n channels of the whole multi-channel multi-stage parallel ultra-high speed sample hold circuit, so that the time domain interleaving function is realized, and the sampling speed is improved. And m first-stage sample hold circuits 1 can reduce possible clock deviations of the system to m, so that the precision is greatly improved.
Further, a floor circuit structure of the channel multistage parallel superspeed sample-and-hold circuit of the present embodiment will be specifically described. Referring to fig. 4, fig. 4 is a circuit diagram of a first-stage sample-and-hold circuit provided in the embodiment of the present invention, as shown in the figure, the first-stage sample-and-hold circuit 1 of the embodiment includes a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, and a sixth MOS transistor M6, wherein the first MOS transistor M1, the second MOS transistor M2, the third MOS transistor M3, the fourth MOS transistor M4, the fifth MOS transistor M5, and the sixth MOS transistor M6 are all NMOS transistors; the drain of the first MOS transistor M1 is used as the first input end of the first stage sample-and-hold circuit 1, the source is connected to the drain of the second MOS transistor M2, and the gate inputs the first signal of the first stage clock signal corresponding to the differential signal; the drain of the second MOS transistor M2 is connected to the source thereof, the source is used as the first output end of the first stage sample-and-hold circuit 1, and the gate inputs the second signal of the corresponding differential signal of the first stage clock signal; the drain of the third MOS transistor M3 is used as the second input end of the first stage sample-and-hold circuit 1, the source is connected to the drain of the fourth MOS transistor M4, and the gate inputs the first signal of the first stage clock signal corresponding to the differential signal; the drain of the fourth MOS transistor M4 is connected to the source thereof, the source is used as the second output terminal of the first stage sample-and-hold circuit 1, and the gate inputs the second signal of the first stage clock signal corresponding to the differential signal; the source electrode of the fifth MOS transistor M5 is connected to the drain electrode of the first MOS transistor M1, the drain electrode is connected to the source electrode of the fourth MOS transistor M4, and the gate electrode is connected to the ground terminal GND; the source of the sixth MOS transistor M6 is connected to the drain of the third MOS transistor M3, the drain is connected to the source of the second MOS transistor M2, and the gate is connected to the ground GND.
In the figure, Vin and Vip are input signals of a sample-and-hold circuit, CLK1 is a first signal of a differential signal corresponding to a first-stage clock signal, CLKN1 is a second signal of the differential signal corresponding to the first-stage clock signal, CLK1 corresponds to the clock signal cki (i is 1 to m) in fig. 3, and differential signals Von1 and Vop1 are first-stage sample signals. When the CLK1 is at high level, the first MOS transistor M1 and the third MOS transistor M3 are turned on, and the first-stage sampling signals Von1 and Vop1 follow the voltage values of the input signals Vip and Vin. When the CLK1 is at low level, the first MOS transistor M1 and the third MOS transistor M3 are turned off, and the voltage values of the first-stage sampling signals Von1 and Vop1 are held in the parasitic capacitors (not shown) at the input ends of the following buffers. The redundant second MOS transistor M2 and the fourth MOS transistor M4 can reduce the influence of clock feed-through, and the fifth MOS transistor M5 and the sixth MOS transistor M6 with grounded gate terminals can eliminate signal feed-through.
Further, referring to fig. 5, fig. 5 is a circuit diagram of a buffer according to an embodiment of the present invention, as shown in the figure, a first input terminal of a buffer 2 is connected to a first output terminal of a corresponding first-stage sample-and-hold circuit 1, and a second input terminal of the buffer 2 is connected to a second output terminal of the corresponding first-stage sample-and-hold circuit 1. The buffer 2 comprises a seventh MOS transistor M7, an eighth MOS transistor M8, a ninth MOS transistor M9, a tenth MOS transistor M10, a first resistor R1, a second resistor R2, a third resistor R3, a first inductor L1 and a second inductor L2, wherein the seventh MOS transistor M7, the eighth MOS transistor M8, the ninth MOS transistor M9 and the tenth MOS transistor M10 are PMOS transistors; the source electrode of the seventh MOS tube M7 is connected with a power supply voltage end VDD, the drain electrode of the seventh MOS tube M7 is connected with the source electrode of the ninth MOS tube M9, and the grid electrode of the seventh MOS tube M7 is connected with a bias voltage end Vb; the source electrode of the eighth MOS transistor M8 is connected with a power supply voltage end VDD, the drain electrode is connected with the source electrode of the tenth MOS transistor M10, and the grid electrode is connected with a bias voltage end Vb; the gate of the ninth MOS transistor M9 is used as the first input end of the buffer 2, and the drain is used as the first output end of the buffer 2; the gate of the tenth MOS transistor M10 is used as the second input terminal of the buffer 2, and the drain is used as the second output terminal of the buffer 2; the first resistor R1 is connected in series between the drain of the seventh MOS transistor M7 and the drain of the eighth MOS transistor M8; the second resistor R2 and the first inductor L1 are sequentially connected in series between the drain of the ninth MOS transistor M9 and the ground GND; the third resistor R3 and the second inductor L2 are sequentially connected in series between the drain of the tenth MOS transistor M10 and the ground GND.
Vin1 and Vip1 in the figure are input signals, that is, first-stage sampling signals Von1 and Vop1 output from the first-stage sample-and-hold circuit 1, and differential signals Von2 and Vop2 are output signals of the buffer 2. The existence of the first resistor R1 enables the linearity to be increased, and the first inductor L1 and the second inductor L2 play a role in expanding the bandwidth.
Further, in this embodiment, the second-stage sample-and-hold circuit 3 includes a first sampling branch 301 and a second sampling branch 302, where an input end of the first sampling branch 301 is connected to a first output end of the corresponding buffer 2, and an output end is used as a first output end of the second-stage sample-and-hold circuit 3; the input end of the second sampling branch 302 is connected to the second output end of the corresponding buffer 2, and the output end is used as the second output end of the second stage sample-and-hold circuit 3.
Specifically, referring to fig. 6, fig. 6 is a circuit diagram of a second-stage sample-and-hold circuit according to an embodiment of the present invention, as shown in the drawing, the first sampling branch 301 includes an eleventh MOS transistor M11, a twelfth MOS transistor M12, a thirteenth MOS transistor M13, a fourteenth MOS transistor M14, a fifteenth MOS transistor M15, a sixteenth MOS transistor M16, a seventeenth MOS transistor M17, an eighteenth MOS transistor M18, a nineteenth MOS transistor M19, a twentieth MOS transistor M20, a twenty-first MOS transistor M21, a twelfth MOS transistor M22, a first capacitor C1, a second capacitor C2, and a third capacitor C3. The fourteenth MOS transistor M14 and the sixteenth MOS transistor M16 are both PMOS transistors, and the rest are NMOS transistors.
The drain electrode of the eleventh MOS transistor M11, the drain electrode of the twelfth MOS transistor M12, the drain electrode of the thirteenth MOS transistor M13, the source electrode of the fourteenth MOS transistor M14 and the gate electrode of the nineteenth MOS transistor M19 are all connected with a power supply voltage end VDD; a source electrode of the eleventh MOS transistor M11 is connected to a gate electrode of the twelfth MOS transistor M12 and a gate electrode of the thirteenth MOS transistor M13, respectively, a gate electrode of the eleventh MOS transistor M11 is connected to a source electrode of the twelfth MOS transistor M12, and a source electrode of the thirteenth MOS transistor M13 is connected to a source electrode of the sixteenth MOS transistor M16; the grid electrode of the fourteenth MOS tube M14 inputs the first signal of the corresponding differential signal of the second-stage clock signal, and the drain electrode is respectively connected with the drain electrode of the fifteenth MOS tube M15, the grid electrode of the sixteenth MOS tube M16 and the drain electrode of the seventeenth MOS tube M17; the gate of the fifteenth MOS transistor M15 inputs the first signal of the second-level clock signal corresponding to the differential signal, the source is connected to the drain of the twenty-second MOS transistor M22, the source of the seventeenth MOS transistor M17, and the source of the eighteenth MOS transistor M18, and the drain is connected to the gate of the sixteenth MOS transistor M16 and the drain of the seventeenth MOS transistor M17, respectively; the gate of the sixteenth MOS transistor M16 is connected to the drain of the seventeenth MOS transistor M17, and the drain is connected to the source of the nineteenth MOS transistor M19 and the gate of the twenty-first MOS transistor M21, respectively; the source electrode of the seventeenth MOS transistor M17 is connected with the source electrode of the eighteenth MOS transistor M18, and the grid electrodes are respectively connected with the grid electrode of the eighteenth MOS transistor M18 and the grid electrode of the twenty-first MOS transistor M21; the source electrode of the eighteenth MOS transistor M18 is connected to the drain electrode of the twenty-second MOS transistor M22, the drain electrode is connected to the source electrode of the twenty-first MOS transistor M21, and the drain electrode of the eighteenth MOS transistor M18 serves as the input end of the first sampling branch 301; the drain of the nineteenth MOS transistor M19 is connected to the source of the twentieth MOS transistor M20, the gate of the twentieth MOS transistor M20 receives the second signal of the second-level clock signal corresponding to the differential signal, and the drain is connected to the ground GND; the drain of the twenty-first MOS transistor M21 is used as the output end of the first sampling branch 301, the gate of the twenty-second MOS transistor M22 inputs the second signal of the second-level clock signal corresponding to the differential signal, and the source is connected to the ground GND; the first capacitor C1 is connected in series between the source of the eleventh MOS transistor M11 and the gate of the twenty-second MOS transistor M22, the upper plate of the second capacitor C2 is connected to the source of the twelfth MOS transistor M12, the first signal of the second-stage clock signal corresponding to the differential signal is input to the lower plate, and the third capacitor C3 is connected in series between the source of the thirteenth MOS transistor M13 and the drain of the twenty-second MOS transistor M22.
The second sampling branch 302 and the first sampling branch 301 have the same circuit structure, and the specific connection manner is not described here, it is worth to be noted that the drain of the eighteenth MOS transistor M18 of the first sampling branch 301 is used as the first input terminal of the second-stage sample-and-hold circuit 3 and connected to the first output terminal of the corresponding buffer 2, and the drain of the twenty-first MOS transistor M21 is used as the first output terminal of the second-stage sample-and-hold circuit 3. The drain of the eighteenth MOS transistor M18 of the second sampling branch 302 is used as the second input terminal of the second stage sample-and-hold circuit 3 and is connected to the second output terminal of the corresponding buffer 2, and the drain of the twenty-first MOS transistor M21 is used as the second output terminal of the second stage sample-and-hold circuit 3. The first output end and the second output end of the second-stage sample-and-hold circuit 3 output a pair of differential signals, i.e. second-stage sampling signals, and the second-stage sampling signals are transmitted to the analog-to-digital converter at the rear end.
In the figure, Vboost is the gate voltage of the twenty-first MOS transistor M21, Vin2 and Vip2 are input signals, that is, output signals Von2 and Vop2 of the buffer 2, differential signals Von3 and Vop3 are second-stage sampling signals, CLK2 is a first signal corresponding to a differential signal of the second-stage clock signal, CLKN2 is a second signal corresponding to a differential signal of the second-stage clock signal, CLK2 corresponds to the clock signal ckij (i is 1 to M, j is 1 to n) in fig. 3, and the third capacitor C3 is a bootstrap capacitor. Taking the first sampling branch 301 as an example to explain the working principle thereof, the eleventh MOS transistor M11, the twelfth MOS transistor M12, the first capacitor C1 and the second capacitor C2 constitute a voltage-doubling structure, when CLK2 is at a low level and CLKN2 is at a high level, the voltage of the upper plate of the first capacitor C1 is 2VDD, so that the thirteenth MOS transistor M13 is turned on, and CLKN2 is at a high level, so that the second twelfth MOS transistor M22 is turned on, at this time, the circuit on the right of the third capacitor C3 is in an off state, the third capacitor C3 is charged, and the voltage is VDD. When the CLK2 is at a low level and the CLKN2 is at a high level, the thirteenth MOS transistor M13 and the twelfth MOS transistor M22 are turned off, the sixteenth MOS transistor M16 and the eighteenth MOS transistor M18 are turned on, and at this time, the gate voltage Vboost of the twenty-first MOS transistor M21 is Vin2+ VDD, so that the gate voltage of the twenty-first MOS transistor M21 achieves the purpose of bootstrap, thereby greatly improving the output precision.
The multi-channel multi-stage parallel superspeed sample-and-hold circuit of this embodiment, compare in traditional sampling mode, can reduce the mismatch degree between the passageway by a wide margin, sampling speed and precision have been improved, the sample-and-hold circuit of this embodiment is provided with first order sample-and-hold circuit, buffer and second level sample-and-hold circuit, wherein, first order sample-and-hold circuit utilizes redundant transistor, most non-ideal factors have been eliminated, sampling precision has been improved, the buffer adopts the common source amplifier who has inductance peaking technique, the bandwidth of signal has been improved, second level sample-and-hold circuit utilizes the grid voltage bootstrapping to improve the linearity.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (6)
1. A multi-channel multi-stage parallel superspeed sample-and-hold circuit comprising m two-stage sample-and-hold circuits (100) connected in parallel, said two-stage sample-and-hold circuit (100) comprising a first stage sample-and-hold circuit (1), a buffer (2) and a second stage sample-and-hold circuit (3),
the first-stage sampling and holding circuit (1) is used for sampling an input signal for one time according to a first-stage clock signal to generate a first-stage sampling signal;
the n buffers (2) and the second-stage sample-and-hold circuit (3) which are connected in series are connected to the output end of the first-stage sample-and-hold circuit (1) in parallel;
the second-stage sampling and holding circuit (3) carries out second sampling on the first-stage sampling signal according to a second-stage clock signal to generate a second-stage sampling signal, and the second-stage sampling signal is transmitted to an analog-to-digital converter at the rear end;
the first-stage sample-and-hold circuit (1) and the second-stage sample-and-hold circuit (3) realize interleaving of m multiplied by n channels, wherein m and n are integers which are more than or equal to 2.
2. A multi-channel multi-stage parallel ultra high speed sample and hold circuit according to claim 1, wherein the phase difference between the first stage clock signals of the adjacent parallel first stage sample and hold circuits (1) is the inverse of the sampling frequency of the multi-channel multi-stage parallel ultra high speed sample and hold circuit; the phase difference between the second-stage clock signals of the adjacent parallel second-stage sampling and holding circuits (3) is the reciprocal of the frequency of the first-stage clock signal of the preceding first-stage sampling and holding circuit (1).
3. A multi-channel multi-stage parallel superspeed sample-and-hold circuit as claimed in claim 1, wherein said first stage sample-and-hold circuit (1) comprises a first MOS transistor (M1), a second MOS transistor (M2), a third MOS transistor (M3), a fourth MOS transistor (M4), a fifth MOS transistor (M5) and a sixth MOS transistor (M6),
the first MOS transistor (M1), the second MOS transistor (M2), the third MOS transistor (M3), the fourth MOS transistor (M4), the fifth MOS transistor (M5) and the sixth MOS transistor (M6) are all NMOS transistors;
the drain electrode of the first MOS tube (M1) is used as the first input end of the first stage sample-hold circuit (1), the source electrode is connected with the drain electrode of the second MOS tube (M2), and the grid electrode inputs the first signal of the corresponding differential signal of the first stage clock signal;
the drain electrode of the second MOS tube (M2) is connected with the source electrode thereof, the source electrode is used as the first output end of the first-stage sample-and-hold circuit (1), and the grid electrode inputs the second signal of the first-stage clock signal corresponding to the differential signal;
the drain electrode of the third MOS tube (M3) is used as the second input end of the first-stage sample-and-hold circuit (1), the source electrode is connected with the drain electrode of the fourth MOS tube (M4), and the grid electrode inputs the first signal of the corresponding differential signal of the first-stage clock signal;
the drain electrode of the fourth MOS tube (M4) is connected with the source electrode thereof, the source electrode is used as the second output end of the first-stage sample-and-hold circuit (1), and the grid electrode inputs the second signal of the first-stage clock signal corresponding to the differential signal;
the source electrode of the fifth MOS tube (M5) is connected with the drain electrode of the first MOS tube (M1), the drain electrode of the fifth MOS tube (M5) is connected with the source electrode of the fourth MOS tube (M4), and the grid electrode of the fifth MOS tube is connected with the ground terminal (GND);
the source electrode of the sixth MOS tube (M6) is connected with the drain electrode of the third MOS tube (M3), the drain electrode is connected with the source electrode of the second MOS tube (M2), and the grid electrode is connected with the ground terminal (GND).
4. A multi-channel multi-stage parallel superspeed sample-and-hold circuit as claimed in claim 1, wherein the input terminal of said buffer (2) is connected to the corresponding output terminal of said first stage sample-and-hold circuit (1), said buffer (2) comprises a seventh MOS transistor (M7), an eighth MOS transistor (M8), a ninth MOS transistor (M9), a tenth MOS transistor (M10), a first resistor (R1), a second resistor (R2), a third resistor (R3), a first inductor (L1) and a second inductor (L2), wherein,
the seventh MOS transistor (M7), the eighth MOS transistor (M8), the ninth MOS transistor (M9) and the tenth MOS transistor (M10) are all PMOS transistors;
the source electrode of the seventh MOS transistor (M7) is connected with a power supply voltage terminal (VDD), the drain electrode of the seventh MOS transistor is connected with the source electrode of the ninth MOS transistor (M9), and the grid electrode of the seventh MOS transistor is connected with a bias voltage terminal (Vb);
the source electrode of the eighth MOS transistor (M8) is connected with the power supply voltage terminal (VDD), the drain electrode of the eighth MOS transistor (M10) is connected with the source electrode of the tenth MOS transistor, and the grid electrode of the eighth MOS transistor (M8) is connected with the bias voltage terminal (Vb);
the gate of the ninth MOS transistor (M9) is used as the first input end of the buffer (2), and the drain is used as the first output end of the buffer (2);
the grid electrode of the tenth MOS tube (M10) is used as the second input end of the buffer (2), and the drain electrode is used as the second output end of the buffer (2);
the first resistor (R1) is connected in series between the drain electrode of the seventh MOS transistor (M7) and the drain electrode of the eighth MOS transistor (M8);
the second resistor (R2) and the first inductor (L1) are sequentially connected in series between the drain of the ninth MOS transistor (M9) and the Ground (GND);
the third resistor (R3) and the second inductor (L2) are sequentially connected in series between the drain of the tenth MOS transistor (M10) and the Ground (GND).
5. A multi-channel multi-stage parallel superspeed sample-and-hold circuit as claimed in claim 1, characterized in that the second stage sample-and-hold circuit (3) comprises a first sampling branch (301) and a second sampling branch (302), wherein,
the input end of the first sampling branch (301) is connected with the first output end of the corresponding buffer (2), and the output end of the first sampling branch is used as the first output end of the second-stage sample-and-hold circuit (3);
the input end of the second sampling branch (302) is connected with the second output end of the corresponding buffer (2), and the output end of the second sampling branch is used as the second output end of the second-stage sampling and holding circuit (3);
the circuit structure of the first sampling branch (301) and the second sampling branch (302) is the same.
6. The multi-channel multi-stage parallel superspeed sample-and-hold circuit of claim 5, wherein the first sampling branch (301) comprises an eleventh MOS transistor (M11), a twelfth MOS transistor (M12), a thirteenth MOS transistor (M13), a fourteenth MOS transistor (M14), a fifteenth MOS transistor (M15), a sixteenth MOS transistor (M16), a seventeenth MOS transistor (M17), an eighteenth MOS transistor (M18), a nineteenth MOS transistor (M19), a twentieth MOS transistor (M20), a twenty-first MOS transistor (M21), a second twelfth MOS transistor (M22), a first capacitor (C1), a second capacitor (C2) and a third capacitor (C3), wherein,
the fourteenth MOS tube (M14) and the sixteenth MOS tube (M16) are both PMOS tubes, and the rest are NMOS tubes;
the drain electrode of the eleventh MOS transistor (M11), the drain electrode of the twelfth MOS transistor (M12), the drain electrode of the thirteenth MOS transistor (M13), the source electrode of the fourteenth MOS transistor (M14) and the gate electrode of the nineteenth MOS transistor (M19) are all connected with a power supply voltage terminal (VDD);
the source electrode of the eleventh MOS transistor (M11) is respectively connected with the gate electrode of the twelfth MOS transistor (M12) and the gate electrode of the thirteenth MOS transistor (M13), the gate electrode is connected with the source electrode of the twelfth MOS transistor (M12), and the source electrode of the thirteenth MOS transistor (M13) is connected with the source electrode of the sixteenth MOS transistor (M16);
the grid electrode of the fourteenth MOS tube (M14) inputs a first signal of a corresponding differential signal of the second-stage clock signal, and the drain electrodes are respectively connected with the drain electrode of the fifteenth MOS tube (M15), the grid electrode of the sixteenth MOS tube (M16) and the drain electrode of the seventeenth MOS tube (M17);
the gate of the fifteenth MOS transistor (M15) inputs the first signal of the second-stage clock signal corresponding to the differential signal, the source is connected to the drain of the twelfth MOS transistor (M22), the source of the seventeenth MOS transistor (M17), and the source of the eighteenth MOS transistor (M18), and the drain is connected to the gate of the sixteenth MOS transistor (M16) and the drain of the seventeenth MOS transistor (M17);
the grid electrode of the sixteenth MOS transistor (M16) is connected with the drain electrode of the seventeenth MOS transistor (M17), and the drain electrodes are respectively connected with the source electrode of the nineteenth MOS transistor (M19) and the grid electrode of the twenty-first MOS transistor (M21);
the source electrode of the seventeenth MOS transistor (M17) is connected with the source electrode of the eighteenth MOS transistor (M18), and the grid electrodes of the seventeenth MOS transistor and the eighteenth MOS transistor are respectively connected with the grid electrode of the eighteenth MOS transistor (M18) and the grid electrode of the twenty-first MOS transistor (M21);
the source electrode of the eighteenth MOS tube (M18) is connected with the drain electrode of the twenty-second twelve MOS tube (M22), the drain electrode of the eighteenth MOS tube (M18) is connected with the source electrode of the twenty-first MOS tube (M21), and the drain electrode of the eighteenth MOS tube (M18) is used as the input end of the first sampling branch (301);
the drain of the nineteenth MOS transistor (M19) is connected with the source of the twentieth MOS transistor (M20), the gate of the twentieth MOS transistor (M20) inputs the second signal of the second-stage clock signal corresponding to the differential signal, and the drain is connected with the Ground (GND);
the drain of the twenty-first MOS transistor (M21) is used as the output end of the first sampling branch (301), the gate of the twenty-second MOS transistor (M22) inputs the second signal of the corresponding differential signal of the second-stage clock signal, and the source is connected to the Ground (GND);
the first capacitor (C1) is connected in series between the source of the eleventh MOS transistor (M11) and the gate of the second twelfth MOS transistor (M22), the upper plate of the second capacitor (C2) is connected to the source of the twelfth MOS transistor (M12), the lower plate of the second capacitor (C2) inputs the first signal of the corresponding differential signal of the second-stage clock signal, and the third capacitor (C3) is connected in series between the source of the thirteenth MOS transistor (M13) and the drain of the second twelfth MOS transistor (M22).
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