CN108233931B - Sample-hold and compare latch circuit - Google Patents

Sample-hold and compare latch circuit Download PDF

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CN108233931B
CN108233931B CN201711483543.3A CN201711483543A CN108233931B CN 108233931 B CN108233931 B CN 108233931B CN 201711483543 A CN201711483543 A CN 201711483543A CN 108233931 B CN108233931 B CN 108233931B
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CN108233931A (en
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李永凯
杨平
廖志凯
岑远军
冯浪
彭箫天
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Chengdu Hua Microelectronics Technology Co.,Ltd.
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Chengdu Sino Microelectronics Technology Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/50—Analogue/digital converters with intermediate conversion to time interval
    • H03M1/54—Input signal sampled and held with linear return to datum

Abstract

A sample-hold and compare latch circuit relates to integrated circuit technology. The invention comprises a sample-hold circuit module, a comparison latch circuit module and a common mode level inverter module, wherein the output ends of the sample-hold circuit module and the common mode level inverter module are respectively connected to the two input ends of the comparison latch circuit module. The invention has the advantages that the sampling and holding function is realized by adopting fewer devices and smaller chip area under the condition of maintaining higher sampling speed and precision, the design difficulty in the whole design process is reduced, and the circuit and layout design is easier to realize.

Description

Sample-hold and compare latch circuit
Technical Field
The present invention relates to integrated circuit technology.
Background
The sample-and-hold circuit is a key unit circuit widely used in analog circuits and hybrid circuits, particularly in AD converters and DA converters. The sample-and-hold circuit mainly samples an analog input signal and holds the analog input signal for a certain time so as to be processed by a subsequent circuit. The comparison latch is to compare the sampled and held signals to obtain a digital signal. The sample-and-hold circuit and the comparison latch circuit are used as key modules in a signal chain to directly determine the performance of the whole chip, and are necessary means for realizing AD conversion. Especially for the AD converter designed by the Flash structure, the performance and the area of the comparator determine the performance and the area of the whole chip, and the number of the comparators of the AD converter designed by the Flash structure reaches 2n-1. For example: an 8-bit pure Flash architecture AD converter requires 255 comparators. Although the number of comparators can be reduced by a segmented structure, the number of comparators required after one segmentation is at least 31, and the larger the segmentation times is, the larger the deviation is, so that how to reduce the area of the sample-hold and the comparator as much as possible becomes a problem to be faced.
Classical sample-and-hold circuit architecture:
a classic sample and hold circuit is shown in fig. 1. The classic sample-and-hold circuit consists of a unity gain buffer, an MOS switch tube and a storage capacitor. M1-M5 are connected to form a unit gain buffer, wherein M1 and M2 are differential pairs, M3 and M4 form a current mirror load, M5 is used as a tail current tube, and a bias circuit needs to be added for the M5 tube in actual work; M6-M8 are switching tubes, C is a sampling holding capacitor, and S1, S1d and S2 are control sequences of the switching tubes M6-M8.
Fig. 2 shows a simplified block diagram of a classical sample-and-hold circuit according to fig. 1. In the sampling phase, stage S1And S1dClosed, storing Vin signal on C, where S1dIs S1The delay clock of (2) is used to eliminate the effect of input feed-through; in the holding phase, stage S2And closing, transferring the Vin signal to an AMP (operational amplifier) input end, and completing the sampling and holding work through a unit buffer formed by the AMP.
A classical high-speed comparator circuit is shown in fig. 3. M11 and M12 form a differential pair, M13 and M14 form a clock-controlled differential pair, M15, M16, M17 and M18 form a regenerative loop, M19 is a switch for controlling the working state of the regenerative loop, and M9 and M10 form an inverter to form a comparator output buffer circuit. When the comparator is in the reset phase: CLK is high, and the switch M19 is turned on to short the two ends of the reset points r1 and r 2. The clocked differential pair M13 and M14 inputs an unbalanced current at r1 and r2 proportional to the pre-amplification. In the comparison stage: CLK is low and the unbalanced voltages present at regeneration points r1 and r2 are quickly amplified to digital levels by the regeneration loop consisting of PMOS and NMOS transistors.
By the aforesaid, classic sample hold circuit structure is more complicated, needs to adopt classic difference pair structure, and the components and parts figure that adopt is more, and area occupied is great. Therefore, the complexity of the chip and the design difficulty of layout and wiring are greatly increased, and the large-scale integrated circuit design with more application to the sampling circuit is not facilitated.
Disclosure of Invention
The invention aims to solve the technical problem of providing a simpler sampling hold circuit structure designed based on a CMOS inverter, which can realize a sampling hold function under the condition of maintaining higher sampling speed and precision by adopting fewer devices and smaller chip area, is easier to realize on circuit and layout design and can be widely applied to various large-scale analog and mixed circuit designs.
The technical scheme adopted by the invention for solving the technical problems is that the sample-hold and comparison latch circuit is characterized by comprising a sample-hold circuit module, a comparison latch circuit module and a common-mode level inverter module, wherein the output ends of the sample-hold circuit module and the common-mode level inverter module are respectively connected to two input ends of the comparison latch circuit module.
The sample-and-hold circuit module includes:
a first input terminal connected to the anode of the first capacitor C1 through a first gate switch K1;
a second input terminal connected to the anode of the first capacitor C1 through a second gate switch K2;
a third input terminal connected to the anode of the second capacitor C2 through a third gate switch K3;
a fourth input terminal connected to the anode of the second capacitor C2 through a fourth gate switch K4;
the cathode of the first capacitor C1 and the cathode of the second capacitor C2 are connected with the input end of the first CMOS inverter;
the input end of the first CMOS inverter is connected with the source electrode and the drain electrode of the twenty-third MOS transistor M23, and the output end of the first CMOS inverter is connected with the anode of the third capacitor C3;
the input end of the first CMOS phase inverter is also connected with the current input end of a twenty-fourth MOS transistor M24;
the current output end of the twenty-fourth MOS transistor M24 is connected with the anode of the third capacitor C3;
the negative electrode of the third capacitor C3 is connected with the input end of the second CMOS inverter;
the input end of the second CMOS inverter is connected with the source electrode and the drain electrode of the twenty-seventh MOS transistor M27, and the output end of the second CMOS inverter is connected with a first reference point through a fifth gating switch K5;
the input end of the second CMOS inverter is also connected with the current input end of a twenty-eighth MOS transistor M28;
and the current output end of the twenty-eighth MOS transistor M28 is connected with the output end of the second CMOS inverter.
The first CMOS phase inverter and the second CMOS phase inverter are both composed of two MOS tubes which are connected in series.
The comparison latch circuit module comprises:
a current input end of the thirty-first MOS tube M31 is connected with a system high level, a gate end of the thirty-first MOS tube M31 is used as an input end of the second clock, and a current output end of the thirty-third MOS tube M33 is connected with a current input end of the thirty-fifth MOS tube M35;
a current input end of the thirty-second MOS transistor M32 is connected with a current output end of the thirty-fourth MOS transistor M34 and a current output end of the thirty-sixth MOS transistor M36, a current output end of the thirty-second MOS transistor M32 is grounded, and a gate end of the thirty-second MOS transistor M32 is used as an inverted signal input end of the second clock;
a gate terminal of the thirty-third MOS transistor M33 is connected to the first reference point, and a current output terminal of the thirty-fourth MOS transistor M34 is connected to a current input terminal of the thirty-fifth MOS transistor M35 and a gate terminal of the thirty-sixth MOS transistor M36;
a thirty-fourth MOS transistor M34, the gate terminal of which is connected with the first reference point, and the current input terminal of which is also connected with the second reference point;
a thirty-fifth MOS transistor M35, the current output end of which is connected with the current output end of the forty-first MOS transistor M41, and the current output end of which is also connected with the first reference point;
and the current input end of the thirty-sixth MOS tube M36 is connected with the current output end of the forty-first MOS tube M41, the gate end of the thirty-sixth MOS tube M36 is connected with the gate end of the thirty-fifth MOS tube, and the gate end of the thirty-sixth MOS tube M36 is also connected with a second reference point.
A thirty-seventh MOS transistor M37, the current input end of which is connected with the system high level VDD, the current output end of which is connected with the current input end of the forty-first MOS transistor, and the gate end of which is connected with a third reference point;
a thirty-eighth MOS tube M38, the current input end of which is connected with the system high level VDD, the current output end of which is connected with a third reference point, and the gate end of which is connected with the current output end of the thirty-seventh MOS tube;
a thirty-ninth MOS transistor M39, the gate terminal of which is connected with the third clock input terminal, the current input terminal of which is connected with the system high level VDD, and the current output terminal of which is connected with the gate terminal of a thirty-seventh MOS transistor M37;
a forty-th MOS transistor M40, the gate terminal of which is connected with the third clock input terminal, the current input terminal of which is connected with the system high level VDD, and the current output terminal of which is connected with the gate terminal of the thirty-eighth MOS transistor M38;
a forty-first MOS transistor M41, the gate terminal of which is connected to the third clock input terminal;
a forty-second MOS transistor M42, the gate of which is connected with the third clock input end, the current output end of which is connected with the second reference point, and the current input end of which is connected with the third reference point;
the third reference point is connected to the final output through an inverter.
The common mode level inverter module is composed of a twenty ninth MOS tube M29 and a thirty MOS tube M30 which are connected in series, the grids of the twenty ninth MOS tube M29 and the thirty MOS tube M30 are connected to a series connection point, the series connection point is connected to a second reference point through a sixth gating switch K6, and the series connection point is a connection point of a current output end of the twenty ninth MOS tube M29 and a current input end of the thirty MOS tube M30.
The invention has the advantages that the sampling and holding function is realized by adopting fewer devices and smaller chip area under the condition of maintaining higher sampling speed and precision, the design difficulty in the whole design process is reduced, and the circuit and layout design is easier to realize.
Drawings
Fig. 1 is a classic sample and hold circuit diagram.
Fig. 2 is a block diagram of a classical sample and hold circuit.
Fig. 3 is a circuit diagram of a classic high-speed comparator.
Fig. 4 is a circuit diagram of a sample and hold circuit used in the present invention.
FIG. 5 is a circuit diagram of a comparison latch circuit used in the present invention.
FIG. 6 is a circuit diagram of the sample-and-hold and compare-latch circuit of the present invention.
FIG. 7 is a timing diagram of the present invention.
Fig. 8 is a waveform diagram illustrating a sample-and-hold function verification according to the present invention.
FIG. 9 is a graph of the comparative latch simulation waveform of the present invention
FIG. 10 is a diagram of THD and ENOB simulation waveforms in accordance with the present invention.
Detailed Description
The invention directly adopts the CMOS inverter as the common-mode output voltage and AMP to use, thus completing the sampling and holding function of the input signal.
The invention utilizes the short circuit of the output end and the input end of the CMOS inverter, and the generated voltage (generally Vdd/2, and the flip voltage and the common-mode value of the comparator can be adjusted according to the specific power consumption requirement) is used as the common-mode voltage of the sampling holding, thereby saving the common-mode voltage generating circuit required by the common sampling holding circuit and effectively reducing the complexity of the sampling holding circuit.
In the invention, the CMOS inverter is used as the AMP to amplify the sampling signal while the front-stage switch capacitor completes the charge transfer, so that the design difficulty of the rear-stage circuit is reduced, a special AMP is not required to be used for amplifying or buffering the output sampling holding signal, and the complexity and layout design difficulty of the circuit are further reduced;
the sample-and-hold circuit includes an input unit, a first stage sample-and-hold unit, and a second stage sample-and-hold unit. Fig. 4 shows an input unit and a first stage sample-and-hold unit.
The input unit includes 4 gate switches and a first capacitor C1 and a second capacitor C2, which have the same capacitance value. The first-stage sample-and-hold unit and the second-stage sample-and-hold unit are identical in structure, are provided with a MOS capacitor for inhibiting the clock feedthrough effect, and are provided with a CMOS inverter formed by two MOS tubes in series.
The input signal Vin port is connected with the upper plate of the first capacitor C1 through a first gating switch K1, and the Vflash port is connected with the upper plate of the first capacitor C1 through a second gating switch K2; the 0.5LSB port is connected with the upper plate of a second capacitor C2 through a third gating switch K3, and the VREF-port is connected with the upper plate of a second capacitor C2 through a fourth gating switch K4;
the lower electrode plates of the first capacitor C1 and the second capacitor C2 are connected together in a short circuit and then connected to the input end of the first-stage sample-and-hold unit, the first-stage sample-and-hold unit is connected to one end of the source drain of the twenty-fourth MOS transistor M24 and the source drain of the twenty-third MOS transistor M23 serving as a MOS capacitor, and the other end of the source drain of the twenty-fourth MOS transistor M24 is connected to the output end of the CMOS phase inverter. The CMOS phase inverter is formed by connecting a twenty-first MOS transistor M21 and a twenty-second MOS transistor M22 in series, wherein the grid electrode of a twenty-fourth MOS transistor M24 is connected with a clock signal CLK1, the grid electrode of a MOS capacitor (a twenty-third MOS transistor) is connected with clock signals CLK1, and 'to' represents the phase inversion.
For convenience of description, the device names are directly represented by symbols in the drawings, for example, M34 denotes a "thirty-four MOS transistor M34".
Fig. 5 shows a comparison latch circuit BLOCK (BLOCK2) of the present invention, which includes a cross-coupled dual CMOS inverter comparator circuit. M33 and M34, M35 and M36 are respectively connected in series to form an inverter structure; m33 and M35, M34 and M36 are respectively short-circuited at the source ends; the input end of the inverter formed by M33 and M34 is shorted with the output end of the inverter formed by M35 and M36 and connected to IN & OUT1 (namely, a first reference point), and the output end of the inverter formed by M33 and M34 is shorted with the input end of the inverter formed by M35 and M36 and connected with IN & OUT2 (a second reference point); m31 and M32 are used as switching tubes, the source of M31 is connected to VDD, the drain of M31 is connected to the source ends of inverter devices M33 and M35, and the gate of M31 is connected to a second clock CLK 2; the source end of M32 is connected to GND, the drain end is connected to the source ends of inverter devices M34 and M36, and the gate of M32 is connected to-CLK 2; CLK2 and CLK2 are inverted clock signals.
M37 and M38 form a positive feedback circuit, and M39-M42 form a dynamic latch switch. The source ends of M37 and M38 are respectively connected to VDD, the drain end of M37 is connected in series with M41 and then connected with the output end of an inverter consisting of a cross-coupled double CMOS inverter comparator circuit M35 and M36, and the drain end of M38 is connected in series with M42 and then connected with the output end of an inverter consisting of a cross-coupled double CMOS inverter comparator circuit M33 and M34; the M39-M42 gates are connected together and then clocked with CLK 3.
Fig. 6 is a complete circuit of the present invention. The circuit samples and amplifies an input signal by adopting a two-stage same sampling and holding circuit, and the amplified input signal is sent to the input end of a comparator to be compared with a common mode level to output a comparison result. The common mode level is designed based on the inverter structure, so that the common mode level generated by using a peripheral circuit is omitted, and the difficulty in chip design is effectively reduced. In the present invention, the PMOS transistor and NMOS transistor of the inverter (two CMOS inverters in BLOCK 1) and the inverter (BLOCK3) forming common mode level in the sample hold circuit have the same ratio of width to length,
and the inverter in the second-stage sample-and-hold circuit and the inverter (BLOCK3) PMOS tube and NMOS tube forming the common mode level adopt the same width-length ratio, have the same turnover point level, and can effectively improve the precision of the whole sample-and-hold and comparison circuit.
Example (b):
see fig. 4, 5, 6.
The invention comprises a sample-and-hold circuit (see fig. 4) and a comparison latch circuit (see fig. 5). The whole circuit of the invention is shown in figure 6.
The invention uses the voltage division characteristic when the input and the output of the MOS inverter are short-circuited as the common mode level in the sampling stage, and completes the sampling and holding process of the input signal by using the amplification characteristic when the input and the output of the CMOS inverter are disconnected.
The working principle of the sample hold circuit is as follows: in the sampling stage, K2, K4 and CLK1 are opened, K1, K3 and CLK1 are closed, Vflash and VREF-signals are connected with upper electrode plates of storage capacitors C1 and C2, CLK1 is opened to enable an MOS inverter to be conducted to form divided voltage Vcm, the divided voltage is connected with negative electrode plates of capacitors C1 and C2 in a common mode voltage mode, and Vflash signals are sampled to the input end of the inverter. In the holding stage, K2, K4 and CLK1 are closed, K1 and K3 are opened, the Vin signal and the 0.5LSB signal are transferred to the input end of the inverter, and CLK1 is opened to inhibit the leakage charges generated in the process of CLK1 closing, so that the Vin signal is sampled and held at the input end of the inverter and is transmitted to the output end Vout through the amplification effect of the CMOS inverter, and the sampling and holding work is completed.
In FIG. 4, Vflash is the comparison voltage in Flash ADC, and for 4-bit ADC, the Vflash voltages are respectively
Figure GDA0003046214400000051
Δ Vx is the CMOS inverter inputThe voltage variation of the port, Vcm is common mode voltage formed by input and output short circuits of the CMOS inverter, and Cp is MOS capacitance formed by M3.
Can be calculated in the sample and hold stage (Cp is far less than C)
Figure GDA0003046214400000052
△Vx＝Vx-Vcm (2)
From (1) and (2) can be obtained
Figure GDA0003046214400000053
△Vout＝-A*△Vx (4)
A is the gain of the CMOS inverter, thus obtaining the sampling voltage, and the sampling voltage is amplified by A times.
The comparison latch circuit (fig. 5) includes two input terminals VIN & OUT1, VIN & OUT2, an output terminal VOUT, a CMOS inverter formed by connecting M33 and M34 in series, a CMOS inverter formed by connecting M35 and M36 in series, a positive feedback circuit formed by connecting M37 and M38, and switching tubes M31, M32, and M39 to M42. The invention utilizes the comparator formed by the interconnection of the input and the output of two CMOS phase inverters and combines the positive feedback formed by a PMOS tube, thereby improving the working speed of the original comparator structure, reducing the dynamic power consumption of the whole comparator by utilizing the dynamic clock latching technology formed by the switching tubes M39-M42, and realizing the high-speed comparison function by increasing less devices and chip areas.
The working principle of the comparison latch circuit is as follows: in the comparison stage, CLK2 and CLK2 are opened before CLK3, and after VIN & OUT1 and VIN & OUT2 signals enter the comparator for comparison, CLK3 is opened, the comparison is completed and the comparison result is output; in the non-comparison stage, CLK2, CLK2 and CLK3 are closed, and the whole comparator is in a closed state, so that the power consumption of the whole comparator is reduced.
Fig. 6 shows a sample-and-hold circuit and a comparison latch complete circuit. The circuit samples and amplifies an input signal by adopting a two-stage same sampling and holding circuit, and the amplified input signal is sent to the input end of a comparator to be compared with a common mode level to output a comparison result. The common mode level is designed based on the inverter structure, so that the common mode level generated by using a peripheral circuit is omitted, and the difficulty in chip design is effectively reduced. Because the PMOS tube and the NMOS tube of the phase inverter in the sample hold circuit and the phase inverter forming the common mode level have the same width-length ratio, and the PMOS tube and the NMOS tube of the phase inverter in the second-stage sample hold circuit and the phase inverter forming the common mode level adopt the same width-length ratio, the PMOS tube and the NMOS tube have the same turning point, the influence caused by offset voltage is effectively reduced, and the precision of the whole sample hold and comparison circuit can be effectively improved.
The invention fully utilizes the inverter as a main circuit to realize the functions of sampling, holding, comparing and latching. Compared with the traditional adoption and protection and comparison latch circuit formed by adopting differential operational amplifier, the structure is simpler, the occupied layout area is smaller, and the realization is easier.
Simulation verification
In the present invention, the 8-bit AD converter is actually used in the design, and fig. 8 is a waveform for verifying the sample-and-hold function of the 8-bit AD converter. Vin is a sine wave input signal with frequency of 79.7119140625KHz, offset voltage of 2.5V and swing of 2.5V. Vout is an output waveform, and the waveform shows that the sampling and holding circuit realizes the sampling and holding function of the 8-bit AD converter.
FIG. 9 shows simulation waveforms of the comparison latch circuit of the present invention. The output results are all inverted at the comparison latch stage of the cross point of the input signals, the hysteresis or the advance phenomenon does not exist, and the high-speed comparison and latch process is really realized.
Fig. 10 shows the simulation waveform verification result of the 8-bit converter designed by the present invention, which realizes the sample-and-hold function of the AD converter. In this 8-bit AD converter: THD reaches 43.073dB (fs is 80KHz), ENoB is 6.862.
Table 1 actual measurement results of 8-bit AD converter samples designed by the present invention
Figure GDA0003046214400000061
It can be seen from fig. 8, 9, 10 and table 1 that the sample-hold and compare-latch function is realized by the present invention, the linearity error is less than or equal to 0.5LSB, THD is less than or equal to 43.073dB, and ENob is 6.862. The invention has the characteristics of simple structure and easy integration.

Claims (4)

1. The sampling holding and comparing latch circuit is characterized by comprising a sampling holding circuit module, a comparing latch circuit module and a common mode level inverter module, wherein the output ends of the sampling holding circuit module and the common mode level inverter module are respectively connected to the two input ends of the comparing latch circuit module;
the common mode level inverter module is composed of a twenty-ninth MOS transistor (M29) and a thirty-fifth MOS transistor (M30) which are connected in series, the gates of the twenty-ninth MOS transistor (M29) and the thirty-fifth MOS transistor (M30) are connected to a series connection point, the series connection point is connected to a second reference point through a sixth gate switch (K6), and the series connection point is a connection point of a current output end of the twenty-ninth MOS transistor (M29) and a current input end of the thirty-fifth MOS transistor (M30).
2. The sample-and-hold and compare-latch circuit of claim 1, wherein the sample-and-hold circuit block comprises:
a first input terminal connected to the positive electrode of the first capacitor (C1) through a first gate switch (K1);
a second input terminal connected to the anode of the first capacitor (C1) through a second gate switch (K2);
a third input terminal connected to the anode of the second capacitor (C2) through a third gate switch (K3);
a fourth input terminal connected to the anode of the second capacitor (C2) through a fourth gate switch (K4);
the cathode of the first capacitor (C1) and the cathode of the second capacitor (C2) are connected with the input end of the first CMOS inverter;
the input end of the first CMOS inverter is connected with the source electrode and the drain electrode of the twenty-third MOS transistor (M23), and the output end of the first CMOS inverter is connected with the anode of the third capacitor (C3);
the input end of the first CMOS inverter is also connected with the current input end of a twenty-four MOS tube (M24);
the current output end of the twenty-fourth MOS tube (M24) is connected with the anode of the third capacitor (C3);
the negative electrode of the third capacitor (C3) is connected with the input end of the second CMOS inverter;
the input end of the second CMOS inverter is connected with the source electrode and the drain electrode of the twenty-seventh MOS transistor (M27), and the output end of the second CMOS inverter is connected with a first reference point through a fifth gating switch (K5);
the input end of the second CMOS inverter is also connected with the current input end of a eighteenth MOS tube (M28);
and the current output end of the twenty-eight MOS tube (M28) is connected with the output end of the second CMOS inverter.
3. The sample-hold-and-compare latch circuit of claim 2, wherein the first CMOS inverter and the second CMOS inverter are each formed of two MOS transistors connected in series.
4. The sample-and-hold and compare latch circuit of claim 1, wherein the compare latch circuit block comprises:
a thirty-first MOS transistor (M31), the current input end of which is connected with the system high level, the gate end of which is used as the input end of the second clock, and the current output end of which is connected with the current input end of a thirty-third MOS transistor (M33) and the current input end of a thirty-fifth MOS transistor (M35);
a current input end of the third twelve MOS transistor (M32) is connected with a current output end of the third fourteen MOS transistor (M34) and a current output end of the third sixteen MOS transistor (M36), a current output end of the third twelve MOS transistor is grounded, and a grid end of the third twelve MOS transistor is used as an inverted signal input end of the second clock;
a gate terminal of the thirteenth MOS transistor (M33) is connected with the first reference point, and a current output terminal of the thirteenth MOS transistor is connected with a current input terminal of the fourteenth MOS transistor (M34), a gate terminal of the fifteenth MOS transistor (M35) and a gate terminal of the sixteenth MOS transistor (M36);
a thirty-fourth MOS tube (M34), wherein the grid end of the thirty-fourth MOS tube is connected with the first reference point, and the current input end of the thirty-fourth MOS tube is also connected with the second reference point;
a current output end of the thirty-fifth MOS tube (M35) is connected with a current output end of the forty-first MOS tube (M41), and the current output end of the thirty-fifth MOS tube is also connected with the first reference point;
the current input end of the sixteenth MOS tube (M36) is connected with the current output end of the eleventh MOS tube (M41), the gate end of the sixteenth MOS tube is connected with the gate end of the fifteenth MOS tube (M35), and the gate end of the sixteenth MOS tube is also connected with a second reference point;
a current input end of the seventeenth MOS tube (M37) is connected with a system high level VDD, a current output end of the seventeenth MOS tube is connected with a current input end of the forty-first MOS tube (M41), and a grid end of the seventeenth MOS tube is connected with a third reference point;
the current input end of the thirty-eighth MOS tube (M38) is connected with the system high level VDD, the current output end is connected with a third reference point, and the grid end is connected with the current output end of the thirty-seventh MOS tube (M37);
a gate end of the thirty-ninth MOS tube (M39) is connected with a third clock input end, a current input end of the thirty-ninth MOS tube is connected with a system high level VDD, and a current output end of the thirty-ninth MOS tube is connected with a gate end of the thirty-seventh MOS tube (M37);
a forty-fifth MOS transistor (M40), the gate terminal of which is connected with the third clock input terminal, the current input terminal of which is connected with the system high level VDD, and the current output terminal of which is connected with the gate terminal of the thirty-eighth MOS transistor (M38);
a fourth eleventh MOS transistor (M41), the gate terminal of which is connected with the third clock input terminal;
a fourth twelve MOS tube (M42), the grid end of which is connected with the third clock input end, the current output end of which is connected with the second reference point, and the current input end of which is connected with the third reference point;
the third reference point is connected to the final output through an inverter.
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