CN108233931A - Sampling keeps the latch cicuit compared with - Google Patents
Sampling keeps the latch cicuit compared with Download PDFInfo
- Publication number
- CN108233931A CN108233931A CN201711483543.3A CN201711483543A CN108233931A CN 108233931 A CN108233931 A CN 108233931A CN 201711483543 A CN201711483543 A CN 201711483543A CN 108233931 A CN108233931 A CN 108233931A
- Authority
- CN
- China
- Prior art keywords
- oxide
- semiconductor
- metal
- input terminal
- current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/50—Analogue/digital converters with intermediate conversion to time interval
- H03M1/54—Input signal sampled and held with linear return to datum
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Sampling keeps the latch cicuit compared with, is related to integrated circuit technique.The present invention includes sampling hold circuit module, compares latch cicuit module and common mode electrical level inverter modules, and the output terminal of sampling hold circuit module and common mode electrical level inverter modules is connected respectively to two input terminals for comparing latch cicuit module.The beneficial effects of the invention are as follows, in the case where maintaining higher sample rate and precision, by using less device and smaller chip area, realize sampling and keep function, the design difficulty in entire design process is reduced, is more easily realized on circuit and layout design.
Description
Technical field
The present invention relates to integrated circuit techniques.
Background technology
Sampling hold circuit is widely applied essential elements circuit in analog circuit and hybrid circuit, is particularly turned in AD
In parallel operation and D/A converter.Sampling hold circuit mainly samples analog input signal, and keep certain time so as to
Late-class circuit is handled.Compare the signal for latching and being to keep to sampling and be compared processing, obtain digital signal.Sampling is kept
Circuit latch cicuit compared with directly determines the performance of whole chips as the key modules in signal chains, is to realize AD conversion
Necessary means.Especially for the AD converter of Flash structure designs, the performance and area of comparator determine whole chips
Performance and area reach 2 using the AD converter comparator number of Flash structure designsn- 1.Such as：One 8 pure
The AD converter of Flash structures needs 255 comparators.Although the number of comparator can be reduced by segmental structure,
The comparator needed after primary segmentation at least also wants 31 comparators, and is segmented that number is more, and the deviation brought is also bigger, this
Sample how to reduce as possible sampling keep and comparator area just become must face the problem of.
Classical sampling hold circuit structure：
It is as shown in Figure 1 classical sampling hold circuit figure.Classical sampling hold circuit is by unity gain buffer, MOS
Switching tube and storage capacitance composition.M1~M5 connects into unity gain buffer, and wherein M1 and M2 is differential pair, and M3 and M4 is formed
Current mirror load, M5 need to increase biasing circuit in real work as tail current pipe for M5 pipes；M6~M8 be switching tube, C
To sample holding capacitor, S1, S1d, S2 are the control sequential of switching tube M6~M8.
Classical sampling hold circuit block diagram to be simplified according to Fig. 1 as shown in Figure 2.In sampling rank, section S1With S1dIt is closed, it will
Vin signals are stored on C, wherein S1dFor S1Delayed clock for eliminate input feedthrough caused by influence；Keeping rank, section
S2It is closed, Vin signals are transferred to AMP (operational amplifier) input terminal, complete sampling by the unit buffer that AMP is formed and protect
Hold work.
It is illustrated in figure 3 as classical high-speed comparator circuit.M11 and M12 forms differential pair, clock when M13 and M14 is
The differential pair of system, M15, M16, M17, M18 composition regeneration ring, M19 regenerate the switch of ring working condition, M9 and M10 groups in order to control
Comparator output buffer is formed into phase inverter.When comparator is in reseting stage：CLK is high level, and switching tube M19 is connected,
By reduction point r1 and r2 shorted on both ends.The differential pair M13 and M14 of clock control is proportional to preposition amplification in r1 and r2 inputs
Out-of-balance current.In comparison phase：CLK is low level, is present in the unbalance voltage of regeneration point r1 and r2 by PMOS and NMOS
The regeneration ring of transistor composition is amplified to rapidly digital level.
By aforementioned, classical sampling hold circuit structure is more complicated, needs, using classical differential pair structure, to be used
Component number is more, and area occupied is larger.The complexity of chip and the design of laying out pattern wiring are considerably increased in this way
Difficulty is unfavorable for applying more VLSI Designs for sample circuit.
Invention content
The technical problems to be solved by the invention are to propose a kind of simpler sampling based on CMOS inverter design
Holding circuit structure, the structure can maintain higher sampling speed by using less device and smaller chip area
It under degree and precision, realizes that sampling keeps function, is more easily realized on circuit and layout design, can be widely applied to all kinds of big
Among scale simulation and design of hybrid circuits.
The present invention solve the technical problem the technical solution adopted is that, sampling keep compared with latch cicuit, feature
It is, including sampling hold circuit module, compares latch cicuit module and common mode electrical level inverter modules, sampling hold circuit mould
The output terminal of block and common mode electrical level inverter modules is connected respectively to two input terminals for comparing latch cicuit module.
The sampling hold circuit module includes：
First input end is connected to the anode of the first capacitance C1 by the first gating switch K1；
Second input terminal is connected to the anode of the first capacitance C1 by the second gating switch K2；
Third input terminal is connected to the anode of the second capacitance C2 by third gating switch K3；
4th input terminal is connected to the anode of the second capacitance C2 by the 4th gating switch K4；
The cathode of the cathode of first capacitance C1 and the second capacitance C2 connect the input terminal of the first CMOS inverter；
The input terminal of first CMOS inverter connects the source electrode and drain electrode of the 23rd metal-oxide-semiconductor M23, the first CMOS inverter
Output termination third capacitance C3 anode；
The input terminal of first CMOS inverter is also connected with the current input terminal of the 24th metal-oxide-semiconductor M24；
The anode of the current output terminal connection third capacitance C3 of 24th metal-oxide-semiconductor M24；
The cathode of third capacitance C3 connects the input terminal of the second CMOS inverter；
The input terminal of second CMOS inverter connects the source electrode and drain electrode of the 27th metal-oxide-semiconductor M27, the second CMOS inverter
Output terminal the first reference point is connect by the 5th gating switch K5；
The input terminal of second CMOS inverter is also connected with the current input terminal of the 28th metal-oxide-semiconductor M28；
The current output terminal of 28th metal-oxide-semiconductor M28 connects the output terminal of the second CMOS inverter.
First CMOS inverter and the second CMOS inverter are all made of the metal-oxide-semiconductor of two series connection.
The relatively latch cicuit module includes：
31st metal-oxide-semiconductor M31, current input terminal welding system high level, input terminal of the grid end as second clock,
Its current output terminal connects the current input terminal of the 33rd metal-oxide-semiconductor M33 and the current input terminal of the 35th metal-oxide-semiconductor M35；
32nd metal-oxide-semiconductor M32, current input terminal connect the current output terminal and the 36th of the 34th metal-oxide-semiconductor M34
The current output terminal of metal-oxide-semiconductor M36, current output terminal ground connection, non-inverting signal input thereof of the grid end as second clock；
33rd metal-oxide-semiconductor M33, grid end connect the first reference point, and current output terminal connects the 34th metal-oxide-semiconductor M34's
The grid end of current input terminal, the grid end of the 35th metal-oxide-semiconductor M35 and the 36th metal-oxide-semiconductor M36；
34th metal-oxide-semiconductor M34, grid end connect the first reference point, and current input terminal also connects the second reference point；
35th metal-oxide-semiconductor M35, current output terminal connect the current output terminal of the 41st metal-oxide-semiconductor M41, and electric current is defeated
Outlet is also connect with the first reference point；
36th metal-oxide-semiconductor M36, current input terminal connect the current output terminal of the 41st metal-oxide-semiconductor M41, and grid end connects
The grid end of 35th metal-oxide-semiconductor, grid end also connect the second reference point.
37th metal-oxide-semiconductor M37, current input terminal welding system high level VDD, current output terminal meet the 41st MOS
The current input terminal of pipe, grid end connect third reference point；
38th metal-oxide-semiconductor M38, current input terminal welding system high level VDD, current output terminal connect third reference point,
Grid end connects the current output terminal of the 37th metal-oxide-semiconductor；
39th metal-oxide-semiconductor M39, grid end connect third input end of clock, current input terminal welding system high level VDD,
Current output terminal connects the grid end of the 37th metal-oxide-semiconductor M37；
40th metal-oxide-semiconductor M40, grid end connect third input end of clock, current input terminal welding system high level VDD, electricity
The grid end of the 38th metal-oxide-semiconductor M38 of stream output termination；
41st metal-oxide-semiconductor M41, grid end connect third input end of clock；
42nd metal-oxide-semiconductor M42, grid end connect third input end of clock, and current output terminal connects the second reference point, electricity
Stream input termination third reference point；
Third reference point is connected to final output end by a phase inverter.
The common mode electrical level inverter modules are made of the 29th metal-oxide-semiconductor M29 to connect and the 30th metal-oxide-semiconductor M30, the
The grid of 29 metal-oxide-semiconductor M29 and the 30th metal-oxide-semiconductor M30, which is connected on, to be connected in series with a little, is connected in series with and is a little opened by the 6th gating
It closes K6 and is connected to the second reference point, it is described to be connected in series with a little as the current output terminal and the 30th MOS of the 29th metal-oxide-semiconductor M29
The tie point of the current input terminal of pipe M30.
The invention has the advantages that in the case where maintaining higher sample rate and precision, by using less device and
Smaller chip area realizes sampling and keeps function, the design difficulty in entire design process reduced, in circuit and domain
It is more easily realized in design.
Description of the drawings
Fig. 1 is classical sampling hold circuit figure.
Fig. 2 is classical sampling hold circuit block diagram.
Fig. 3 is adopts classical high-speed comparator circuit diagram.
Fig. 4 is used sampling hold circuit figure by the present invention.
Fig. 5 by the present invention use compare the circuit diagram of latch cicuit.
Fig. 6 is used sampling to keep and compare latch complete circuit by the present invention.
Fig. 7 is used sequence diagram by the present invention.
Fig. 8 keeps functional verification oscillogram for present invention sampling.
Fig. 9 relatively latches simulation waveform for the present invention
Figure 10 is THD and ENOB simulation waveforms of the present invention.
Specific embodiment
The present invention is directly used using CMOS inverter as common mode output voltage and AMP, is completed to input signal
Sampling keeps function.
The present invention is using CMOS inverter output terminal and input terminal short circuit, and (generally Vdd/2, can root for generated voltage
Turnover voltage, the common mode value of comparator are adjusted according to specific power consumption requirements) as the common-mode voltage for sampling holding, it eliminates and usually adopts
Common-mode voltage generation circuit needed for sample holding circuit effectively reduces the complexity adopted and protect circuit.
In the present invention, CMOS inverter is used as AMP to sampling while prime switching capacity completes electric charge transfer
Signal is also exaggerated, and reduces the design difficulty of rear stage circuit, it is not necessary to as amplification or be delayed using special AMP again
Punching output sampling keeps signal, further reduces the complexity of circuit and layout design difficulty；
Sampling hold circuit includes input unit, first order sample holding unit and second level sample holding unit.Fig. 4 shows
Input unit and first order sample holding unit are gone out.
Input unit includes 4 gating switches and the first capacitance C1 and the second capacitance C2, the capacitance phase of the two capacitances
Deng.First order sample holding unit is identical with second level sample holding unit structure, and all there are one inhibit clock feed-through effect for tool
Mos capacitance and, all there are one connected the CMOS inverter formed tool by two metal-oxide-semiconductors.
Input signal Vin ports connect the top crown of the first capacitance C1, while Vflash ports by the first gating switch K1
The top crown of the first capacitance C1 is connected to by the second gating switch K2；0.5LSB ports connect the second electricity by third gating switch K3
Hold the top crown of C2, while VREF- ports are connected to the top crown of the second capacitance C2 by the 4th gating switch K4；
The bottom crown of first capacitance C1 and the second capacitance C2, which are shorted together, is followed by the input of first order sample holding unit
End, be connected to one end in the 24th metal-oxide-semiconductor M24 source and drain, as mos capacitance the 23rd metal-oxide-semiconductor M23 source and drain two
End, the other end of the 24th metal-oxide-semiconductor M24 source and drain are connected to the output terminal of CMOS inverter.CMOS inverter is by the 21st
Metal-oxide-semiconductor M21 is concatenated with the 22nd metal-oxide-semiconductor M22, and the 24th metal-oxide-semiconductor M24 grids connect clock signal clk 1, mos capacitance
(the 23rd metal-oxide-semiconductor) grid is connected with clock signal~CLK1, and "~" represents reverse phase.
For ease of description, device name is directly represented with the label in attached drawing below, for example, representing the " the 34th with M34
Metal-oxide-semiconductor M34 ".
Fig. 5 show the comparison latch cicuit module (BLOCK2) of the present invention, including the double CMOS inverter ratios of cross-couplings
Compared with device circuit.M33 and M34, M35 and M36 are serially connected to form inverter structure respectively；The source of M33 and M35, M34 and M36
End is shorted together respectively；The inverter output short circuit that the input terminal of M33 and M34 composition phase inverters is formed with M35 and M36 is simultaneously
The output terminal for being connected to the phase inverter of IN＆OUT1 (i.e. the first reference point), M33 and M34 composition is shorted to M35 and M36 compositions
The input terminal of phase inverter, while connect with IN＆OUT2 (the second reference point)；M31 and M32 is used as switching tube, the source electrode of M31
VDD is connected to, drain terminal is connected to the source of inverter device M33 and M35, the grid connection second clock CLK2 of M31；M32's
Source is connected to GND, and drain terminal is connected to the source of inverter device M34 and M36, and the grid of M32 is connected to~CLK2；CLK2 with
~CLK2 is inverting clock signal.
M37, M38 form positive-feedback circuit, and M39~M42 forms dynamic latch switch.M37 couples respectively with the source of M38
To VDD, the drain terminal of M37 concatenates the phase inverter formed after M41 with the double CMOS inverter comparator circuit M35 and M36 of cross-couplings
Output terminal be connected, after the drain terminal of M38 concatenation M42 with the double CMOS inverter comparator circuit M33 and M34 compositions of cross-couplings
The output terminal of phase inverter is connected；M39~M42 grids are connected after linking together with CLK3 clocks.
Fig. 6 is the complete circuit of the present invention.The circuit by using the similary sampling hold circuit of two-stage to input signal into
Row is sampled and is amplified, and is sent to the input terminal of comparator after amplification and common mode electrical level is compared output comparison result.Common mode electricity
It is flat equally to be designed based on inverter structure, it is omitted and generates common mode electrical level using peripheral circuit, it is difficult to effectively reduce chip design
Degree.In the present invention, the phase inverter in sampling hold circuit (two CMOS inverters in BLOCK1) is with forming common mode electrical level
The PMOS tube of phase inverter (BLOCK3) must have identical breadth length ratio ratio with NMOS tube,
And in the sampling hold circuit of the second level phase inverter with formed common mode electrical level phase inverter (BLOCK3) PMOS tube with
NMOS tube uses identical breadth length ratio, has completely the same overturning level point, can effectively improve entire sampling and keep
And the precision of comparison circuit.
Embodiment：
Referring to Fig. 4, Fig. 5, Fig. 6.
The present invention includes sampling hold circuit (see Fig. 4), compares latch cicuit (see Fig. 5).Integrated circuit of the present invention is shown in figure
6。
The partial pressure properties when present invention is by the use of MOS phase inverter input and output short circuits as sample phase common mode electrical level, it is sharp
The sampling that amplification characteristic when being disconnected with CMOS inverter input and output completes to input signal keeps process.
Sampling hold circuit operation principle is：In sample phase, K2, K4 and CLK1 are opened, K1, K3 and~CLK1 closings,
Vflash meets storage capacitance C1 and C2 top crowns with VREF- signals, and CLK1 openings make MOS phase inverters M1 be connected to form partial pressure with M2
Vcm, the partial pressure are connected in the form of common-mode voltage with C1, C2 capacitance negative plate, by Vflash signal samplings to inverter input.
In the stage of holding, K2, K4 and CLK1 are closed, and K1 and K3 is opened, and Vin signals and 0.5LSB signals are transferred to the input of phase inverter
End, simultaneously~CLK1 are opened for inhibiting generated leakage charge in CLK1 closing courses, and such Vin signals are kept by sampling
In inverter input, by the amplification of CMOS inverter, output end vo ut is transferred to, sampling is completed and keeps work.
Vflash is the comparison voltage in Flash ADC in Fig. 4, and by taking 4 ADC as an example, Vflash voltages are respectivelyVoltage varieties of the Δ Vx for CMOS inverter input port, Vcm CMOS
The common-mode voltage that phase inverter input and output short circuit is formed, Cp are mos capacitance value formed by M3.
By can be calculated sampling holding stage (Cp is much smaller than C)
△ Vx=Vx-Vcm (2)
It can be obtained by (1), (2)
△ Vout=-A* △ Vx (4)
A is the gain of CMOS inverter, has thus obtained sampled voltage, while carried out A times to sampled voltage and amplified.
Compare latch cicuit (Fig. 5) and include two input terminals VIN＆OUT1, VIN＆OUT2, output terminal VOUT, M33 and M34
The CMOS inverter that CMOS inverter, the M35 formed is concatenated with M36 is concatenated, the positive-feedback circuit that M37 and M38 is linked to be is opened
Close pipe M31, M32, M39~M42.The comparator that the present invention is formed using two CMOS inverter input and output interconnections, with reference to
The positive feedback that PMOS tube is formed improves the operating rate of original comparator configuration, is formed using switching tube M39~M42 dynamic
State clock latch technique reduces the dynamic power consumption of entire comparator, and height is realized by increasing less device and chip area
Fast comparing function.
Comparing latch cicuit operation principle is：In comparison phase, CLK2 and~CLK2 is opened prior to CLK3, VIN＆OUT1 with
VIN＆OUT2 signals enter after comparator is compared, CLK3 is opened completed by M07 with the positive feedback effect of M08 compared with and it is defeated
Go out comparison result；In non-comparison phase, CLK2 ,~CLK2, CLK3 are closed, and entire comparator is off state, are reduced entire
The power consumption of comparator.
Fig. 6 is sampling hold circuit and compares latch complete circuit.The circuit equally samples holding electricity by using two-stage
Road is sampled and is amplified to input signal, is sent to the input terminal of comparator after amplification and common mode electrical level is compared output ratio
Relatively result.Common mode electrical level is equally designed based on inverter structure, is omitted and is generated common mode electrical level using peripheral circuit, effectively reduces
Chip design difficulty.Due to the PMOS tube and NMOS of the phase inverter in sampling hold circuit and the phase inverter for forming common mode electrical level
Pipe must have identical breadth length ratio ratio, and phase inverter of the phase inverter with forming common mode electrical level in the sampling hold circuit of the second level
PMOS tube uses identical breadth length ratio with NMOS tube, then they just have identical overturning point, effective to reduce
Influence caused by offset voltage can effectively improve entire sampling and keep and the precision of comparison circuit.
Present invention full utilization phase inverter realizes sampling as main body circuit and keeps and compare latch function.Compare tradition
Adopt guarantor using what difference amplifier was formed and compare that latch cicuit structure is simpler, the chip area smaller of occupancy, and more
It is easily achieved.
Simulating, verifying
Border should be in 8 bit A/D converters in this of the invention tangible secondary design, and Fig. 8 is that the sampling based on 8 bit A/D converters is protected
Hold functional verification waveform.Vin is sinusoidal input signal, frequency=79.7119140625KHz, offset voltage 2.5V, the amplitude of oscillation
2.5V.Vout is output waveform, by waveform it can be seen that the sampling that this sampling hold circuit realizes 8 bit A/D converters is kept
Function.
Fig. 9 is the simulation waveform of the present invention relatively latch cicuit.It exports result in the comparison in input signal crosspoint
Latch stage is overturn, and there is no sluggish or leading effect, is truly realized and is compared at a high speed and latching process.
Figure 10 is the simulation waveform verification result of 8 bit pad designed by the invention, realizes adopting for AD converter
Sample keeps function.In this 8 bit A/D converter：THD reaches 43.073dB (fs=80KHz), ENoB=6.862.
18 bit A/D converter print measured result designed by the invention of table
From Fig. 8, Fig. 9, Figure 10 and table 1 as can be seen that realizing sampling using the present invention keeps and compare latch function, line
Property error≤0.5LSB, THD≤43.073dB, ENob=6.862.The present invention has the characteristics that simple in structure be easily integrated.
Claims (5)
1. sampling keeps the latch cicuit compared with, which is characterized in that including sampling hold circuit module, compares latch cicuit module
With common mode electrical level inverter modules, the output terminal of sampling hold circuit module and common mode electrical level inverter modules is connected respectively to ratio
Compared with two input terminals of latch cicuit module.
2. sampling as described in claim 1 keeps the latch cicuit compared with, which is characterized in that the sampling hold circuit module
Including：
First input end is connected to the anode of the first capacitance (C1) by the first gating switch (K1)；
Second input terminal is connected to the anode of the first capacitance (C1) by the second gating switch (K2)；
Third input terminal is connected to the anode of the second capacitance (C2) by third gating switch (K3)；
4th input terminal is connected to the anode of the second capacitance (C2) by the 4th gating switch (K4)；
The cathode of first capacitance (C1) and the cathode of the second capacitance (C2) connect the input terminal of the first CMOS inverter；
The input terminal of first CMOS inverter connects the source electrode and drain electrode of the 23rd metal-oxide-semiconductor (M23), the first CMOS inverter
The anode of output termination third capacitance (C3)；
The input terminal of first CMOS inverter is also connected with the current input terminal of the 24th metal-oxide-semiconductor (M24)；
The anode of the current output terminal connection third capacitance (C3) of 24th metal-oxide-semiconductor (M24)；
The cathode of third capacitance (C3) connects the input terminal of the second CMOS inverter；
The input terminal of second CMOS inverter connects the source electrode and drain electrode of the 27th metal-oxide-semiconductor (M27), the second CMOS inverter
Output terminal connects the first reference point by the 5th gating switch (K5)；
The input terminal of second CMOS inverter is also connected with the current input terminal of the 28th metal-oxide-semiconductor (M28)；
The current output terminal of 28th metal-oxide-semiconductor (M28) connects the output terminal of the second CMOS inverter.
3. sampling as described in claim 1 keeps the latch cicuit with compared with, which is characterized in that first CMOS inverter with
Second CMOS inverter is all made of the metal-oxide-semiconductor of two series connection.
4. sampling as described in claim 1 keeps the latch cicuit compared with, which is characterized in that the relatively latch cicuit module
Including：
31st metal-oxide-semiconductor (M31), current input terminal welding system high level, input terminal of the grid end as second clock,
Current output terminal connects the current input terminal of the 33rd metal-oxide-semiconductor (M33) and the current input terminal of the 35th metal-oxide-semiconductor (M35)；
32nd metal-oxide-semiconductor (M32), current input terminal connect the current output terminal and the 36th of the 34th metal-oxide-semiconductor (M34)
The current output terminal of metal-oxide-semiconductor (M36), current output terminal ground connection, non-inverting signal input thereof of the grid end as second clock；
33rd metal-oxide-semiconductor (M33), grid end connect the first reference point, and current output terminal connects the 34th metal-oxide-semiconductor (M34)
The grid end of current input terminal, the grid end of the 35th metal-oxide-semiconductor (M35) and the 36th metal-oxide-semiconductor (M36)；
34th metal-oxide-semiconductor (M34), grid end connect the first reference point, and current input terminal also connects the second reference point；
35th metal-oxide-semiconductor (M35), current output terminal connect the current output terminal of the 41st metal-oxide-semiconductor (M41), and electric current is defeated
Outlet is also connect with the first reference point；
36th metal-oxide-semiconductor (M36), current input terminal connect the current output terminal of the 41st metal-oxide-semiconductor (M41), and grid end connects
The grid end of 35th metal-oxide-semiconductor (M35), grid end also connect the second reference point.
37th metal-oxide-semiconductor (M37), current input terminal welding system high level VDD, current output terminal connect the 41st metal-oxide-semiconductor
(M41) current input terminal, grid end connect third reference point；
38th metal-oxide-semiconductor (M38), current input terminal welding system high level VDD, current output terminal connect third reference point, grid
Terminate the current output terminal of the 37th metal-oxide-semiconductor (M37)；
39th metal-oxide-semiconductor (M39), grid end connect third input end of clock, current input terminal welding system high level VDD, electricity
The grid end of stream output the 37th metal-oxide-semiconductor (M37) of termination；
40th metal-oxide-semiconductor (M40), grid end connect third input end of clock, current input terminal welding system high level VDD, electric current
The grid end of output the 38th metal-oxide-semiconductor (M38) of termination；
41st metal-oxide-semiconductor (M41), grid end connect third input end of clock；
42nd metal-oxide-semiconductor (M42), grid end connect third input end of clock, and current output terminal connects the second reference point, electric current
Input termination third reference point；
Third reference point is connected to final output end by a phase inverter.
5. sampling as described in claim 1 keeps the latch cicuit compared with, which is characterized in that the common mode electrical level phase inverter mould
Block is made of the 29th metal-oxide-semiconductor (M29) connected and the 30th metal-oxide-semiconductor (M30), the 29th metal-oxide-semiconductor (M29) and the 30th
The grid of metal-oxide-semiconductor (M30), which is connected on, to be connected in series with a little, is connected in series with and is a little connected to the second reference by the 6th gating switch (K6)
Point, it is described to be connected in series with a little as the input of the electric current of the current output terminal of the 29th metal-oxide-semiconductor (M29) and the 30th metal-oxide-semiconductor (M30)
The tie point at end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711483543.3A CN108233931B (en) | 2017-12-29 | 2017-12-29 | Sample-hold and compare latch circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711483543.3A CN108233931B (en) | 2017-12-29 | 2017-12-29 | Sample-hold and compare latch circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108233931A true CN108233931A (en) | 2018-06-29 |
| CN108233931B CN108233931B (en) | 2021-08-24 |
Family
ID=62646210
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711483543.3A Active CN108233931B (en) | 2017-12-29 | 2017-12-29 | Sample-hold and compare latch circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108233931B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111900986A (en) * | 2020-08-10 | 2020-11-06 | 中国电子科技集团公司第二十四研究所 | Follow-up hold switch circuit |
| CN112234948A (en) * | 2020-10-26 | 2021-01-15 | 成都华微电子科技有限公司 | High-speed high-linearity time-interleaved dynamic operational amplifier circuit |
| CN112309880A (en) * | 2020-02-17 | 2021-02-02 | 成都华微电子科技有限公司 | Chip edge damage detection method and circuit |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101232286A (en) * | 2007-01-25 | 2008-07-30 | 夏普株式会社 | A/D converter |
| CN101883211A (en) * | 2010-03-11 | 2010-11-10 | 香港应用科技研究院有限公司 | Use the optics black level of the optical pickocff of open loop sampling correcting amplifier to eliminate |
| US20140085122A1 (en) * | 2012-09-27 | 2014-03-27 | Electronics And Telecommunications Research Institute | Successive approximation register analog-to-digital converter |
| CN104731425A (en) * | 2013-12-23 | 2015-06-24 | 联阳半导体股份有限公司 | Capacitor Sensor Circuit |
| CN104901700A (en) * | 2015-05-12 | 2015-09-09 | 清华大学 | Fully digital Sigma-Delta modulator based on phase inverter |
| US20170352418A1 (en) * | 2015-07-29 | 2017-12-07 | Nantero, Inc. | Ddr compatible open array achitectures for resistive change element arrays |
-
2017
- 2017-12-29 CN CN201711483543.3A patent/CN108233931B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101232286A (en) * | 2007-01-25 | 2008-07-30 | 夏普株式会社 | A/D converter |
| CN101883211A (en) * | 2010-03-11 | 2010-11-10 | 香港应用科技研究院有限公司 | Use the optics black level of the optical pickocff of open loop sampling correcting amplifier to eliminate |
| US20140085122A1 (en) * | 2012-09-27 | 2014-03-27 | Electronics And Telecommunications Research Institute | Successive approximation register analog-to-digital converter |
| CN104731425A (en) * | 2013-12-23 | 2015-06-24 | 联阳半导体股份有限公司 | Capacitor Sensor Circuit |
| CN104901700A (en) * | 2015-05-12 | 2015-09-09 | 清华大学 | Fully digital Sigma-Delta modulator based on phase inverter |
| US20170352418A1 (en) * | 2015-07-29 | 2017-12-07 | Nantero, Inc. | Ddr compatible open array achitectures for resistive change element arrays |
Non-Patent Citations (3)
| Title |
|---|
| M.SUÁREZ: "《Offset-compensated comparator with full-input range in 150nm FDSOI CMOS-3D technology》", 《2010 FIRST IEEE LATIN AMERICAN SYMPOSIUM ON CIRCUITS AND SYSTEMS (LASCAS)》 * |
| MAURO SANTOS: "《Logarithmic AD Conversion Using Latched Comparators and a Time-to-Digital Converter》", 《MAURO SANTOS，2014 21ST IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS)》 * |
| YOUNG-HWA KIM: "《A time-based successive approximation register analog-to-digital converter using a pulse width modulation technique with a single capacitor》", 《2009 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC)》 * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112309880A (en) * | 2020-02-17 | 2021-02-02 | 成都华微电子科技有限公司 | Chip edge damage detection method and circuit |
| CN112309880B (en) * | 2020-02-17 | 2023-05-19 | 成都华微电子科技股份有限公司 | Chip edge damage detection method and circuit |
| CN111900986A (en) * | 2020-08-10 | 2020-11-06 | 中国电子科技集团公司第二十四研究所 | Follow-up hold switch circuit |
| CN112234948A (en) * | 2020-10-26 | 2021-01-15 | 成都华微电子科技有限公司 | High-speed high-linearity time-interleaved dynamic operational amplifier circuit |
| CN112234948B (en) * | 2020-10-26 | 2022-09-06 | 成都华微电子科技股份有限公司 | High-speed high-linearity time-interleaved dynamic operational amplifier circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108233931B (en) | 2021-08-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104124972B (en) | 10-bit ultra-low-power successive approximation register analog-to-digital converter based on charge redistribution | |
| CN206164507U (en) | Successive approximation type adc with segmentation capacitor array | |
| CN106130557B (en) | A kind of comparator imbalance voltage self-correcting positive circuit | |
| CN104967451B (en) | Gradual approaching A/D converter | |
| CN103095302B (en) | A kind of sampling hold circuit being applied to high-speed, high precision circuit | |
| CN111049525B (en) | Superspeed successive approximation type analog-to-digital converter | |
| CN102142840B (en) | Folding analog-to-digital converter | |
| CN107070455A (en) | Mix successive approximation register analog-digital converter and the method for performing analog-to-digital conversion | |
| CN101197559B (en) | Shared amplifier circuit | |
| CN104124971B (en) | Two-stage flow-line modulus converter based on Approach by inchmeal principle | |
| CN108233931A (en) | Sampling keeps the latch cicuit compared with | |
| CN106330184B (en) | A kind of current steer type DAC based on dynamic error alignment technique | |
| CN103178813B (en) | Low-offset full-motion comparator | |
| CN103905046B (en) | A kind of 9 grade of ten bit stream waterline adc circuit | |
| CN106067817A (en) | 1.5 redundancy bits based on controlled asymmetric dynamic comparator accelerate gradual approaching A/D converter | |
| CN100428631C (en) | Method for reducing analog-digital converter capacitance mismatch error based on capacitance match | |
| CN104168025B (en) | A kind of charge type streamline gradual approaching A/D converter | |
| CN106921391A (en) | System-level error correction SAR analog-digital converters | |
| WO2022032987A1 (en) | Follow-hold switch circuit | |
| CN108347234A (en) | high-speed comparator circuit based on inverter design | |
| CN107947792A (en) | A kind of low-power consumption SAR ADC control logic circuits | |
| CN103944571B (en) | High-speed configurable assembly line analog-to-digital converter | |
| CN110034762A (en) | A kind of adjustable analog-digital converter of sample frequency | |
| Lotfi et al. | A 1-V MOSFET-only fully-differential dynamic comparator for use in low-voltage pipelined A/D converters | |
| CN110943726A (en) | Multi-channel multi-stage parallel ultra-high-speed sample hold circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: No. 2201 and 2301, floor 22-23, building 1, No. 1800, middle section of Yizhou Avenue, high tech Zone, China (Sichuan) pilot Free Trade Zone, Chengdu, Sichuan 610041 Patentee after: Chengdu Hua Microelectronics Technology Co.,Ltd. Address before: 610000 22 / F, building 1, No. 1800, middle section of Yizhou Avenue, hi tech Zone, Chengdu City, Sichuan Province Patentee before: CHENGDU SINO MICROELECTRONICS TECHNOLOGY Co.,Ltd. |