CN112309880A - Chip edge damage detection method and circuit - Google Patents
Chip edge damage detection method and circuit Download PDFInfo
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- CN112309880A CN112309880A CN202010097825.5A CN202010097825A CN112309880A CN 112309880 A CN112309880 A CN 112309880A CN 202010097825 A CN202010097825 A CN 202010097825A CN 112309880 A CN112309880 A CN 112309880A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
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Abstract
The invention belongs to the field of integrated circuits, and is used for monitoring whether the edge of a chip (Die) cut by a wafer is damaged in real time and reporting an alarm. According to the invention, chip edge routing is arranged at the edge of a chip before the chip is cut, and the chip edge routing comprises a resistor and a metal wire which are connected in series; the edge of the chip is surrounded by a section of chip edge routing, or is surrounded by a plurality of sections of chip edge routing relays; and detecting the on-off of the chip edge wiring after the chip is cut, and if the chip edge wiring is disconnected, knowing that the chip edge provided with the chip edge wiring is damaged. The invention can judge the physical damage of the chip caused by the heat, stress and other reasons in the wafer cutting process or the use process in time and sense whether the edge of the chip is broken or not. So as to facilitate the processes of screening, chip replacement and the like.
Description
Technical Field
The invention belongs to the field of integrated circuits, and is used for monitoring whether the edge of a chip (Die) cut by a wafer is damaged in real time and reporting an alarm.
Background
In the integrated circuit packaging process, a processed wafer needs to be cut into rectangular or square blocks, which is called wafer Dicing (Die saw) and is sometimes called Dicing (Dicing). Individual chips may be produced on a wafer in the range of tens to thousands, and the purpose of dicing is to cut each individual chip from the entire wafer by means of a diamond blade rotating at high speed in preparation for the subsequent process.
The gap between the chips for dicing is called a dicing channel (dicing channel), and also becomes a scribe line (scribe line), saw lane (saw channel), or street (street). The width of the cutting channel (scriber width) reserved should be larger than the width (kerf) of the cutting trace of the diamond cutting blade.
If impurity particles are mixed in cutting liquid, cleaning liquid and the like used in the chip cutting process, or the size of a cutting tool bit is not selected reasonably, or the design of a cutting channel between chips is not designed reasonably, the chips can be damaged. However, if the chip damage is small, the "bad chip" cannot be selected during chip detection, and the hidden damage is increased due to the action of heat, stress and the like during long-term use of the "bad chip", so that the chip functions abnormally.
Disclosure of Invention
In view of this, the present invention is directed to detecting whether cracks exist around a chip, and reporting an alarm when cracks exist around the chip.
In order to solve the technical problem, the invention provides a chip edge damage detection method, which comprises the steps that chip edge routing is arranged on the edge of a chip before chip cutting, and the chip edge routing comprises a resistor and a metal wire which are connected in series; the edge of the chip is surrounded by a section of chip edge routing, or is surrounded by a plurality of sections of chip edge routing relays; and detecting the on-off of the chip edge routing after the chip is cut, and if the chip edge routing is disconnected, knowing that the chip edge provided with the chip edge routing is damaged.
Furthermore, the chip comprises N metal layers, wherein N is a natural number, and the metal wires routed at the edge of the chip comprise metal wires arranged on all metal layers or part of metal layers at the edge of the chip.
Further, the resistor of the chip edge routing is manufactured by one or more resistor processes of a Poly resistor manufacturing process, an N trap resistor manufacturing process, a P + resistor manufacturing process and an N + resistor manufacturing process.
The invention also provides a chip edge damage detection circuit which is characterized by comprising a chip edge routing and a detection module, wherein the chip edge routing is arranged along the edge of the chip and comprises a resistor and a metal wire which are connected together in series; the edge of the chip is surrounded by a section of chip edge routing, or is surrounded by a plurality of sections of chip edge routing relays; the detection circuit is used for detecting the on-off of the chip edge routing, and if the chip edge routing is detected to be disconnected, the chip edge damage of the chip edge routing of the section of chip edge routing is judged and an alarm is given;
furthermore, the chip comprises N metal layers, wherein N is a natural number, and the metal wires routed at the edge of the chip comprise metal wires arranged on all metal layers or part of metal layers at the edge of the chip.
Furthermore, the chip edge wiring, the current source and the switch tube are connected in series and then connected between a power supply VDD and a ground GND, the positions of the chip edge wiring, the current source and the MOS tube can be exchanged, and one end of the chip edge wiring, which can indicate whether the voltage drop is normal or not, is sent to the first input end of the comparator; the enabling end of the comparator and the control end of the switch tube are connected with an enabling signal EN, the second input end of the comparator is connected with a reference voltage, and the reference voltage is used for distinguishing the voltage drop when the wiring at the edge of the chip is normal and the voltage drop when the wiring is damaged;
the enabling signal EN controls a path from a power supply VDD to a ground GND through the edge annular wiring of the chip by the switching tube, and power consumption is reduced by enabling control of the comparator; when EN is high level, the switching tube is conducted, the comparator is enabled, and the detection module works normally; when the enable signal EN is at a low level, the switching tube is turned off, the comparator is turned off, the detection module is turned off and does not work;
the current source provides current I, and the current I flows through the edge annular wiring of the chip to generate voltage drop; when the chip edge is normal, the input voltage of the first input end of the comparator is compared with the reference voltage of the second input end of the comparator, and then a signal representing that the chip edge is normal is output; when the chip edge is damaged, the voltage of the first input end of the comparator is compared with the reference voltage of the second input end of the comparator to output a signal representing the chip edge damage.
Further, the detection module is integrated in the chip; the signal representing the chip edge damage is sent to the chip as an alarm signal, or is remotely output to a control center for alarm through a network after being processed; the switch tube is an MOS tube, one end of the chip edge wiring is connected with a power supply VDD, and the other end of the chip edge wiring is connected with the input end of a current source and the first input end of the comparator; the output end of the current source is connected with the drain electrode of the MOS tube, the grid electrode of the MOS tube is connected with an enable signal EN, and the source electrode of the NMOS tube is grounded GND; the resistance is one or more of Poly resistance, N trap resistance, P + resistance and N + resistance.
Advantageous effects
The invention can judge the physical damage of the chip caused by the heat, stress and other reasons in the wafer cutting process or the use process in time and sense whether the edge of the chip is broken or not. So as to facilitate the processes of screening, chip replacement and the like.
Drawings
FIG. 1 is a top view of a chip edge damage detection circuit location with an uncut chip;
FIG. 2 is a cross-sectional view of a main level of a chip;
FIG. 3 is a schematic diagram of the detection of the edge damage detection circuit of the chip, wherein (a) is when the edge of the chip is normal, and (b) is when the edge of the chip is abnormal;
FIG. 4 is a diagram of an equivalent circuit structure of a chip edge damage detection circuit according to an embodiment of the present invention;
Detailed Description
The following describes in detail embodiments of the present invention with reference to the drawings.
The relationship of the chip edge damage detection circuit location to the uncut chip is shown in fig. 1. The chip edge ring-shaped wiring is placed along the chip edge, and for each chip, only one chip edge ring-shaped wiring and one corresponding detection circuit are needed, or multiple sections of chip edge wiring and corresponding detection circuits are needed, namely the chip edge ring-shaped wiring can be used in a segmented mode, for example, four sections of chip edge wiring are arranged on the periphery of the chip respectively, and one section of chip edge wiring is arranged on each side.
A cross-sectional view of the main level of the chip is shown in fig. 2. The chip edge ring-shaped wire is mainly composed of a resistor and a metal wire. The chip integrated resistors are mainly classified into 4 types according to the difference of the levels of the formed resistors: poly resistance, N well resistance, P + resistance (P-plus resistance), N + resistance (N-plus resistance). The resistor of the chip edge ring-shaped routing can be composed of one or more of the resistors so as to detect whether the silicon-based part of the chip is broken or damaged.
The annular routing at the edge of the chip can also continue to be connected with the metal layer routing in series so as to detect whether the metal layer of the chip is broken or damaged. The number of metal layers is different according to chip design, from the metal layer 1 and the metal layer 2 to the metal layer N, wherein N is the maximum number of metal layers. The ring-shaped routing at the edge of the chip can be connected with all metal layer routing or part of the metal layer routing in series, namely, the ring-shaped routing is wound for a plurality of circles along the edge of the chip by using different layers and is finally connected in series to form a signal routing. In this case, the chip edge ring trace is formed by connecting a plurality of metal traces in series. The resistor is connected with the multilayer metal wires in series, so that whether a certain layer of the chip is broken or not can be sensed.
The detection principle of the chip edge damage detection circuit is shown in fig. 3. The circular routing at the edge of the chip can be equivalent to a resistor R with a known resistance value when the edge of the chip is normal, and can be equivalent to a resistor R' which is theoretically close to infinity when the edge of the chip is abnormal, namely when the edge of the chip is broken.
The detection circuit detects the equivalent resistance of the annular wiring at the edge of the chip to obtain a chip edge damage detection output signal. One embodiment of the chip edge damage detection circuit of fig. 3 is shown in fig. 4.
In this embodiment, VDD is the operating power supply for the chip edge damage detection circuit. EN is an enable signal of the chip edge damage detection circuit. One end of the chip edge wiring is connected with a power supply VDD, and the other end of the chip edge wiring is connected with the current source input end and the first input end of the comparator; the output end of the current source is connected with the drain electrode of the NMOS tube, the grid electrode of the NMOS tube is connected with an enable signal EN, and the source electrode of the NMOS tube is grounded GND; the enable end of the comparator is connected with an enable signal EN, and the second input end of the comparator is connected with a reference voltage. The path of the equivalent resistance R (or resistance R') of the chip edge ring trace from the power supply VDD to the ground GND is controlled by the NMOS transistor M1. And power consumption is reduced by enabling control of the comparator. When EN is high level, namely logic '1', the NMOS tube M1 is conducted, the comparator is enabled, and the detection circuit works normally; when EN is low level, i.e. logic "0", the NMOS transistor M1 is turned off, the comparator is turned off, the detection circuit is turned off, and the operation is not performed.
The position of the NMOS transistor M1 controlled by the enable signal EN can be exchanged with the position of the current source or the ring wire of the chip, or replaced by other types of switch transistors such as PMOS transistors. The positions of the current source and the edge ring trace of the chip can be switched. When the chip edge wiring is normal, the voltage drop is different from that when the chip edge wiring is damaged, one end of the chip edge wiring, which can indicate whether the voltage drop is normal, is selected to be connected with a comparator, and the reference voltage input by the other end of the comparator is used for distinguishing the voltage drop when the chip edge wiring is normal from the voltage drop when the chip edge wiring is damaged.
The current source provides a current I, and the current I flows through the equivalent resistor R of the annular routing at the edge of the chip to generate voltage drop.
In the embodiment shown in fig. 4, when the chip edge is normal, the voltage Va at the input terminal a of the comparator is VDD-I × R. The other end of the comparator is inputted with a reference level Vref. The reasonable current I, the chip edge annular routing equivalent resistor R and the reference level Vref are designed, so that Va is greater than Vref, and the chip edge damage detection output signal is low level, namely logic '0', which indicates that the chip edge is normal.
When the chip edge is damaged, the voltage Va at the comparator input terminal a is VDD-I R ', R ' is theoretically close to infinity, and the voltage Va at the comparator input terminal a is VDD-I R ' and is approximately 0. At this time, Va < Vref, so the chip edge damage detection output signal is high, i.e., logic "1", indicating that there has been damage to the chip edge. At this time, the edge damage detection output signal may be reported to the logic portion of the chip as an alarm signal.
The chip edge damage detection circuit performs identification on the normality or abnormality of the chip edge by the method to obtain an edge damage detection output signal and report an alarm.
The chip edge damage detection circuit can be used for judging the physical damage of the chip caused by heat, stress and the like in the wafer cutting process or the use process.
The chip edge damage detection circuit outputs signals, can provide alarm signals for a logic circuit of the chip, and can remotely output the alarm signals to a control center through a network after the alarm signals are processed by upper-layer logic and software.
The present invention is not limited to the above preferred embodiments, and any modifications, equivalents, improvements, etc. made within the principle of the present invention are included in the scope of the present invention.
Claims (10)
1. A chip edge damage detection method is characterized by comprising the following steps,
chip edge routing is arranged at the edge of the chip before chip cutting, and the chip edge routing comprises a resistor and a metal wire which are connected in series; the edge of the chip is surrounded by a section of chip edge routing, or is surrounded by a plurality of sections of chip edge routing relays;
and detecting the on-off of the chip edge routing after the chip is cut, and if the chip edge routing is disconnected, knowing that the chip edge provided with the chip edge routing is damaged.
2. The method for detecting chip edge damage according to claim 1, wherein the chip includes N metal layers, N is a natural number, and the metal lines routed at the chip edge include metal lines disposed on all or a part of the metal layers at the chip edge.
3. The method for detecting chip edge damage according to claim 1 or 2, wherein the resistor of the chip edge trace is manufactured by one or more of a Poly resistor manufacturing process, an N-well resistor manufacturing process, a P + resistor manufacturing process, and an N + resistor manufacturing process.
4. A chip edge damage detection circuit is characterized by comprising a chip edge routing line and a detection module, wherein the chip edge routing line is arranged along the edge of a chip and comprises a resistor and a metal wire which are connected in series; the edge of the chip is surrounded by a section of chip edge routing, or is surrounded by a plurality of sections of chip edge routing relays; the detection circuit is used for detecting the on-off of the chip edge wiring, and if the chip edge wiring is detected to be disconnected, the chip edge damage of the chip edge wiring arranged on the section of chip edge wiring is judged and an alarm is given.
5. The chip edge damage detection circuit of claim 4, wherein the chip comprises N metal layers, N is a natural number, and the metal lines routed at the chip edge comprise metal lines disposed at all or a portion of the metal layers at the chip edge.
6. The chip edge damage detection circuit of claim 4 or 5, wherein the detection module comprises a switch tube, a comparator and a current source; the chip edge routing, the current source and the switch tube are connected in series and then connected between a power supply VDD and a ground GND, the positions of the chip edge routing, the current source and the MOS tube can be exchanged, and one end of the chip edge routing, which can indicate whether the voltage drop is normal or not, is sent to a first input end of the comparator; the enabling end of the comparator and the control end of the switch tube are connected with an enabling signal EN, the second input end of the comparator is connected with a reference voltage, and the reference voltage is used for distinguishing the voltage drop when the wiring at the edge of the chip is normal and the voltage drop when the wiring is damaged;
the enabling signal EN controls a path from a power supply VDD to a ground GND through the edge annular wiring of the chip by the switching tube, and power consumption is reduced by enabling control of the comparator; when EN is high level, the switching tube is conducted, the comparator is enabled, and the detection module works normally; when the enable signal EN is at a low level, the switching tube is turned off, the comparator is turned off, the detection module is turned off and does not work;
the current source provides current I, and the current I flows through the edge annular wiring of the chip to generate voltage drop; when the chip edge is normal, the input voltage of the first input end of the comparator is compared with the reference voltage of the second input end of the comparator, and then a signal representing that the chip edge is normal is output; when the chip edge is damaged, the voltage of the first input end of the comparator is compared with the reference voltage of the second input end of the comparator to output a signal representing the chip edge damage.
7. The chip edge damage detection circuit of claim 6, wherein the detection module is integrated into the chip.
8. The chip edge damage detection circuit of claim 6, wherein the signal indicative of chip edge damage is sent to the chip as an alarm signal or is processed and remotely output to a control center via a network for alarm.
9. The chip edge damage detection circuit of claim 6, wherein the switch transistor is an MOS transistor, one end of the chip edge trace is connected to a power supply VDD, and the other end of the chip edge trace is connected to the current source input terminal and the first input terminal of the comparator; the output end of the current source is connected with the drain electrode of the MOS tube, the grid electrode of the MOS tube is connected with an enable signal EN, and the source electrode of the NMOS tube is grounded GND.
10. The chip edge damage detection circuit of claim 4 or 5, wherein the resistor is one or more of a Poly resistor, an N-well resistor, a P + resistor, and an N + resistor.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010097825.5A CN112309880B (en) | 2020-02-17 | 2020-02-17 | Chip edge damage detection method and circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010097825.5A CN112309880B (en) | 2020-02-17 | 2020-02-17 | Chip edge damage detection method and circuit |
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| CN112309880B CN112309880B (en) | 2023-05-19 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117391043A (en) * | 2023-12-12 | 2024-01-12 | 北京象帝先计算技术有限公司 | Antenna effect detection method, device, electronic equipment and storage medium |
Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001020658A1 (en) * | 1999-09-14 | 2001-03-22 | Alpha Metals, Inc. | Wafer coating method for flip chips |
| US6211277B1 (en) * | 1997-10-03 | 2001-04-03 | Hitachi Chemical Company, Ltd. | Encapsulating material and LOC structure semiconductor device using the same |
| US20050146964A1 (en) * | 2003-11-05 | 2005-07-07 | Fujitsu Limited | Semiconductor integrated circuit |
| WO2008004414A1 (en) * | 2006-07-07 | 2008-01-10 | Sharp Kabushiki Kaisha | Semiconductor device having defect detecting function |
| US20080012572A1 (en) * | 2006-07-13 | 2008-01-17 | Nec Electronics Corporation | Semiconductor device having a function of detection breakages on a periphery thereof |
| US20080035923A1 (en) * | 2006-08-10 | 2008-02-14 | Infineon Technologies Ag | Semiconductor Device With Damage Detection Circuit and Method for Producing the Same |
| KR20090058306A (en) * | 2007-12-04 | 2009-06-09 | 주식회사 동부하이텍 | System for detecting wafer chipping and method for detecting wafer chipping |
| US20130009663A1 (en) * | 2011-07-07 | 2013-01-10 | Infineon Technologies Ag | Crack detection line device and method |
| CN105632911A (en) * | 2016-01-02 | 2016-06-01 | 北京工业大学 | Wafer level package method for reducing edge stress |
| US20170199439A1 (en) * | 2014-07-15 | 2017-07-13 | Huawei Technologies Co., Ltd. | Method for Detecting Substrate Crack, Substrate, and Detection Circuit |
| CN108109930A (en) * | 2016-11-24 | 2018-06-01 | 迈来芯科技有限公司 | The monitoring system of die edge integrality |
| WO2018098773A1 (en) * | 2016-12-01 | 2018-06-07 | 华为技术有限公司 | Timing error detection circuit, trigger and latch |
| CN108233931A (en) * | 2017-12-29 | 2018-06-29 | 成都华微电子科技有限公司 | Sampling keeps the latch cicuit compared with |
-
2020
- 2020-02-17 CN CN202010097825.5A patent/CN112309880B/en active Active
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6211277B1 (en) * | 1997-10-03 | 2001-04-03 | Hitachi Chemical Company, Ltd. | Encapsulating material and LOC structure semiconductor device using the same |
| WO2001020658A1 (en) * | 1999-09-14 | 2001-03-22 | Alpha Metals, Inc. | Wafer coating method for flip chips |
| US20050146964A1 (en) * | 2003-11-05 | 2005-07-07 | Fujitsu Limited | Semiconductor integrated circuit |
| WO2008004414A1 (en) * | 2006-07-07 | 2008-01-10 | Sharp Kabushiki Kaisha | Semiconductor device having defect detecting function |
| US20080012572A1 (en) * | 2006-07-13 | 2008-01-17 | Nec Electronics Corporation | Semiconductor device having a function of detection breakages on a periphery thereof |
| US20080035923A1 (en) * | 2006-08-10 | 2008-02-14 | Infineon Technologies Ag | Semiconductor Device With Damage Detection Circuit and Method for Producing the Same |
| KR20090058306A (en) * | 2007-12-04 | 2009-06-09 | 주식회사 동부하이텍 | System for detecting wafer chipping and method for detecting wafer chipping |
| US20130009663A1 (en) * | 2011-07-07 | 2013-01-10 | Infineon Technologies Ag | Crack detection line device and method |
| US20170199439A1 (en) * | 2014-07-15 | 2017-07-13 | Huawei Technologies Co., Ltd. | Method for Detecting Substrate Crack, Substrate, and Detection Circuit |
| CN105632911A (en) * | 2016-01-02 | 2016-06-01 | 北京工业大学 | Wafer level package method for reducing edge stress |
| CN108109930A (en) * | 2016-11-24 | 2018-06-01 | 迈来芯科技有限公司 | The monitoring system of die edge integrality |
| WO2018098773A1 (en) * | 2016-12-01 | 2018-06-07 | 华为技术有限公司 | Timing error detection circuit, trigger and latch |
| CN108233931A (en) * | 2017-12-29 | 2018-06-29 | 成都华微电子科技有限公司 | Sampling keeps the latch cicuit compared with |
Non-Patent Citations (1)
| Title |
|---|
| 许国君;王剑;曾洁;吴作好;贾世杰;: "基于SPI控制的16路输出开关芯片MC33996的原理及应用" * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117391043A (en) * | 2023-12-12 | 2024-01-12 | 北京象帝先计算技术有限公司 | Antenna effect detection method, device, electronic equipment and storage medium |
| CN117391043B (en) * | 2023-12-12 | 2024-06-21 | 北京象帝先计算技术有限公司 | Antenna effect detection method, device, electronic equipment and storage medium |
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| CN112309880B (en) | 2023-05-19 |
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