JP2000124279A - Semiconductor device applicable to wafer burn-in - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform a correct burn-in test with an IC chip as set, when a disorder takes place at burn-in test and an excessive current flows in a semiconductor device, allowing the excessive current to melt a fuse, so that a test current applied from a power source line is cut off. SOLUTION: A wafer with a power source connected to each IC chip 1 is put in a specified high-temperature atmosphere, and a burn-in test is started. When a disorder takes place in the IC chip 1 during the test, an excessive current flows in a circuit element in the IC chip 1 from a power source line 4 through a proving pad 2. When the current exceeds a pre-set tolerable current of a fuse 5, it melts the fuse 5 and the current flowing into the IC chip 1 from the power source line 4 is cut off. Thus, a correct burn-in test with the IC chip 1 is performed as set.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device having a function of performing a test in a wafer state in one burn-in test of a product test performed in a semiconductor device manufacturing process.

[0002]

2. Description of the Related Art Generally, in a final step of manufacturing a semiconductor device, various tests for checking the quality of manufactured products are performed.

[0003] Among them, a burn-in test, which is a kind of screening test, is performed as a test for finding potential defects or inherent defects of a semiconductor device. This burn-in test is an aging test performed in a high-temperature atmosphere. A constant current or an input signal close to actual operation is applied to each device by applying a power supply voltage of a rated voltage or higher, and the temperature and voltage are reduced. This is a test in which potential defects are intentionally generated by applying stress and selected.

Conventionally, a wafer has been diced into individual chips and then tested individually. In recent years, however, as shown in FIG.
Test power supply line 1 connected to bonding pad 12 inside
3 is formed in a normal manufacturing process. Then, after applying a power supply voltage and performing burn-in, a probe of a test apparatus is applied to the bonding pad 12 to perform a test, so that a burn-in test can be performed for each wafer.

For example, Japanese Patent Application Laid-Open No. 5-55327 discloses that a burn-in power supply line is formed on a wafer provided with a plurality of IC chips so as to cross a die sink (scribe) line. , Each IC
It is connected to the input side of a chip (semiconductor device). By applying an operating voltage to each of the IC chips via the burn-in power supply line, all the IC chips can be efficiently and efficiently subjected to the burn-in test for each wafer in a short time.

In addition, a resistor is provided on the input side of each IC chip to prevent a short circuit when an insulation failure occurs in the IC chip due to a defect, thereby suppressing the influence on other normal IC chips.

[0007]

However, in a configuration in which a burn-in power supply line is formed on each IC chip on a wafer, if an IC chip failure occurs during a burn-in test, an overcurrent is applied to the defective IC chip. There is a risk of flowing. If an overcurrent flows and the load exceeds the allowable output range of the burn-in test device, the device itself stops,
Burn-in test is interrupted on the way.

Further, as described in the above-mentioned publication, even with a configuration in which a resistor is provided for each IC chip, an overcurrent due to a short circuit can be prevented to some extent by the resistor, but a test is performed on the IC chip in which a defect has occurred. As a result, the voltage to be applied to other normal IC chips may be reduced due to the flow of the applied power, and the prescribed test may not be performed.

If a resistor is provided on the input side of each IC chip, unnecessary current consumption is originally performed, and since a large number of IC chips are formed on the entire wafer, the applied voltage becomes high. Is not preferred.

Therefore, according to the present invention, during a burn-in test on a plurality of IC chips formed on a wafer, a test power supply or a signal applied to a defective IC chip is cut off, so that a normal IC chip can be restored. It is an object of the present invention to provide a semiconductor device compatible with wafer burn-in, which can perform the burn-in test as set.

[0011]

According to the present invention, there is provided a semiconductor device comprising a plurality of circuit elements, a scribe line provided therebetween, and a plurality of semiconductor elements formed on a semiconductor substrate. In the apparatus, a test power supply line formed on the scribe line, and probing connected to the power supply line and formed on an input side in the semiconductor device, to which a test terminal of a test apparatus is pressed during a wafer test. And a pad provided in the semiconductor device,
A fuse provided in the middle of wiring for connecting the bonding pad to the circuit element and the probing pad, and when a fault occurs during a burn-in test and an overcurrent flows to the semiconductor device, The present invention provides a semiconductor device that cuts off a test current applied from the power supply line by blowing the fuse with a current.

The semiconductor device having the above-described configuration is provided with a pad and a fuse for use in a test in the middle of the power supply line to the IC chip. Since the probing pad 2 and the internal circuit element are electrically disconnected from each other, the chip 1 cannot perform a normal test, and is determined to be defective.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a configuration of a semiconductor device capable of performing a burn-in test in a wafer state according to an embodiment of the present invention.

The semiconductor device 1 is composed of a plurality of circuit elements, is formed in a large number on a semiconductor substrate (wafer) made of silicon or the like, and is individually chipped by dicing. Hereinafter, in the present embodiment, the semiconductor device is referred to as an IC chip.

In these IC chips 1, probing pads 2 are formed on the input side, and scribe lines 3 are formed.
It is connected to the test power supply line 4 wired above. The probing pad 2 is a pad to which a probe or the like of a test device is pressed during a wafer test.

The probing pad 2 is connected to a bonding pad 7 connected to an internal circuit element via a wiring 6 having a fuse 5 made of polycrystalline silicon, metal or the like which is blown when an overcurrent flows. The standard of the blow of the fuse 5 is, for example, that the fuse 5 is blown when a current of about five times the normal current consumption in the IC chip 1 flows. Of course, if the maximum current amount is strictly defined in the design stage of the IC chip, the device is formed so as to be blown by a current according to the value.

The operation of the semiconductor device having such a configuration when a burn-in test is performed will be described.

First, as in the conventional case, a wafer supplied with power to each IC chip is placed in a predetermined high-temperature atmosphere,
Start the burn-in test.

If a defective product occurs in the IC chip 1 during this test, an overcurrent flows from the power supply line 4 to the circuit element in the chip through the probing pad 2. When the overcurrent exceeds a predetermined allowable current amount of the fuse 5, the fuse 5 is blown and the current flowing from the power supply line 4 to the IC chip 1 is cut off.

Therefore, the blowout of the fuse 5 is electrically interrupted from the power supply line 4, and the burn-in test is interrupted only for the defective IC chip 2.

After the burn-in test, a wafer test is performed using a probe card or the like to further select good products. At this time, the probing pad 2 of each IC chip 1 is used for applying a voltage for the wafer test.

In the case of a normal IC chip 1, the probing pad 2 is connected to an internal circuit element via the wiring 6 and the fuse 5, so that a normal screening test is performed.

In the IC chip 1 in which the fuse 5 has been blown due to an overcurrent during the burn-in test, the test cannot be performed because the probing pad 2 and the internal circuit element are electrically disconnected. It is determined as defective.

As described above, according to the present embodiment,
Since a pad and a fuse for use in the test are provided in the middle of the power supply line to the IC chip, when a burn-in test is performed on each IC chip in a wafer state, only an IC chip which has become defective due to a defect has an overcurrent. It flows and the fuse blows.

As a result, the output of the burn-in test apparatus is not overloaded and does not stop, and the burn-in test for a normal IC chip is performed as set without any drop in the power supply voltage.

Further, since the probing pad is provided exclusively for the test, when the dicing is performed, the mounting is performed on the frame in the packaging process, and the wiring is connected, the pad to be bonded is contacted with the test probe. No damage and no defects.

[0028]

As described above in detail, according to the present invention, when a burn-in test is performed on a plurality of IC chips formed on a wafer, a test power supply and a signal applied to the defective IC chip are supplied. It is possible to provide a semiconductor device corresponding to wafer burn-in that can shut off and perform a burn-in test on a normal IC chip as set.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a semiconductor device capable of performing a burn-in test in a wafer state according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a semiconductor device capable of performing a burn-in test in a wafer state according to a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... IC chip 2 ... Probing pad 3 ... Scribe line 4 ... Power supply line 5 ... Fuse 6 ... Wiring 7 ... Bonding pad 11 ... IC chip 12 ... Probing and shared pad 13 ... Power supply line

Claims (2)

[Claims] 1. A semiconductor device comprising a plurality of circuit elements, a plurality of scribe lines provided therebetween, and a plurality of semiconductor devices formed on a semiconductor substrate, wherein a test power supply formed on the scribe lines is provided. A probing pad connected to the power supply line and formed on an input side in the semiconductor device, to which a test terminal of a test device is pressed during a wafer test; and a circuit element provided in the semiconductor device, And a fuse provided in the middle of a wiring connecting the probing pad to the probing pad. Wherein the fuse is blown to cut off a test current applied from the power supply line. Body apparatus. 2. The fuse of the semiconductor device, wherein an overcurrent for blowing the fuse is one of five times a normal current consumption of the semiconductor device or a value specified in advance when designing the semiconductor device. A semiconductor device corresponding to wafer burn-in according to claim 1.