JP2014033000A - Semiconductor device and testing method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow for determination that a target element has been subjected to stress test.SOLUTION: A monitor MOSFET 2 is formed of a gate insulation film thinner than the gate insulation film of a MOSFET in a target element. The gate insulation film of the monitor MOSFET 2 is formed to be deteriorated or broken, when the monitor MOSFET 2 is subjected to the same stress test as that of the target element. A power supply voltage Va is fed via a disconnection circuit 10 to perform the stress test, and operation of which is turned on/off by an inverter circuit 11. Deterioration state is brought about in the final stage via a normal electrical stress test or burn-in test, and successful implementation of stress test can be confirmed by determining the deterioration state. If the target element is normal, it can be determined as a non-defective product.

Description

  The present invention relates to a semiconductor device and a method for testing a semiconductor device.

  As one of semiconductor devices, a technique for accurately detecting a deterioration state of an integrated circuit, particularly an LSI is provided. In this technique, a monitor circuit having the same configuration as that of the actually used circuit is prepared, and an element equivalent to the actually used circuit is provided. Usually, when the actual circuit is operated, the monitor circuit is also operated at the same time, and this is a technique for detecting the deterioration of the actual circuit by measuring the degree of deterioration of the monitor circuit.

  In such a configuration in which the monitor circuit is provided, the actual use circuit and the monitor circuit are manufactured in the same process, so that an equivalent quality product can be obtained. Can be estimated. As a result, both the actual use circuit and the monitor circuit can be in a situation where the destruction of the oxide film caused by the foreign matter or the like occurs with the same probability.

  In this case, when the monitor circuit deteriorates (fails) due to foreign matter in the burn-in test, it can be said that the thermal and electrical stress due to the burn-in test was sufficient for the initial failure of the oxide film. However, if there is no foreign object in the monitor circuit or the actual circuit, it cannot be determined whether or not the stress test is sufficient to deteriorate the initial failure.

  Therefore, in such a conventional technique, it is impossible to determine from the monitor circuit whether or not the stress of the burn-in test or the high voltage application test has been sufficiently performed. Furthermore, even if there is a defect in the inspection process that prevents sufficient application of stress, or a failure that prevents the electrical stress test itself from being performed due to poor connection, etc., this is detected to determine that the test is defective. There is a problem that can not be.

JP-A-5-243356

  The present invention has been made in consideration of the above circumstances, and the purpose thereof is to confirm that a stress test has been performed for each chip, thereby performing a post-test inspection on the target element for which the stress test has been reliably performed. Another object of the present invention is to provide a semiconductor device having a configuration that can be used and a method for testing the semiconductor device.

  According to the semiconductor device of the first aspect, the target element including the gate oxide film formed on the semiconductor substrate and the gate oxide film having a thickness smaller than the gate oxide film of the target element are provided. A monitor element that deteriorates when subjected to a stress test and a disconnect circuit that can be separated from the monitor element after an electrical stress test are provided.

  As a result, when the electrical stress test is applied to the target element, the same electrical stress test is also performed on the monitor element at the same time, so that the monitor element having a thin gate oxide film is damaged by the stress test. Leading to deterioration or destruction. As a result, the target element that has been subjected to electrical stress at the same time can be determined as an initial defective product if it has deteriorated. It is possible to determine that there is no deterioration after performing a dynamic stress test. After the reliable determination by the monitor element in this way, the monitor element is separated by the disconnection circuit, so that the monitor element as a semiconductor device can be put into a state that does not affect the operation.

  According to the test method for a semiconductor device according to claim 12, a target element including a gate oxide film formed on a semiconductor substrate and a gate oxide film having a thickness smaller than the gate oxide film of the target element are provided. An electrical stress test is performed on a semiconductor device having a monitor element that deteriorates when an electrical stress test is performed on the element and a separation circuit that can be separated after the electrical stress test on the monitor element. Since the monitor element has deteriorated or destroyed after the test, it is possible to determine that the target element that has been subjected to the electrical stress test at the same time is not deteriorated as a normal target element. it can.

Electrical configuration diagram of the first embodiment Schematic cross section of monitor element and target element Example of inspection process of target element and monitor element (1) Example of inspection process of target element and monitor element (part 2) Example of inspection process of target element and monitor element (Part 3) Example of inspection process for target element and monitor element (Part 4) Modification Example of Monitor Element (Part 1) Modification of monitor element (2) Electrical configuration diagram of the second embodiment (part 1) Electrical configuration diagram of the second embodiment (part 2) Electrical configuration diagram of the second embodiment (part 3) Electrical configuration diagram of the second embodiment (part 4) Electrical configuration diagram of the third embodiment Electrical configuration diagram of the fourth embodiment Electrical configuration diagram of fifth embodiment (part 1) Electrical configuration diagram of the fifth embodiment (part 2) Electrical configuration diagram of fifth embodiment (part 3)

(First embodiment)
The first embodiment will be described below with reference to FIGS.
In this embodiment, as shown in FIG. 2, a MOSFET 1 formed integrally with a semiconductor device is assumed as a target element. The target element MOSFET 1 is a semiconductor element incorporated in a circuit within a semiconductor device. A durable semiconductor device remains as a good product after undergoing a stress test before shipment, and a semiconductor device in which an insulating film or the like is broken is defective. Are treated as

  In this semiconductor device, a monitor MOSFET 2 and its peripheral circuit are integrally formed as a monitor element as shown in FIG. In the semiconductor device, for example, a MOSFET 1 and a monitor MOSFET 2 are formed on an SOI (silicon on insulator) substrate. Other elements are also formed in the semiconductor device, but here, the description will focus on the configuration of the target MOSFET 1 as a target element and the monitor MOSFET 2 as a monitor element corresponding thereto.

  In the SOI substrate, a silicon single crystal layer 3 is formed on a support substrate (not shown) via an insulating film, and an element is formed in the silicon single crystal layer 3. The silicon single crystal layer 3 is separated by an insulating film 4 such as a silicon oxide film around the element or circuit to be built. Further, the periphery of each surface from which the silicon single crystal layer 3 is separated is configured to be covered with a field oxide film 5.

  Gate insulating films 6 and 7 made of a silicon oxide film or the like are formed at the center of the upper surface of each silicon single crystal layer 3 of the MOSFET 1 and the monitor MOSFET 2, and a gate electrode 8 made of a polycrystalline silicon film or the like is formed thereon. . The gate insulating film 6 of the MOSFET 1 has a film thickness that can ensure a predetermined breakdown voltage. Further, the gate insulating film 7 of the monitor MOSFET 2 is formed with a film thickness thinner than that of the gate insulating film 6, and has a gate breakdown voltage lower than that of the MOSFET 1, and deteriorates or breaks through a normal stress test described later. Formed as.

  In the stress test, as will be described later, when the MOSFET 1, which is a target element formed in the chip, is an initial defective product, it is actively applied by applying stress (voltage, temperature, time) necessary to break it down. Cause a failure and remove it. In this case, the gate insulating film 7 of the monitor MOSFET 2 is set to an oxide film thickness that is deteriorated or destroyed when subjected to such a stress test. In addition, the thickness of the gate insulating film 7 of the monitor MOSFET 2 is set to be smaller than the minimum film thickness within the range of variation that occurs in the process of forming the gate insulating film 6 of the MOSFET 1.

  The surface having the above structure is formed so as to be covered with the interlayer insulating film 9, and the interlayer insulating film 9 in the contact formation portion of the source / drain region 3a is removed to form a contact. As described above, the monitor MOSFET 2 is provided as the monitor element with respect to the MOSFET 1 as the target element.

  In addition, as shown in FIG. 1, the semiconductor device is provided with a circuit for causing the monitor MOSFET 2 to function. The inverter circuit 10 serving as a disconnecting circuit is a circuit that is provided so that the voltage Va at the time of the stress test is applied to the drain of the monitor MOSFET 2 and is disconnected after the test, and is constituted by a CMOS (complementary MOS) inverter circuit here. . Further, the inverter circuit 11 constituted by CMOS controls the voltage Va applied to the gate of the monitor MOSFET 2.

  The semiconductor device described above is manufactured through a wafer process A1 and an assembly process A2 as manufacturing processes. In the wafer process A1, a wafer such as a silicon substrate is subjected to various processing processes to produce a large number of semiconductor chips as a semiconductor device. In the assembling step A2, a large number of semiconductor chips formed on the wafer are separated and packaged individually. A wafer test T1 is performed during the wafer process A1, and a shipping test T3 is performed in the assembly process A2. Also, a burn-in test T2 or T4, which is one of stress tests, is performed in either the wafer process A1 or the assembly process A2. Through these tests, screening is performed to remove a semiconductor device in which an initial failure or the like occurs.

  These tests are performed, for example, at the timings shown in FIGS. When the process shown in FIG. 3 is adopted, a wafer test T1 is performed at the final stage of the wafer process A1, a burn-in (B / I) test (stress test) T2 is performed at the final stage of the assembly process A2, and finally the shipment is performed. Test T3 is performed. When the process shown in FIG. 4 is employed, a WLBI (wafer level burn in) test (stress test) is performed as a burn-in test after wafer test T1 in wafer process A1.

  In this case, the B / I test T2 performed in the assembling step A2 is performed by inserting individual semiconductor devices assembled in a package into a test connector in a state in which temperature stress is applied by holding the semiconductor device at a high temperature. This is an electrical acceleration test. Further, in the WLBI test T4 performed in the wafer process A1, an electrical acceleration test is performed while applying temperature stress to the individual semiconductor devices in a wafer state in which a large number of chips are formed.

  In the wafer test T1, the test is mainly performed by applying electrical stress to each chip, and in the shipping test T3, the test is performed by applying the same electrical stress for each package. In the stress determination test, it is finally determined that the device has resistance to stress and does not have an initial failure.

  When the process shown in FIG. 5 is adopted, the process is similar to the process of FIG. 3, but in the wafer test T1a, a plurality of electrical stress tests are performed and a stress determination test is also performed. In the shipping test T3a, a plurality of electrical stress tests are performed to perform a final stress determination test. When the process shown in FIG. 6 is adopted, the B / I test T3 is omitted from the process of FIG. 3, and this is a process when no temperature stress is applied.

  In the above-described configuration, when a semiconductor device is manufactured through the processes shown in FIGS. 3 to 6, each formed chip is tested in a wafer state at the final stage of the wafer process A1. In this test, a stress test is set in addition to a normal characteristic measurement for each chip. For example, the test is performed by applying a high voltage to operate the chip. In this stress test, stress is applied to the MOSFET 1 and other circuit elements formed on each chip on the wafer, and the same stress is applied to the monitor MOSFET 2.

  Thereafter, when the manufacturing process shown in FIGS. 3, 5, and 6 is employed, the process proceeds to the assembling process A2. In addition, when the manufacturing process shown in FIG. 4 is adopted, the WLBI test T4 is performed. In the WLBI test T4, stress is applied by applying a high voltage at a high temperature to all chips formed on the wafer. Also in the WLBI test T4, stress is applied to the MOSFET 1 and other circuit elements formed on each chip on the wafer as described above, and the same stress is applied to the monitor MOSFET 2.

  In the assembly process A2, as described above, the semiconductor device is formed through the process of separating the semiconductor chips from the wafer and individually packaging them. In this state, a terminal corresponding to a circuit incorporated in the semiconductor device is connected to the lead of the package, and an electrical signal is exchanged with the outside. Further, each terminal of the monitor MOSFET 2 is connected to a lead of the package in order to apply an electrical stress from the outside.

  At the stage where the assembling process A2 is completed, the B / I test T2 or the shipping test T3 is performed. In the B / I test T2, as in the WLBI test described above, an acceleration stress is applied to each semiconductor device by applying a high voltage in a high temperature atmosphere. In the shipping test T3, various stress tests are performed without increasing the temperature. Then, at the final stage of the shipping test T3, a stress determination test is performed.

  The monitor MOSFET 2 operates in the same manner as the MOSFET 1 and other circuit elements, and when the gate insulating film 7 is in a deteriorated state or a dielectric breakdown state, it can be determined that electrical stress is reliably applied to the chip. As an actual stress test, the monitor MOSFET 2 is operated at a clock speed comparable to that of the MOSFET 1 and other circuit elements, and is connected to the same power supply system Va.

  As a result, when the gate insulating film 7 of the monitor MOSFET 2 is in a deteriorated state or is in a state of being destroyed due to dielectric breakdown or the like, a leakage current flows in the OFF state. As described above, after the gate insulating film 7 of the monitor MOSFET 2 deteriorates or breaks down, the leakage current at the OFF time increases, and after performing a burn-in test or a high voltage application test as a stress test, In the IDDQ (quiescent power supply current) test, the leakage current can be measured to confirm the deterioration state or the destruction state. As a result, it can be determined that sufficient stress is applied to the gate insulating film 6 of the MOSFET 1 and the oxide films of other circuit elements.

  Further, when it is determined that sufficient stress is applied to the MOSFET 1 and other circuit elements as described above, the monitor MOSFET 2 is in a deteriorated state or a destroyed state. 10 disables the monitor MOSFET 2. Specifically, switching is set so that a low level signal is input as the gate signal of the inverter circuit 10. As a result, the power supply line from Va to the monitor MOSFET 2 can be disconnected from the power supply line and connected to the GND level. As a result, the monitor MOSFET 2 that has been deteriorated or broken down in the stress test can be separated from the power supply line Va, and a circuit originally formed in another part can be used as the semiconductor device.

  According to this embodiment, the monitor MOSFET 2 is provided, and the thickness of the gate insulating film 7 is set to be thinner than that of the gate insulating film 6 of the MOSFET 1. By conducting the same stress test on the monitor MOSFET 2 as the electrical stress test of the MOSFET 1 as the target element, the MOSFET 1 is utilized by utilizing the fact that the gate insulating film 7 is easily deteriorated or broken as much as the film thickness is set thin. It can be determined that the electrical stress test has been carried out reliably, and if the MOSFET 1 is deteriorated, it can be determined that it is an initial defective product. It can be determined.

  Since the inverter circuit 10 is provided as the disconnection circuit, a low level gate signal is applied to the inverter circuit 10 to apply the power supply voltage Va to the monitor MOSFET 2 and a high level gate signal is applied to ground the drain of the monitor MOSFET 2 You can switch to the state. As a result, after the monitor MOSFET 2 is used, it can be separated by the inverter circuit 10 so that there is no problem in actual use of the semiconductor device.

Next, variations of the configuration of the monitor MOSFET 2 will be described with reference to FIGS.
FIG. 7A shows a cross-sectional configuration of the monitor MOSFET 12, in which a gate insulating film 13 formed by thinning only the central portion of the gate insulating film 6 equivalent to the MOSFET 1 is provided. The central portion of the gate insulating film 13 has a breakdown voltage comparable to that of the gate insulating film 7, and is formed to a thickness that causes deterioration or dielectric breakdown by undergoing various stress tests through the same manufacturing process. Yes. Thereby, it can be determined that the stress test has been reliably performed.

  FIG. 7B shows a cross-sectional configuration of the monitor MOSFET 14. The gate insulating film 15 is set to have the same film thickness as that of the gate insulating film 6 on one side of the source / drain regions 3 a and 3 a, and the gate insulating film 15 on the other side. It is formed so as to change from one side to the other side so as to have the same film thickness as the film 7.

  FIG. 7C shows a cross-sectional configuration of the monitor MOSFET 16. In this configuration, the protrusion 3 b is formed at the gate portion of the silicon single crystal layer 3. The gate insulating film 17 is formed so as to cover the protrusion 3 b of the silicon single crystal layer 3, and the film thickness of the protrusion 3 b is approximately the same as the film thickness of the gate insulating film 7.

  FIG. 8A shows a cross-sectional configuration of the monitor MOSFET 18. In this configuration, the gate insulating film 19 is set so that one side of the source / drain regions 3 a and 3 a has the same thickness as the gate insulating film 6 and the other side has the same thickness as the gate insulating film 7. It is set and a step is formed in the middle.

  FIG. 8B shows a cross-sectional configuration of the monitor MOSFET 20. In this configuration, a plurality of small protrusions 21 are formed at the gate portion of the silicon single crystal layer 3. The gate insulating film 22 is formed so as to cover the small protrusions 21 of the silicon single crystal layer 3, and the film thickness in the protrusions 3 b is approximately the same as the film thickness of the gate insulating film 7.

  In FIG. 8C, a monitor unit 23 having a structure in which the MOSFET 1 and the monitor MOSFET 2 are formed in one silicon single crystal layer 3 is provided. In this configuration, the silicon single crystal layer 3 separated by the insulating film 4 is widely formed. In this example, the MOSFET 1 and the monitor MOSFET 2 are formed as elements having different oxide film thicknesses in the silicon single crystal layer 3 serving as the same element island, and the monitor MOSFET 2 is used for confirming the execution of the stress test.

  In the modification shown in FIG. 7 and FIG. 8 described above, the gate insulating film of each monitor MOSFET is formed so as to have a film thickness equivalent to that of the gate insulating film 7 of the monitor MOSFET 2. In addition to a simple monitor MOSFET, one or more other monitor MOSFETs having different gate insulating film thicknesses are provided, and different monitor MOSFETs are used depending on the level of the stress test, thereby determining a more accurate stress test application state. You can also

(Second Embodiment)
9 to 12 show a second embodiment, in which a voltage adjusting means is interposed in order to apply a voltage lower than the power supply voltage Va to the power supply path of the monitor MOSFET 2. As the voltage adjusting means, various devices can be applied as will be described below, whereby the voltage applied to the monitor MOSFET 2 can be appropriately adjusted to adjust the stress test conditions.

  9 to 12 show specific configurations of the voltage adjusting means. In FIG. 9, a p-channel MOSFET 24 is provided on the power supply line of the monitor MOSFET 2 in a state where the gate / drain are short-circuited. The p-channel MOSFET 24 as such a voltage adjusting means is provided as a so-called load MOSFET, and functions as a resistance element that is always turned on when a voltage is applied to flow current.

  FIG. 10 shows a configuration in which a resistor 25 is directly interposed in the power supply line of the monitor MOSFET 2. As a voltage adjusting means, a voltage drop is caused by interposing a resistor 25, and a voltage lower by the voltage drop is applied to the monitor MOSFET 2.

11 shows a configuration in which, for example, a series circuit of three diodes 26a to 26c is inserted in the power supply line of the monitor MOSFET 2 as voltage adjusting means. Since the forward voltage V _F of one diode 26a is about 0.7 V, it is possible to voltage adjustment by connecting the diode 26a of the number corresponding to a desired voltage drop in series.

  FIG. 12 shows a configuration in which a Zener diode 27 as voltage adjusting means is inserted into the power supply line of the monitor MOSFET 2. Thereby, the power supply voltage lowered by the Zener voltage Vz by the Zener diode 27 can be applied to the monitor MOSFET 2.

  According to the second embodiment, the p-channel MOSFET 24, the resistor 25, the diodes 26a to 26c, and the Zener diode 27 are provided as voltage adjusting means in the power supply path of the monitor MOSFET 2, so that the monitor can be performed with a simple configuration. The voltage applied to the MOSFET 2 can be adjusted. Thereby, the voltage applied to the monitor MOSFET 2 can be set lower than the voltage Va applied to the MOSFET 1 according to the stress test conditions.

  By providing such voltage adjusting means, the applied voltage is adjusted so as to meet the stress test conditions in consideration of the withstand voltage and durability in relation to the film thickness of the gate insulating film 7 of the monitor MOSFET 2. It can also be used as a means.

  In addition, any of the p-channel MOSFET 24, the resistor 25, the diodes 26a to 26c, and the Zener diode 27 as the voltage adjusting means described above can be used, or they can be provided in combination. Furthermore, it can be used in combination with any configuration of the first embodiment.

(Third embodiment)
FIG. 13 shows the third embodiment. The difference from the first embodiment is that a p-channel MOSFET 28 is provided in the power supply path as a disconnecting circuit instead of the inverter circuit 10. By supplying a low level gate signal to the gate of the MOSFET 28, power is supplied to the monitor MOSFET 2, and by supplying a high level gate signal, the power is cut off and disconnected from the power source.

In this configuration, the p-channel MOSFET 29a is also connected to the gate of the monitor MOSFET 2, and a resistor 29b is provided as a discharge path. In this configuration, a low-level gate signal is applied to the MOSFET 29a to turn it on, so that the monitor MOSFET 2 is turned on by being turned on, and a high-level gate signal is applied to turn off the monitor MOSFET 2.
Even in the third embodiment, the same effects as those in the first embodiment and the second embodiment can be obtained.

(Fourth embodiment)
FIG. 14 shows the fourth embodiment, which is different from the first embodiment in that an inverter circuit 30 including a monitor p-channel MOSFET 30a and an n-channel MOSFET 30b is provided in place of the monitor MOSFET 2. . This is because when the degradation state of the p-channel MOSFET and the n-channel MOSFET is determined as a stress test target, the monitoring MOSFETs 30a and 30b having the same configuration and a thin gate insulating film are provided. This is an attempt to reliably determine the implementation.

  This makes it possible to reliably determine that the stress test has been performed in the same manner even in a CMOS type semiconductor device or a semiconductor device having a configuration in which p-channel MOSFETs and n-channel MOSFETs are mixed.

  When only one of the monitor p-channel MOSFET 30a and the n-channel MOSFET 30b is used as a stress test method, the deterioration of the p-channel MOSFET or the n-channel MOSFET incorporated in the semiconductor device is determined. it can.

(Fifth embodiment)
15 to 17 show a fifth embodiment, which is an embodiment having a configuration in which means for changing the voltage to the gate is provided. In these drawings, the monitor inverter circuit 30 shown in the fourth embodiment is provided.

  In FIG. 15, different power supply voltages Va and Vb (<Va) can be switched as gate inputs of the inverter circuit 30. As a gate input of the inverter circuit 30, an inverter circuit 11 similar to that of the first embodiment is provided in a path for supplying a power supply voltage Va, and a backflow preventing diode 31 is provided. An inverter circuit 32 and a backflow preventing diode 33 are provided in series on the path for supplying the power supply voltage Vb.

With this configuration, when the power supply voltage Va is applied as the gate input of the monitoring inverter circuit 30, the p-channel MOSFET is turned on by setting the gate input of the inverter circuit 11 to a low level. Thus, the gate input of the inverter circuit 30 the forward voltage V _F only down voltage of the diode 31 from the power supply voltage Va is applied. Note that the gate input of the inverter circuit 32 is set to the high level, the p-channel MOSFET is turned off, and the n-channel MOSFET is turned on. However, since the reverse current blocking diode 33 is provided, the gate input is given to the inverter circuit 30. be able to.

On the other hand, when the power supply voltage Vb is applied as the gate input of the monitoring inverter circuit 30, the p-channel MOSFET is turned on by setting the gate input of the inverter circuit 32 to a low level. Thus, the gate input of the inverter circuit 30 the forward voltage V _F only down voltage of the diode 33 from the power supply voltage Vb is applied. The gate input of the inverter circuit 11 is set to the high level, the p-channel MOSFET is turned off, and the n-channel MOSFET is turned on. However, since the reverse current blocking diode 31 is provided, the gate input is given to the inverter circuit 30. be able to.

  In FIG. 16, the voltage adjustment circuit 34 is provided in the power supply path using one power supply voltage Va. The gate input of the inverter circuit 30 gives the power supply voltage Va by switching on and off by the inverter circuit 11. A voltage adjustment circuit 34 is interposed in a path from the output stage of the inverter circuit 11 to the gate input of the inverter circuit 30. In the voltage adjustment circuit 34, diodes 35 and 36 are connected in series in the forward direction in the power feeding direction, and a diode 37 is connected in the forward direction in the reverse direction, that is, in the gate charge discharging direction. Further, as a configuration for adjusting the voltage, a switch 38 for short-circuiting both terminals of the diode 35 is provided.

According to this arrangement, when the set switch 38 to the OFF state, the voltage only drops the voltage of the sum of the forward voltage V _F of the two diodes 35 and 36 is provided as a gate input of the inverter circuit 30. Further, when the set switch 38 to the ON state, the diode 35 is short-circuited state, the forward voltage V _F only down voltage of the diode 36 is applied as the gate input of the inverter circuit 30.

  In the diode 37, the p-channel MOSFET is turned off and the n-channel MOSFET is turned on when an on / off operation signal is input to the inverter circuit 11 to perform a stress test for turning on and off the monitoring inverter circuit 30. Sometimes it functions to discharge the charge stored in the gate from the n-channel MOSFET via the diode 37.

  In FIG. 17, similarly to the above, a single power supply voltage Va is used and a voltage adjustment circuit 39 is provided in the power supply path. The gate input of the inverter circuit 30 gives the power supply voltage Va by switching on and off by the inverter circuit 11. A voltage adjustment circuit 39 is interposed in a path from the output stage of the inverter circuit 11 to the gate input of the inverter circuit 30. The voltage adjustment circuit 39 includes a first voltage dividing circuit 40 and a second voltage dividing circuit 41 that generate different voltages, and activates one of them to give a gate input.

  The first voltage dividing circuit 40 includes voltage dividing resistors 40a and 40b and switches 40c and 40d. The second voltage dividing circuit 41 includes voltage dividing resistors 41a and 41b and switches 41c and 41d. The switches 40c and 40d are turned on, the switches 41c and 41d are turned off to enable the first voltage dividing circuit 40, and the voltage generated in the voltage dividing resistor 40b is supplied as the gate input of the inverter circuit 30 for monitoring. Further, the switches 41c and 41d are turned on, the switches 40c and 40d are turned off to enable the second voltage dividing circuit 41, and the voltage generated in the voltage dividing resistor 41b is given as the gate input of the monitoring inverter circuit 30. .

  Accordingly, by enabling any one of the voltage dividing circuits 40 and 41, a gate input of a different voltage can be given to the monitoring inverter circuit 30, and a discharge path for gate charge can be formed.

  According to the fifth embodiment, the same effect as that of the first embodiment can be obtained, and gate inputs of different voltages can be set for the monitor inverter circuit 30 under various conditions. A stress test can be performed.

  In the configuration of FIG. 15, two different power supply voltages Va and Vb can be applied as gate inputs by the inverter circuits 11 and 32. However, three or more different power supply voltages are set to correspond to each. An inverter circuit can also be provided.

Similarly, in the configuration of FIG. 16, the voltage adjustment circuit 34 has a configuration in which two diodes 35 and 36 are provided. However, a configuration in which three or more diodes are provided may be employed. Further, by providing the switch for short-circuiting the respective diodes, the switches can be changed either providing what stage the forward voltage V _F by turning on and off the, setting this by different voltages as the gate input Can do.

  In the configuration of FIG. 17, the voltage adjustment circuit 39 provided with the two voltage dividing circuits 40 and 41 is provided. However, for the same purpose, a voltage dividing circuit capable of generating three or more different voltages is provided. can do.

(Other embodiments)
In addition, this invention is not limited only to one embodiment mentioned above, It can apply to various embodiment in the range which does not deviate from the summary, For example, it can deform | transform or expand as follows. .

  The gate insulating film of the monitor element such as the monitor MOSFET 2 may be formed to have a film thickness that can be deteriorated by undergoing the same stress test as the stress test of the target element, or to a film thickness that can cause breakdown. It may be formed. It is possible to reliably determine whether the stress test is performed by setting the level so that the deterioration state or the destruction state can be determined.

  Although the monitor MOSFETs 2, 12, 14, 16, 18, and 20 have been exemplified as the monitor elements, other than this, a gate insulating film that is deteriorated or destroyed by performing a stress test on the target element partially or entirely is provided. Thus, the determination operation can be performed reliably.

There are various application methods for the stress test in addition to those shown in the embodiment. In any case, the stress test is performed by determining the deterioration state or the destruction state of the monitor element in the final stage. Can be reliably determined.
Each of the above embodiments can be applied in combination as appropriate, and a composite embodiment can be adopted.

  In the drawings, 1 is a MOSFET (target element), 2, 12, 14, 16, 18, 20 are monitor MOSFETs (monitor elements), 6, 7, 13, 15, 17, 19, 22 are gate insulating films, 10 is Inverter circuit (separation circuit), 11 is an inverter circuit, 24 is a p-channel MOSFET (voltage adjusting means), 25 is a resistor (voltage adjusting means), 26a to 26c are diodes (voltage adjusting means), 27 is a zener diode (voltage) Adjustment means), 28 is a p-channel MOSFET (separation circuit), 30 is an inverter circuit (monitor element), 32 is an inverter circuit, and 34 and 39 are voltage adjustment circuits (application voltage switching means).

Claims (15)

A target element including a gate oxide film formed on a semiconductor substrate;
A monitor element that includes a gate oxide film that is thinner than the gate oxide film of the target element and that deteriorates when subjected to an electrical stress test on the target element;
A semiconductor device comprising: a separation circuit that can be separated from the monitor element after the electrical stress test. The semiconductor device according to claim 1,
2. The semiconductor device according to claim 1, wherein the disconnection circuit includes a voltage application circuit that supplies a high voltage to the monitor element when stress is applied and supplies a low voltage when no stress is applied. The semiconductor device according to claim 2,
The semiconductor device according to claim 1, wherein the disconnecting circuit has a configuration in which voltage adjusting means is interposed in a power supply path from the voltage applying circuit to the monitor element. The semiconductor device according to claim 3.
The semiconductor device according to claim 1, wherein the voltage adjusting means is a load MOSFET. The semiconductor device according to claim 2,
2. The semiconductor device according to claim 1, wherein the separation circuit includes a MOSFET having a conductivity type complementary to the monitor element, and constitutes a monitor inverter circuit. The semiconductor device according to any one of claims 1 to 5,
The semiconductor device according to claim 1, wherein the disconnecting circuit includes an applied voltage switching unit capable of applying a different voltage to the monitor element. The semiconductor device according to claim 6.
The applied voltage switching means is supplied with a different power supply voltage from the outside, selectively switches the power supply voltage, and supplies power to the monitor element. The semiconductor device according to claim 6.
The applied voltage switching means switches the voltage by supplying a power supply voltage supplied from the outside to the monitor element through a diode in the forward direction. The semiconductor device according to claim 6.
The applied voltage switching means includes a plurality of voltage dividing circuits having different terminal voltages, and switches the voltage by supplying a power supply voltage supplied from the outside to the monitor element by switching the plurality of voltage dividing circuits. A semiconductor device. The semiconductor device according to claim 1,
The monitoring device has a structure in which the gate oxide film is formed to be uniformly thinner than the gate oxide film of the target element. The semiconductor device according to claim 1,
2. The semiconductor device according to claim 1, wherein the monitor element has a structure in which the gate oxide film is thinner than the gate oxide film of the target element. The semiconductor device according to claim 1,
2. The semiconductor device according to claim 1, wherein a plurality of the monitor elements having different gate oxide film thicknesses are formed. A target element having a gate oxide film formed on a semiconductor substrate and a monitor element having a gate oxide film thinner than the gate oxide film of the target element and deteriorating when subjected to an electrical stress test on the target element And a test method for a semiconductor device comprising a disconnecting circuit separable after the electrical stress test with respect to the monitor element,
A test method for a semiconductor device, comprising: determining that a stress test has been normally performed on the target element because the monitor element has deteriorated after the stress test. The method for testing a semiconductor device according to claim 13,
A test method for a semiconductor device, comprising performing IDDQ (stationary state power supply current) measurement for detecting that the monitor element is deteriorated. The semiconductor device testing method according to claim 13 or 14,
The stress test is performed as a test in which a plurality of tests are combined in time series,
A test method for a semiconductor device, comprising: determining that a stress test in which a plurality of tests are normally combined with the target element has been performed because the monitor element has deteriorated after the stress test.

Images