JP2013219084A - Semiconductor chip and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor chip that allows identifying the occurrence place of a crack in the semiconductor chip.SOLUTION: A semiconductor chip 1 includes: a substrate 30; a first electrode pad 12; wiring 10 for crack check having one end connected to the first electrode pad 12 and extending along the outer peripheral edge of the substrate; and a plurality of transistors 21a, 21b, 21c, 21d, 21e, 21f, and 21g in which ones of sources and drains are connected to a plurality of different places of the wiring 10 for crack check.

Description

  The present invention relates to a semiconductor chip and a semiconductor device including the semiconductor chip. In particular, the present invention relates to a technique for detecting cracks in a semiconductor chip.

  In manufacturing a semiconductor device, a crack may be generated in a semiconductor chip due to stress or the like during cutting, mounting, or heating.

  As a method for detecting the occurrence of such cracks, Patent Document 1 discloses that a crack detection wiring and a plurality of electrode pads are arranged along the entire outer peripheral edge of a semiconductor chip, and a plurality of electrode pads are arranged at both ends of the wiring. A technique for detecting whether or not a crack has occurred in a semiconductor chip by connecting a first electrode pad and a second electrode pad selected from the above, and detecting a change in resistance value between the first and second electrode pads. It is disclosed.

JP 2009-54862 A

Futagawa Kiyoshi "New edition LSI failure analysis technology" P88-94, P164, Nikka Giren

  The following analysis is given by the present invention.

  However, the crack detection method described in Patent Document 1 can detect whether or not a crack is generated, but cannot detect which part of the semiconductor chip has a crack.

  A semiconductor chip according to a first aspect of the present invention includes a substrate, a first electrode pad, a crack check wiring having one end connected to the first electrode pad and extending along an outer peripheral edge of the substrate. And a plurality of transistors connected to one of the source / drain at a plurality of different positions of the crack check wiring.

  A semiconductor chip according to a second aspect of the present invention includes a substrate, a first electrode pad, a crack check wiring that is connected to the first electrode pad at one end and is extended along an outer peripheral edge of the substrate. And a plurality of capacitive elements connected to a plurality of different positions of the crack check wiring.

  According to the semiconductor chip of the present invention, it is possible to specify the occurrence location of cracks in the semiconductor chip.

1A and 1B are a plan view and a circuit diagram showing a semiconductor chip according to a first embodiment of the present invention. It is sectional drawing between X-X 'of FIG. It is sectional drawing and the expanded sectional view of the semiconductor device which concern on the 1st Embodiment of this invention. It is the top view and circuit diagram which show the semiconductor chip concerning the 2nd Embodiment of this invention. 5 is a timing chart showing the operation of the shift register of FIG. It is a figure for demonstrating operation | movement of the semiconductor chip which concerns on the 2nd Embodiment of this invention. It is the top view and circuit diagram which show the semiconductor chip concerning the 3rd Embodiment of this invention. It is a top view which shows the semiconductor chip concerning the 4th Embodiment of this invention. It is sectional drawing of the semiconductor device which concerns on the 4th Embodiment of this invention.

  First, the outline | summary of embodiment of this invention is demonstrated. Note that the reference numerals of the drawings added in the description of the outline of the embodiment are merely examples for helping understanding, and are not intended to be limited to the illustrated modes.

  As shown in FIG. 1, the semiconductor chip 1 according to an embodiment of the present invention has a substrate 30, a first electrode pad 12, one end connected to the first electrode pad 12, and the outer periphery of the substrate 30. A plurality of transistors 21a to 21g having one of the source / drain (drain in FIG. 1B) connected to a plurality of different positions of the crack check wiring 10 and the crack check wiring 10; Is provided.

  With the above configuration, when the crack check wiring 10 is disconnected as shown in FIG. 1C, if a current is supplied to the crack check wiring 10 through the first electrode pad 12, A current flows through the transistors connected up to 18 and emits light, but no current flows through transistors connected after the disconnection point 18 and thus does not emit light. Whether or not a current is flowing through the transistor can be determined using a known optical emission microscope or the like, so that the disconnection portion 18 of the crack check wiring 10 can be specified. That is, it is possible to specify the occurrence location of cracks in the semiconductor chip 1.

  In the semiconductor chip 1, as shown in FIG. 1B, the other end of the crack check wiring 10 may be connected to the ground.

  Further, as shown in FIG. 1B, the semiconductor chip 1 further includes a second electrode pad 14, and the other end of the crack check wiring 10 is connected to the second electrode pad 14. Also good.

  The semiconductor chip 1 may further include a control signal input terminal 16, and the control electrodes of the plurality of transistors 21 a to 21 g may be connected in common and connected to the control signal input terminal 16.

  4B, the semiconductor chip 3 includes a shift register 84 including a plurality of shift circuits 82a to 82g connected in cascade and the other of the sources / drains of the plurality of transistors 21a to 21g (FIG. 4). (B) includes a source) and a plurality of test electrode pads 83a to 83g connected to each other, and outputs (Q1 to Q7) of the plurality of shift circuits 82a to 82g are connected to a plurality of transistors 21a to 21g. You may make it connect with each of these control electrodes.

  As shown in FIG. 5, in the shift register 84, a plurality of shift circuits 82a to 82g are operated in response to a clock signal CLK, and a plurality of transistors 21a to 21g connected to the respective shift circuits 82a to 82g are sequentially provided. It is preferable to turn it on.

  As shown in FIG. 7, the semiconductor chip 2 in another embodiment of the present invention has a substrate 30, a first electrode pad 12, one end connected to the first electrode pad 12, and the outer periphery of the substrate 30. The crack check wiring 10 extended along, and a plurality of capacitive elements 61a to 61g connected to a plurality of different positions of the crack check wiring 10 are provided.

  In the semiconductor chip 2, as shown in FIG. 7B, the other end of the crack check wiring 10 may be connected to the ground.

  Further, as shown in FIG. 7B, the semiconductor chip 2 further includes a second electrode pad 14, and the other end of the crack check wiring 10 is connected to the second electrode pad. Good.

  As shown in FIG. 3, a semiconductor device 91 according to an embodiment of the present invention includes any one of the semiconductor chips described above (1 in FIG. 1, 3 in FIG. 4, and 2 in FIG. 7). (In FIG. 3, the semiconductor chip 1 is included).

  8 and 9, the semiconductor device 204 is a semiconductor device in which a plurality of semiconductor chips 4a to 4d are stacked on each other, and each of the semiconductor chips 4a to 4d further includes a through electrode 201. Semiconductor chips facing each other may be connected by a through electrode 201.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[First Embodiment]
(Configuration of the first embodiment)
The configuration of the semiconductor chip according to the first embodiment and the semiconductor device on which the semiconductor chip is mounted will be described in detail with reference to the drawings. First, FIG. 1A is a plan view showing the configuration of the semiconductor chip 1 according to the first embodiment. As shown in FIG. 1A, the crack check wiring 10 is provided along the outer peripheral edge of the Si (silicon) substrate 30, and the crack check wiring 10 includes transistors 21a to 21a at predetermined intervals. g is connected. In FIG. 1A, seven transistors are connected, but the invention is not limited to this. As will be described later, since the disconnection location of the crack check wiring 10 is specified at the position of two transistors sandwiching the disconnection location, the number of transistors is preferably set according to the required accuracy for specifying the disconnection location.

  The first electrode pad 12 and the second electrode pad 14 are connected to both ends of the crack check wiring 10. FIG. 1B shows a circuit diagram of a portion related to a crack check test of the semiconductor chip 1. As shown in FIG. 1B, the transistors 21a to 21g are N-type MOS transistors, and the drain of each transistor is connected to the crack check wiring 10. On the other hand, the source of each transistor is connected to ground. In addition, the gates of the transistors are connected in common and connected to the gate control signal input terminal 16, and all the transistors 21 a to 21 g are turned on / off by the gate control signal C <b> 1 supplied to the gate control signal input terminal 16. Be controlled.

  In the crack check test, a current is supplied to the first electrode pad 12 from a tester (not shown), and a continuity test of the crack check wiring 10 is performed. The second electrode pad 14 is always connected to the ground via the wiring 15. Thus, when the other end (the second electrode pad 14 side) of the crack check wiring 10 is always connected to the ground, the second electrode pad 14 is not provided because it is not necessary to connect to the tester. May be.

  Alternatively, the second electrode pad 14 may be provided so that it is not always connected to the ground, and the potential of the second electrode pad 14 may be controlled from a tester.

  Next, with reference to FIG. 2, details of a portion where the crack check wiring 10 and the transistors 21a to 21g are connected will be described. FIG. 2 is a cross-sectional view taken along the line X-X ′ in FIG. 1 and shows details of a portion where the transistor 21 c is connected to the crack check wiring 10. In FIG. 2, an N-type MOS transistor 21 c including a source 31, a drain 32, and a gate electrode 36 is formed on a P-type Si substrate 30.

  The source 31 is connected to a VSS power wiring 44 formed on the first aluminum layer 41 through a contact plug. Here, the VSS power supply wiring 44 is a wiring for supplying a ground potential to each of the transistors 21a to 21g. On the other hand, the drain 32 is connected to the crack check wiring 10 formed in the tungsten (W) layer through a contact plug. In addition, the second aluminum layer 42 is provided with, for example, wiring for connecting the first and second electrode pads (12, 14) on the surface of the semiconductor chip.

  Next, the configuration of the semiconductor device 91 in which the semiconductor chip 1 is packaged will be described with reference to FIG. FIG. 3A is a cross-sectional view of the semiconductor device 91 in which the semiconductor chip 1 that has become non-defective after the crack check test is packaged. FIG. 3B is an enlarged cross-sectional view of the broken-line frame portion 94 of FIG. In FIG. 3B, a non-defective semiconductor chip 1 is packaged by FC-BGA (Flip Chip-Ball Grid Array). As shown in FIG. 3B, the semiconductor device 91 includes a semiconductor chip 1 and a mold resin 99 for molding the semiconductor chip 1. Further, the semiconductor device 91 has a wiring pattern 98 on a base material 95, and the wiring pattern 98 and the pad 102 on the semiconductor chip 1 are electrically connected via bumps 101. The wiring pattern 98 and the external terminals 96a and 96b are electrically connected via the via 100. Further, in the base material 95, regions other than the external terminals 96 a and 96 b are covered with the solder resist 97.

(Operation of the first embodiment)
Next, with reference to FIG. 1C, an operation when performing a crack check test of the semiconductor chip 1 according to the first embodiment will be described. The crack check test includes a disconnection check step for checking disconnection of the crack check wiring 10 and a disconnection location specifying step for specifying a disconnection location when a disconnection is detected in the disconnection check test.

  First, the disconnection check step will be described. By supplying a ground potential to the gate control signal input terminal 16 and setting the gate control signal C1 to the low level, all the transistors 21a to 21g are turned off. In this state, when a current is supplied from a tester (not shown) via the first electrode pad 12, whether or not a current flows through the crack check wiring 10 is detected on the tester side. When the crack check wiring 10 is not disconnected, the current flowing from the first electrode pad 12 to the second electrode pad 14 is detected on the tester side. On the other hand, as shown in FIG. 1C, when there is a disconnection portion 18, it is detected on the tester side that no current flows through the crack check wiring 10, and it is determined that the crack check wiring 10 is disconnected. .

  Next, when it is determined in the disconnection check step that the crack check wiring 10 is disconnected, the following disconnection location specifying step is performed. By supplying a high level voltage to the gate control signal input terminal 16, the gate control signal C1 is set to a high level and all the transistors 21a to 21g are turned on. In this state, a current is supplied from the tester (not shown) to the crack check wiring 10 via the first electrode pad 12.

  At this time, as shown in FIG. 1C, when there is a disconnection point 18, in the transistors 21a to 21d connected up to the disconnection point 18, a current flows between the drain and the source, and light is emitted by weak light. However, since no current flows through the transistors 21e to 21g connected after the disconnection point 18, no light is emitted.

  The above weak light emission in the transistor is detected using optical emission microscopy. Thereby, it is detected that the boundary of the presence or absence of light emission is between the transistor 21d and the transistor 21e, and it can be specified that the crack check wiring 10 is disconnected between the transistor 21d and the transistor 21e. That is, in the semiconductor chip 1, it can be specified that a crack has occurred in a region including the crack check wiring 10 between the transistor 21d and the transistor 21e.

  Here, a known optical emission microscopy method used in failure analysis of a semiconductor chip is disclosed in Non-Patent Document 1 and the like. Optical emission microscopy (also referred to as PEM (Photo Emission Microscopy)) is composed of an optical microscope and an ultra-sensitive camera, and detects an emission phenomenon occurring inside a semiconductor with an ultra-sensitive camera. When the number of transistors connected to the crack check wiring 10 in the semiconductor chip 1 is increased, the current flowing through the transistors gradually decreases due to the wiring resistance as the number of transistors approaches the second electrode pad 14 side. However, the optical emission microscopy can detect weak light emission due to a current on the order of several μA, and has sufficient detection capability in the vicinity of the second electrode pad 14 side.

  As described above, the crack check test of the semiconductor chip 1 is performed in the manufacturing inspection process, and only the chips determined to be non-defective are packaged and mounted on the semiconductor device 91 as shown in FIG. Further, the information on the identified crack detection location is also used as analysis data for improving the yield of the semiconductor chip.

  Further, when the semiconductor device 91 fails after product shipment, the above-described crack check test can be performed as failure analysis. However, in order to use optical emission microscopy, a step of exposing the semiconductor chip 1 is required. Specifically, in the case of the configuration of FIG. 3, the process is performed by dissolving the mold resin 99 at the location of the semiconductor chip 1 to be exposed with fuming nitric acid or the like. In the case of packaging with a ceramic package or a metal package, the chip is exposed by mechanically removing or cutting the lid. After the chip is exposed in this way, the above-described crack check test is performed.

  As described above, according to the semiconductor chip 1 according to the first embodiment, not only the presence / absence of a crack in the semiconductor chip 1 can be detected, but also the occurrence location of the crack can be specified. In addition, since the crack check wiring 10 has a simple configuration in which transistors are provided at predetermined intervals, it is possible to identify the location where a crack occurs with a small circuit configuration.

(Second Embodiment)
Next, the semiconductor chip 3 according to the second embodiment will be described with reference to FIG. FIG. 4A is a plan view of the semiconductor chip 3 according to the second embodiment, and FIG. 4B is a circuit diagram of a portion related to a crack check test of the semiconductor chip 3. As can be seen by comparing FIG. 4B with FIG. 1B (first embodiment), in FIG. 4B, the shift register 84 and the sources of the transistors 21a to 21g are newly connected. Test electrode pads 83a-g are added. The other constituent elements are the same as those in FIG. 1B, and thus the same reference numerals are given and description thereof is omitted.

  As shown in FIG. 4B, the shift register 84 is configured by cascading the same number of flip-flop circuits (shift circuits) 82a to 82g as the transistors 21a to 21g. Further, the input terminal of the first stage flip-flop circuit 82a is connected to the ground, and a Low level signal is inputted. The outputs (Q1 to Q7) of the flip-flop circuits 82a to 82g are connected to the gates of the transistors 21a to 21g, and control the on / off of the transistors 21a to 21g, respectively.

  The clock signal CLK is supplied from the clock input terminal 85 to the clock terminals of the flip-flop circuits 82 a to 82 g of the shift register 84. A reset signal is input from a reset signal input terminal 86 to a set terminal S of the flip-flop circuit 82a (first-stage flip-flop circuit) and a reset terminal R of the flip-flop circuits 82b to 82g (second-stage flip-flop circuits). Reset is supplied.

  Further, as shown in FIG. 4A, the test electrode pads 83a to 83g are provided on the surface of the semiconductor chip 3, and a current flowing between the drain and source of each of the transistors 21a to 21g is detected by a tester (not shown). Used to do.

  Next, an operation when performing a crack check test of the semiconductor chip 3 according to the second embodiment will be described with reference to FIGS. The crack check test includes a disconnection check step for checking disconnection of the crack check wiring 10 and a disconnection location specifying step for specifying a disconnection location when a disconnection is detected in the disconnection check test. In the disconnection check step, all the transistors 21a to 21g are turned off while the reset signal Reset is at a low level (inactive) and the clock signal CLK is at a low level (inactive). In this state, it is determined by determining whether or not the first electrode pad 12 and the second electrode pad 14 are conductive (similar to the disconnection check step of the first embodiment).

  When a disconnection is detected in the disconnection check step, a disconnection location specifying step shown below is performed next. First, the operation of the shift register 84 in the disconnection location specifying step will be described with reference to FIG. At time t0, the reset signal Reset transitions to a high level, and the shift register 84 is initialized. The period t0 to t1 is a state in which the shift register 84 is initialized, only Q1 is at a high level, and Q2 to Q7 are at a low level. Next, by applying the clock signal CLK from time t1, the high level signal of Q1 is shifted to the flip-flop circuit in the next stage at the timing of the rising edge of the clock signal CLK. With the above operation, Q1 to Q7 become High level in the periods t0 to t1, t1 to t2, t2 to t3, t3 to t4, t4 to t5, t5 to t6, and t6 to t7, respectively. Therefore, the transistors 21a to 21g are sequentially turned on every period.

  Next, the operation of the disconnection location specifying step will be described with reference to FIG. As shown in FIG. 6, it is assumed that the crack check wiring 10 (disconnection location 88) between the transistor 21d and the transistor 21e is disconnected. In the disconnection location specifying step, the first and second electrode pads 12, 14 and the test electrode pads 83a to 83g are connected to a tester (not shown). 6A to 6G show the sections t0 to t1, t1 to t2,. . . , T6 to t7 show the operation of the transistors 21a to 21g. 6A to 6G, the transistors 21a to 21g are turned on, respectively.

  In the disconnection location specifying step, a current is supplied to the crack check wiring 10 via the first electrode pad 12. At this time, current flows from the first electrode pad 12 to the disconnection point 88, but no current flows from the disconnection point 88 to the second electrode pad 14 due to disconnection. In addition, when an on-state transistor is connected to the crack check wiring 10 through which a current flows, a current flows between the drain and the source of the transistor. Specifically, in FIG. 6A, a current flows between the drain and source of the transistor 21a, and the current can be detected by a tester from the test electrode pad 83a connected to the source.

  Similarly, in FIGS. 6B to 6D, currents can be detected by testers from the test electrode pads 83b to 83d, respectively. However, in FIGS. 6E to 6G, no current flows through the crack check wiring 10, and therefore no current is detected by the tester from the test electrode pads 83e to 83g.

  As described above, it can be detected that the boundary between the transistor through which current flows and the transistor through which current does not flow is between the transistor 21d and the transistor 21e. That is, it can be detected that the crack check wiring 10 between the transistor 21d and the transistor 82e is disconnected. In the semiconductor chip 3, in the region including the crack check wiring 10 between the transistor 21d and the transistor 21e. It can be identified that a crack has occurred.

  As described above, according to the semiconductor chip 3 according to the second embodiment, not only the presence / absence of a crack in the semiconductor chip 3 can be detected, but also the occurrence location of the crack can be specified. Further, in the first embodiment, an optical emission microscope apparatus is necessary. However, in the present embodiment, it can be performed only by detecting current from a test electrode pad 83a-g using a tester, so that it is as large as an optical emission microscope apparatus. The effect that the location where a crack is generated can be easily specified without requiring a simple measuring device.

  Further, in the second embodiment, as in the first embodiment, the above-described crack check test can be performed in the manufacturing inspection process and the failure analysis after product shipment. In the manufacturing inspection process, a crack check test of the semiconductor chip 3 is performed, and only the chips determined to be non-defective are packaged (the semiconductor chip 3 is mounted instead of the semiconductor chip 1 in FIG. 3). Further, in the second embodiment, when performing failure analysis after product shipment, by providing test terminals that can electrically connect the test electrode pads 83a to 83g to the tester in a state where the semiconductor chip 3 is packaged. The effect that the crack generation location can be specified without performing the chip exposure step required in the first embodiment is obtained.

(Third embodiment)
Next, a semiconductor chip 2 according to the third embodiment will be described with reference to FIG. FIG. 7A is a plan view of the semiconductor chip 2 according to the third embodiment, and FIG. 7B is a circuit diagram of a portion related to a crack check test of the semiconductor chip 2. As can be seen by comparing FIG. 7B with FIG. 1B (first embodiment), in FIG. 7B, instead of the transistors 21a to 21g of FIG. g is connected. Specifically, one end of each capacitive element 61a-g is connected at every predetermined interval of the crack check wiring 10, and the other end of each capacitive element 61a-g is connected to the ground. In FIG. 7B, seven capacitor elements are connected, but the invention is not limited to this. As will be described later, since the disconnection location of the crack check wiring 10 is specified by the position of two capacitive elements sandwiching the disconnection location, the number of capacitance elements can be set according to the required accuracy for specifying the disconnection location. preferable.

  Similarly to the first embodiment, when the other end (the second electrode pad 14 side) of the crack check wiring 10 is always connected to the ground, the second electrode pad 14 is connected to the tester. It is not necessary to provide this because it is not necessary.

  Alternatively, the second electrode pad 14 may be provided so that it is not always connected to the ground, and the potential of the second electrode pad 14 may be controlled from a tester. Moreover, since the other component of FIG. 7 is the same as that of FIG. 1, the same referential mark is attached | subjected and description is abbreviate | omitted.

  Next, with reference to FIG. 7C, an operation when performing a crack check test of the semiconductor chip 2 according to the third embodiment will be described. The crack check test includes a disconnection check step for checking disconnection of the crack check wiring 10 and a disconnection location specifying step for specifying a disconnection location when a disconnection is detected in the disconnection check test. Here, since the disconnection check step is the same as that of the first embodiment, the description thereof is omitted.

  As shown in FIG. 7C, it is assumed that the crack check wiring 10 (disconnected portion 68) between the capacitive element 61d and the capacitive element 61e is broken. Further, the crack check wiring 10 has wiring resistance, and the wiring resistance of each section sandwiched between the first electrode pad 12, one end of the capacitive elements 61a to 61g, and the second electrode pad 14 is 62a. Represented by ~ 62g.

  When a disconnection is detected in the disconnection check step, the disconnection location specifying step shown below is performed. The crack check wiring 10 is driven by controlling the voltage of the first electrode pad 12 from a tester (not shown) alternately between a high level and a low level in a predetermined cycle. Then, the capacitive elements 61a to 61d connected up to the disconnection point 68 are charged when the first electrode pad 12 is at a high level and discharged when the first electrode pad 12 is at a low level. That is, the capacitive elements 61a to 61d are repeatedly charged and discharged at the predetermined cycle, and accordingly, current flows through the wiring resistors 62a to 62d of the crack check wiring 10 to generate heat.

  On the other hand, since the crack check wiring 10 from the disconnection point 68 is disconnected, no current flows, and the capacitive elements 61e to 61g do not perform the charging / discharging operation. Therefore, no current flows through the wiring resistances 62e to 62g of the crack check wiring 10 from the disconnection point 68, so that no heat is generated.

  The above heat generation location is detected by an infrared camera or the like. Thereby, it can be specified that the crack check wiring 10 between the capacitative element 61d and the capacitative element 61e is disconnected by detecting the boundary between the heated part and the non-heated part. That is, in the semiconductor chip 2, it can be specified that a crack has occurred in a region including the crack check wiring 10 between the capacitive element 61d and the capacitive element 61e.

  Here, a technique for detecting a heat generation point is disclosed in Non-Patent Document 1 and the like. By operating the optical emission microscopy used in the first embodiment in the infrared region, it can be used to detect heating points.

  As described above, according to the semiconductor chip 2 according to the third embodiment, not only the presence / absence of a crack in the semiconductor chip 2 can be detected, but also the occurrence location of the crack can be specified. Further, in the first embodiment, it is necessary to perform on / off control of each of the transistors 21a to 21g. However, in the third embodiment, since the transistor is replaced with a capacitive element, the above control becomes unnecessary. Thus, an effect that it can be realized with a simpler configuration is obtained.

  Further, in the third embodiment, as in the first embodiment, the above-described crack check test can be performed in the manufacturing inspection process and the failure analysis after product shipment. In the manufacturing inspection process, a crack check test of the semiconductor chip 2 is performed, and only the chips determined to be non-defective are packaged (the semiconductor chip 2 is mounted instead of the semiconductor chip 1 in FIG. 3). Further, in the failure analysis after product shipment, after the necessary portion of the chip is exposed, the location where the crack is generated is specified by detecting the heat generation location.

(Fourth embodiment)
Next, a fourth embodiment will be described with reference to FIGS. FIG. 8 is a plan view showing a semiconductor chip 4 according to the fourth embodiment. As can be seen by comparing the semiconductor chip 4 of FIG. 8 with the semiconductor chip 1 of FIG. 1 (first embodiment), the semiconductor chip 4 of FIG. A plurality of through electrodes 201 are arranged in the electrode region. Since the other components are the same as those of the semiconductor chip 1 of FIG. 1, the same reference numerals are given and description thereof is omitted.

  FIG. 9 is a cross-sectional view showing a configuration of a semiconductor device 204 according to the fourth embodiment. In FIG. 9, a plurality of semiconductor chips 205, 4a to d are stacked and packaged together. Here, the semiconductor chips 4a to 4d are memory devices each having the configuration of the semiconductor chip 4 of FIG. The semiconductor chip 205 is a control chip that controls the semiconductor chips 4a to 4d, and has a through electrode 201 as with the semiconductor chips 4a to 4d. As shown in FIG. 9, the semiconductor chips (control chip) 205 and the semiconductor chips (memory devices) 4 a to 4 d are electrically connected to each other through the plurality of through electrodes 201. The semiconductor device 204 is a stacked semiconductor device that functions as a memory system. However, the stacked semiconductor chips 4a to 4d are not limited to memory devices, and may be other devices (logic or the like).

  The semiconductor chips 205, 4a to d are subjected to the crack check test described in the first embodiment, and only good products are selected. In FIG. 9, a semiconductor chip (control chip) 205 is mounted on a package substrate 206, and semiconductor chips 4a to 4d are stacked on each other. Further, the semiconductor chips 205, 4 a to d are molded with the sealing resin 208. A plurality of external terminals 210 are provided on the surface of the package substrate 206 opposite to the semiconductor chip 205.

  The semiconductor chip 4 in FIG. 8 has a configuration in which the through electrode 201 is provided with respect to the semiconductor chip 1 (FIG. 1) of the first embodiment, but is not limited thereto. The semiconductor chip 4 may have a configuration in which a through electrode is provided with respect to the semiconductor chip 3 of the second embodiment and the semiconductor chip 2 of the third embodiment. Further, the semiconductor chips of the first to third embodiments may be mixed and mounted as a plurality of semiconductor chips (4a to d in FIG. 9) to be stacked on each other.

  In addition, when the semiconductor chips 3 of the second embodiment are stacked, the following effects are obtained in failure analysis after product shipment. That is, a crack check test can be performed in a state where the semiconductor device 204 is packaged in FIG. On the other hand, since the semiconductor chip 1 of the first embodiment needs to detect weak light and the semiconductor chip 2 of the third embodiment needs to detect a heat generation point, failure analysis of the semiconductor chips stacked inside is performed. In some cases, it is necessary to perform chip exposure by disassembling each semiconductor chip.

  On the other hand, in the second embodiment, it is only necessary to detect current from the test electrode pad. Therefore, it is possible to perform a crack check test while the semiconductor chip is packaged. In that case, the first and second electrode pads (12a to 14d, 14a to 14d (not shown)) of each of the semiconductor chips 4a to 4d and the test are provided in the through electrode 201 of the through electrode region (200a or 200b). Electrode pads (83a-g; test electrode pads of a plurality of semiconductor chips are connected to each other by through electrodes 201), etc., and each semiconductor chip 4a-d is controlled from a tester (not shown), A crack check test may be performed.

  The present invention can detect not only the occurrence of cracks in a semiconductor chip, but also the occurrence location. Therefore, the present invention can be applied to a semiconductor chip inspection device, a failure analysis device, and the like.

  Note that, within the scope of the entire disclosure (including claims and drawings) of the present invention, the embodiments can be changed and adjusted based on the basic technical concept. Various combinations or selections of various disclosed elements (including each element of each claim, each element of each embodiment, each element of each drawing, etc.) are possible within the scope of the claims of the present invention. . That is, the present invention naturally includes various variations and modifications that could be made by those skilled in the art according to the entire disclosure including the claims and the drawings, and the technical idea.

1, 2, 3, 4: Semiconductor chips 4a to 4d: Semiconductor chips (memory devices)
10, 10a to e: crack check wiring 12: first electrode pad 14: second electrode pad 15: wiring 16: gate control signal input terminal (control signal input terminal)
18, 68, 88: Disconnection locations 21a to g: Transistor 30: Si substrate (substrate)
31: Source 32: Drain 34: Silicon nitride film 36: Gate electrode 40: Tungsten (W) layer 41: First aluminum layer 42: Second aluminum layer 44: VSS power supply wiring 61a-g: Capacitance elements 62a-g: wiring Resistors 82a to 82g: flip-flop circuits (shift circuits)
83a to g: Test electrode pad 84: Shift register 85: Clock signal input terminal 86: Reset signal input terminal 91, 204: Semiconductor device 95: Substrate 96a, 96b, 210: External terminal 97: Solder resist 98: Wiring pattern 99 : Mold resin 100: Via 101: Bump 102: Pad 200a, 200b: Through electrode region 201: Through electrode 205: Semiconductor chip (control chip)
206: Package substrate 208: Sealing resin C1: Gate control signal CLK: Clock signal Reset: Reset signal

Claims (11)

A substrate,
A first electrode pad;
One end is connected to the first electrode pad, and the crack check wiring extended along the outer periphery of the substrate;
A plurality of transistors having one of the source / drain connected to a plurality of different positions of the crack check wiring; and
A semiconductor chip comprising:   The semiconductor chip according to claim 1, wherein the other end of the crack check wiring is connected to ground. A second electrode pad;
The semiconductor chip according to claim 1, wherein the other end of the crack check wiring is connected to the second electrode pad. A control signal input terminal;
4. The semiconductor chip according to claim 1, wherein control electrodes of the plurality of transistors are connected in common and connected to the control signal input terminal. 5. A shift register composed of a plurality of shift circuits connected in cascade;
A plurality of test electrode pads respectively connected to the other of the source / drain of the plurality of transistors;
Further comprising
4. The semiconductor chip according to claim 1, wherein outputs of the plurality of shift circuits are connected to control electrodes of the plurality of transistors. 5.   6. The semiconductor chip according to claim 5, wherein the shift register operates the plurality of shift circuits in response to a clock signal and sequentially turns on the plurality of transistors connected to each of the shift circuits. . A substrate,
A first electrode pad;
One end is connected to the first electrode pad, and the crack check wiring extended along the outer periphery of the substrate;
A plurality of capacitive elements connected to a plurality of different positions of the crack check wiring,
A semiconductor chip comprising:   The semiconductor chip according to claim 7, wherein the other end of the crack check wiring is connected to ground. A second electrode pad;
The semiconductor chip according to claim 7, wherein the other end of the crack check wiring is connected to the second electrode pad.   A semiconductor device comprising the semiconductor chip according to claim 1. A semiconductor device in which a plurality of semiconductor chips are stacked on each other,
Each of the semiconductor chips further includes a through electrode,
The semiconductor device according to claim 10, wherein the semiconductor chips facing each other are connected by the through electrode.

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