JP4744884B2 - Wafer inspection apparatus and wafer inspection method - Google Patents

Description

  The present invention relates to a wafer inspection apparatus and a wafer inspection method.

  In some cases, two individual elements such as power MOSFETs and diodes and a chip of a composite element are mounted at the same time to manufacture a package having a function of operating with two systems of input signals. In this case, since two chips formed adjacent to each other on the semiconductor wafer are simultaneously mounted as one package, both the two adjacent chips need to be non-defective products.

  Individual elements such as power MOSFETs have only terminals such as a drain, a gate, and a source, and are required to have high voltage, large current, and low resistance measurement accuracy. For this reason, the power supply system and the measurement system have only one unit, and there is no inspection device for parallel measurement. Therefore, the performance of the chip formed on the semiconductor wafer has been inspected by performing measurement one by one.

  Conventionally, inspection of chips formed on a semiconductor wafer has been performed as follows. FIG. 4 is a schematic diagram for explaining the performance inspection of the power MOSFET 10 formed on the semiconductor wafer. Here, for simplification of description, the case where four power MOSFETs 10 are formed in parallel with the first chip, the second chip, the third chip, and the fourth chip on the semiconductor wafer is illustrated. Yes. A source aluminum pad 11 and a gate aluminum pad 12 are formed on the surface of each power MOS EFT 10, while a back surface drain terminal (not shown) common to all chips is formed on the entire back surface.

  The inspection device 20 that performs performance inspection of these power MOSFETs 10 includes a source voltage terminal Sv21, a source current terminal Si22, a gate voltage terminal Gv23, and a gate current terminal Gi24. Each terminal includes a probe 25 for applying a current or a voltage to the source aluminum pad 11 and the gate aluminum pad 12 of the power MOSFET 10. Moreover, the drain terminal (not shown) of the test | inspection apparatus contacted with the back surface drain terminal of power MOSFET10 is provided.

  When the performance test of the power MOSFET 10 is performed, as shown in FIG. 4, first, the probe 25 connected to the source voltage terminal Sv21 and the source current terminal Si22 is brought into contact with the source aluminum pad 11 of the first chip. At the same time, the probe 25 connected to the probe of the gate voltage terminal Gv and the gate current terminal Gi is brought into contact with the gate aluminum pad 12 of the first chip. The back surface drain terminal is in contact with and electrically connected to the drain terminal of the inspection apparatus 20. The gate voltage and gate current are arbitrary values.

  In the connection state as described above, the characteristics of the drain current I1-drain voltage V1 of the first chip are measured. If the drain current at a certain drain voltage is within a predetermined determination standard (FIG. 5, hatched portion), the drain current I1-drain voltage V1 characteristic of the first chip is acceptable, The first chip is determined to be a non-defective product (see FIG. 5).

  When the pass / fail determination of the first chip is completed, the measurement method described above is then executed for the second chip, and the pass / failure determination is performed by measuring the drain voltage V2-drain current I2 characteristic in the same manner. Thereafter, when measuring the third chip and the fourth chip, the measurement is performed for each chip in the same manner, and pass / fail judgment is performed.

  As shown in FIGS. 4 and 5, in the conventional method for testing the power MOSFET 10, the drain current I-drain voltage V is measured for each chip. Accordingly, the time required for measurement is the inspection time for one chip × the number of chips formed on one semiconductor wafer. In recent years, the chip size has become smaller, and a large number of chips are formed on a semiconductor wafer. For this reason, the time required for the performance inspection of the chip becomes very long, which causes a problem that the manufacturing cost increases.

Therefore, Patent Document 1 discloses a chip inspection method that shortens the time required for inspection. As shown in FIG. 6, each chip 1 is provided with a pass / fail judgment element 2. Each pass / fail judgment element 2 is electrically connected across each chip 1. This inspection method does not perform performance inspection for each chip over the entire semiconductor wafer, but is configured to narrow down extraction of defective chips from the whole to a part by selecting measurement terminals.
Japanese Patent Laid-Open No. 3-89529

  However, in the chip of individual elements such as power MOS or diode and composite elements targeted by the present invention, there is no room for forming a pass / fail judgment element on the chip, and the method described in Patent Document 1 described above is It cannot be applied.

  In addition, power MOSFETs and the like have a relatively low chip cost and a high yield rate. Therefore, the increase in manufacturing cost is the dominant factor for the time required for chip performance inspection.

  In addition, when adjacent chips are assembled as a set on a semiconductor wafer and assembled into one package, one chip may be a good product while the other chip may be a defective product. In such a case, the entire package becomes defective as one package, that is, one product. In addition, since the performance inspection is performed for all the chips, the measurement time required for the performance inspection of one good chip in the defective package is wasted.

  Obtaining the true number of non-defective products in which two adjacent chips are both non-defective from the result of performance inspection for each chip is a very difficult task, and development of complex software is essential. Also, at the time of mounting, it is necessary to identify whether or not the two chips to be mounted are both non-defective using special software. Wafer inspection hardware is very expensive considering the ratio of selling prices of individual elements, and reducing the cost of wafer inspection is a major issue.

  A wafer inspection apparatus according to the present invention is a wafer inspection apparatus in which a plurality of semiconductor elements mounted on one package are formed adjacent to each other, and a gate for applying a gate voltage to the plurality of semiconductor elements simultaneously. A voltage terminal; and a current terminal for simultaneously measuring drain-source currents of the plurality of semiconductor elements. As a result, adjacent semiconductor elements formed on the semiconductor wafer can be simultaneously measured, and the time required for inspection can be shortened.

  According to the present invention, it is possible to shorten the measurement time required for inspection of a semiconductor element. In addition, it is possible to omit wasteful inspection when a plurality of adjacent chips on the semiconductor wafer are simultaneously mounted to form one package.

Embodiment 1 FIG.
A semiconductor wafer inspection apparatus according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a schematic diagram showing a configuration of a semiconductor wafer inspection apparatus according to the present embodiment. Here, for simplification of description, a case where the power MOSFET 100 inspects a first chip, a second chip, a third chip, a fourth chip, and four semiconductor wafers formed in parallel is illustrated. Show. A source aluminum pad 101 and a gate aluminum pad 102 are formed on the surface of each power MOSEFT 100, while a back surface drain terminal (not shown) common to all chips is formed on the entire surface on the back surface.

  A wafer inspection apparatus 200 that performs performance inspection of these power MOSFETs 100 includes a source voltage terminal Sv201, a source current terminal Si202, a gate voltage terminal Gv203, and a gate current terminal Gi204. Each terminal includes a probe 205 for applying a current or voltage to the source aluminum pad 101 and the gate aluminum pad 102 of the power MOSFET 100. In addition, a drain terminal (not shown) of a tester that is in contact with the back surface drain terminal of the power MOSFET 100 is provided.

  The source current terminal Si202 includes two probes 205 electrically connected to the source current terminal Si202 so as to be in contact with the source aluminum pads 101 of the two adjacent power MOSFETs 100 simultaneously.

  In addition, the gate current terminal Gi204 includes two probes 205 electrically connected to the gate current terminal Gi204 so as to be in contact with the gate aluminum pads 102 of the two adjacent power MOSFETs 100 simultaneously.

  When performing the performance inspection of the power MOSFET 100 on the semiconductor wafer, first, the source aluminum pad 101 of the first chip has a probe 205 connected to the source voltage terminal Sv and a probe 205 connected to the source current terminal Si. Two are touched. Further, the probe 205 connected to the gate voltage terminal Gv and the probe 205 connected to the gate current terminal Gi are in contact with the gate aluminum pad 102 of the second chip.

  At the same time, the probe 205 electrically connected to the source current terminal Si202 is brought into contact with the source aluminum pad 101 of the second chip adjacent to the first chip. Further, the probe 205 electrically connected to the gate current terminal Gi204 is brought into contact with the gate aluminum pad 102 of the second chip.

  That is, the two probes 205 connected to the source current terminal Si 202 are simultaneously brought into contact with the source aluminum pads 101 of the two adjacent power MOSFETs 100. The two probes connected to the gate current terminal Gi204 are simultaneously in contact with the gate aluminum pads 102 of the two adjacent power MOSFETs 100, respectively.

  A predetermined voltage applied from the source voltage terminal Sv201 to the source aluminum pad 101 of the first chip is also applied to the source aluminum pad 101 of the second chip via the probe 205 connected to the source current terminal Si. The The predetermined voltage applied from the gate voltage terminal Gv203 to the gate aluminum pad 102 of the first chip is also applied to the gate aluminum pad 102 of the second chip via the probe 205 connected to the gate current terminal Gi. Applied. That is, it is possible to simultaneously perform the performance inspection of the two adjacent power MOSFETs 100.

  Note that two probes 205 may be connected to the source voltage terminal Sv201 and the gate voltage terminal Gv203, respectively, and a voltage may be applied to the source aluminum pad 101 and the gate aluminum pad 102 of the two adjacent power MOSFETs 100, respectively.

  A semiconductor wafer inspection method will be described with reference to FIG. 2A is a circuit diagram of the first chip and the second chip that are connected to the wafer inspection apparatus 200, and FIG. 2B is an electrical characteristic measured by the wafer inspection apparatus 200. FIG. FIG. As described above, each probe 205 of the wafer inspection apparatus 200 is connected to the source aluminum pad 101 and the gate aluminum pad 102 of the first chip and the second chip, respectively.

  As shown in FIG. 2A, the two power MOSFETs 100 are connected in parallel. In such a connection state, first, a specific gate voltage is applied. This gate voltage is an arbitrary value. Then, the characteristics of the drain current I and the drain voltage V obtained by combining the first chip and the second chip are measured at a time. After that, if the drain current at a certain preset drain voltage is within the determination standard (the hatched portion in FIG. 2B), the drain current I-drain voltage V characteristics of the first chip and the second chip pass. Is determined. That is, the first chip and the second chip are collectively determined as non-defective products.

  On the other hand, if the drain current at a certain drain voltage set in advance is out of the determination standard (white portion in FIG. 2B), the drain current I-drain voltage V characteristics of the first chip and the second chip are not good. Judged as passing. That is, the first chip and the second chip are collectively determined to be defective. That is, when one of the two chips is a defective product, it is assumed that both of these chips are defective products.

  Thereafter, the third chip and the fourth chip are simultaneously measured for performance inspection. Similarly, when measuring the third chip and the fourth chip, the two chips are also measured at the same time, and the pass / fail judgment of the power MOSFET 100 is executed. In this way, in the electrically connected circuit as shown in FIG. 2, since the drain current I-drain voltage V of the two chips are measured at a time, the pass / fail judgment of the two power MOSFETs 100 can be performed simultaneously. is there.

  The power MOSFET has a relatively low cost of the chip itself and a high yield rate. Therefore, the increase in manufacturing cost has become a dominant factor for the time required for chip performance inspection. However, as described above, since the pass / fail determination is performed for two, it is possible to reduce the time required for the inspection.

  In addition, when two adjacent power MOSFETs 100 are mounted simultaneously as one package, conventionally, when one by one is measured, even if only one is determined to be a good product, the package is a defective product. It was. However, since the two power MOSFETs 100 to be mounted at the same time are judged as good or bad, wasteful inspection (inspection in which only one of them is determined to be good) can be omitted.

  Thus, in the inspection of a semiconductor wafer when manufacturing a product (one package) having two power MOSFETs 100 as one set, the measurement time can be shortened to ½. Therefore, the time required for the semiconductor wafer inspection process can be shortened, the number of production per unit time can be improved, and the manufacturing cost can be reduced.

Embodiment 2. FIG.
Next, the configuration of the semiconductor wafer inspection apparatus 200 according to the second embodiment of the present invention will be described. FIG. 3 is a schematic diagram illustrating the configuration of the semiconductor wafer inspection apparatus 200 according to the second embodiment. In FIG. 3, the same components as those in FIG. The present embodiment is different from the first embodiment in that three probes 205 connected to the source current terminal Si202 and the gate current terminal Gi204 are provided.

  Again, as described above, for simplicity of explanation, the power MOSFET 100 includes four semiconductor chips formed in parallel with the first chip, the second chip, the third chip, and the fourth chip. A case of inspecting a wafer is shown. A source aluminum pad 101 and a gate aluminum pad 102 are formed on the surface of each power MOSEFT 100, while a back surface drain terminal (not shown) common to all chips is formed on the entire surface on the back surface.

  As described in the first embodiment, the wafer inspection apparatus 200 that performs performance inspection of the power MOSFETs 100 includes the source voltage terminal Sv201, the source current terminal Si202, the gate voltage terminal Gv203, and the gate current terminal Gi204. Each terminal includes a probe 205 for applying a current or a voltage to the source aluminum pad 101 and the gate aluminum pad 102 of the MOSFET 100. In addition, a drain terminal (not shown) of a tester that is in contact with the back surface drain terminal of the MOSFET 100 is provided.

  The source current terminal Si202 includes three probes 205 that are electrically connected so as to simultaneously contact the source aluminum pads 101 of the three adjacent MOSFETs 100, respectively. The gate current terminal Gi204 has three probes 205 electrically connected to the gate current terminal Gi204 so as to be in contact with the gate aluminum pads 102 of the three adjacent MOSFETs 100 at the same time.

  When performing the performance test of the MOSFET 100 on the semiconductor wafer, first, as described above, the source aluminum pad 101 of the first chip is connected to the probe 205 connected to the source voltage terminal Sv and the source current terminal Si. Two probes 205 are contacted. Further, the probe 205 connected to the gate voltage terminal Gv and the probe 205 connected to the gate current terminal Gi are in contact with the gate aluminum pad 102 of the second chip.

  At the same time, the probe 205 electrically connected to the source current terminal Si202 is brought into contact with the source aluminum pad 101 of the second chip adjacent to the first chip. Further, the probe 205 electrically connected to the gate current terminal Gi204 is brought into contact with the gate aluminum pad 102 of the second chip. Further, another probe 205 electrically connected to the source current terminal Si202 is in contact with the source aluminum pad 101 of the third chip adjacent to the second chip. Further, another probe 205 electrically connected to the gate current terminal Gi204 is brought into contact with the gate aluminum pad 102 of the third chip.

  That is, the three probes 205 connected to the source current terminal Si 202 are simultaneously in contact with the source aluminum pads 101 of the three adjacent power MOSFETs 100. Further, the three probes connected to the gate current terminal Gi203 simultaneously contact the gate aluminum pads 102 of the three adjacent power MOSFETs 100. That is, the performance inspection of the three power MOSFETs 100 can be performed simultaneously.

  A predetermined voltage applied from the source voltage terminal Sv201 to the source aluminum pad 101 of the first chip is supplied to the second chip and the third chip via the three probes 205 connected to the source current terminal Si. It is also applied to the source aluminum pad 101. A predetermined voltage applied from the gate voltage terminal Gv203 to the gate aluminum pad 102 of the first chip is supplied to the gates of the second chip and the third chip via the probe 205 connected to the gate current terminal Gi. It is also applied to the aluminum pad 102. That is, it is possible to simultaneously perform the performance inspection of the three adjacent power MOSFETs 100.

  Note that three probes 205 may be connected to the source voltage terminal Sv201 and the gate voltage terminal Gv203, respectively, and voltages may be applied to the source aluminum pad 101 and the gate aluminum pad 102 of the three adjacent power MOSFETs 100, respectively.

  The quality determination of these power MOSFETs 100 is executed using the inspection method as described above. That is, in a state where the probes 205 are connected to the three power MOSFETs 100, first, a specific gate voltage is applied. Then, the characteristics of the drain current I and the drain voltage V obtained by collecting the first chip, the second chip, and the third chip are measured at a time. Thereafter, if the drain current at a preset drain voltage is within the determination standard, the first chip, the second chip, and the third chip are collectively determined as non-defective products.

  On the other hand, if the drain current at a certain preset drain voltage is outside the determination standard, the first chip, the second chip, and the third chip are collectively determined to be defective. That is, if any one of the three chips is defective, it is assumed that all three chips are defective.

  As described above, since the pass / fail determination is performed for all three, it is possible to further reduce the time required for the inspection. In addition, when three adjacent power MOSFETs 100 are mounted simultaneously as one package, when one by one is conventionally measured, only one of the three is determined to be non-defective, It was a defective product as a package. However, since the three power MOSFETs 100 to be mounted at the same time are determined as good or bad, wasteful inspection (inspection in which any of the three chip sets is determined as non-defective) can be omitted. By doing so, the measurement time can be shortened to 1/3 in the inspection of the semiconductor wafer in the process of manufacturing a product (one package) having three chips as one set.

  With the same technical idea, when manufacturing a product (one package) having N chips as one set, the measurement time can be shortened to 1 / N in the inspection of the semiconductor wafer. Therefore, it is possible to shorten the time required to manufacture one package with a plurality of power MOSFETs 100 as one set, to improve the number of manufacturing production per unit time, and to reduce the manufacturing cost.

  Further, here, the case where the power MOSFET is inspected is described for the sake of explanation, but the present invention is not limited to this. For example, it can be used for inspection of a semiconductor wafer when a plurality of diodes are mounted as a single package.

It is a typical schematic diagram explaining an example of a wafer inspection device concerning Embodiment 1 of the present invention. It is a figure for demonstrating the wafer inspection method concerning Embodiment 1 of this invention. It is a typical schematic diagram explaining an example of a wafer inspection device concerning Embodiment 2 of the present invention. It is a figure explaining the conventional wafer inspection apparatus and. It is a figure explaining the conventional wafer inspection method. It is a figure which shows arrangement | positioning of the conventional good quality determination element.

Explanation of symbols

100 Power MOSEFT
101 Gate Aluminum Pad 102 Source Aluminum Pad 200 Inspection Device 201 Source Voltage Terminal 202 Source Current Terminal 203 Gate Voltage Terminal 204 Gate Current Terminal 205 Probe

Claims (7)

A wafer inspection apparatus in which a plurality of semiconductor elements mounted in one package are formed adjacent to each other,
A gate voltage terminal for simultaneously applying a gate voltage to the plurality of semiconductor elements;
The drain of the plurality of semiconductor devices - have a current terminal to measure the source current at the same time,
A plurality of first probes connected to a source current terminal;
A plurality of second probes connected to the gate current terminal;
Have
Contacting the plurality of first probes simultaneously with the source pads of adjacent semiconductor elements on the wafer;
Contacting the plurality of second probes simultaneously with the gate pads of adjacent semiconductor elements on the wafer;
A third probe connected to the source voltage terminal; and a fourth probe connected to the gate voltage terminal;
Contacting the third probe with a source pad of a first semiconductor element of the plurality of semiconductor elements in contact with the plurality of first probes;
The wafer inspection apparatus, wherein the fourth probe is brought into contact with a gate pad of the first semiconductor element among the plurality of semiconductor elements in contact with the plurality of second probes . The first probe and the second probe are provided corresponding to the number of adjacent semiconductor elements on the wafer to be mounted on one package.
The wafer inspection apparatus according to claim 1 . The semiconductor elements mounted on the one package and adjacent on the wafer are inspected as one set, and when it is determined as defective, the set is collectively determined as defective.
The wafer inspection apparatus according to claim 1 or 2 . The plurality of semiconductor elements are power MOSFETs
The wafer inspection apparatus according to claim 1. A method for inspecting a wafer in which a plurality of semiconductor elements mounted in one package are formed adjacent to each other,
Applying a gate voltage simultaneously to the plurality of semiconductor elements;
Simultaneously measuring drain-source currents of the plurality of semiconductor elements ;
A plurality of first probes connected to source current terminals are simultaneously brought into contact with source pads of adjacent semiconductor elements on the wafer;
A plurality of second probes connected to a gate current terminal are simultaneously brought into contact with gate pads of adjacent semiconductor elements on the wafer;
Bringing a third probe connected to a source voltage terminal into contact with one of the source pads in contact with the plurality of first probes;
A fourth probe connected to a gate voltage terminal is brought into contact with one of the gate pads in contact with the plurality of second probes;
An inspection method for a wafer, in which adjacent semiconductor elements mounted on one package are inspected as one set, and when it is determined as defective, the set is collectively determined as defective . The first probe and the second probe are provided corresponding to the number of adjacent semiconductor elements on the wafer to be mounted on one package.
The wafer inspection method according to claim 5 . The plurality of semiconductor elements are power MOSFETs
The wafer inspection method according to claim 5 or 6.

Images