CN103837809B - The IC layout of test MOSFET matching and method of testing - Google Patents
The IC layout of test MOSFET matching and method of testing Download PDFInfo
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- CN103837809B CN103837809B CN201210484452.2A CN201210484452A CN103837809B CN 103837809 B CN103837809 B CN 103837809B CN 201210484452 A CN201210484452 A CN 201210484452A CN 103837809 B CN103837809 B CN 103837809B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
Abstract
The invention discloses a kind of integrated circuit layout testing MOSFET matching and method of testing, main contents include: be positioned at the first weld pad group adjacent on semiconductor base, a MOSFET group, the first wire and with described first weld pad group, a MOSFET group, the second weld pad group of the first wire specular and the 2nd MOSFET group, the second wire.In the scheme of the embodiment of the present invention, due to above-mentioned image symmetrical relations, ensure that the grid of a MOSFET in a MOSFET group, drain electrode, the length of source-substrate to the wire of corresponding weld pad, identical to the length of the wire of corresponding weld pad with grid, drain electrode, source-substrate in the 2nd MOSFET in the 2nd MOSFET group, the length of wire is identical means that resistance is identical, therefore, when utilizing this kind of integrated circuit layout to test MOSFET matching, the accuracy of test result is higher.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of MOSFET matching of testing
IC layout, IC layout method and method of testing.
Background technology
In integrated circuit (Integrated Circuit, IC) technical process, due to technique uncertainty and with
The reasons such as chance error difference, some the most duplicate metal-oxide-semiconductor field effect ts (Metal Oxide
Semiconductor Field Effect Transistor, MOSFET) practice on be devious, this partially
Difference is referred to as the mismatch (mismatch) of device.This mismatch is mainly reflected in device electric parameter
In change, such as the threshold voltage (V of MOSFETt), cut-off current I (Ioff), saturation current (Ids), temperature
The change of coefficient etc..And the mismatch of these devices becomes the factor that must take in circuit design, no
Yield rate then can be caused the lowest, and therefore semiconductor manufacturer needs test to test each MOSET, it is thus achieved that
Substantial amounts of test data, and then the distribution of the electrical parameter of MOSFET is obtained according to described test data.
In order to improve testing efficiency, generally by MOSFET to be measured and the weld pad (PAD) that is used for subtest
Being laid out in structure as shown in Figure 1, wherein, 11 represent weld pad, and 12 represent MOSFET, each MOSFET
Drain electrode connect a corresponding weld pad (Fig. 1 will be used for connecting the weld pad of the drain electrode of MOSFET
Mark drain electrode (Drain)), the source electrode (Source) of all MOSFET is connected to (Fig. 1 on same weld pad
In do not show that annexation, but mark Source will be used for connecting on the weld pad of the source electrode of MOSFET), institute
The grid (Gate) having MOSFET is connected to same weld pad and (does not shows that annexation in Fig. 1, but incite somebody to action
Gate is identified on the weld pad connecting the grid of MOSFET), the substrate (Substrate) of all MOSFET
It is connected on same weld pad (Fig. 1 not show that annexation, but will be used for connecting the substrate of MOSFET
Weld pad on identify Substrate).
In the layout shown in described Fig. 1, each MOSFET to be measured is in line, for subtest
The weld pad of the electrical parameter of MOSFET is in line, when each MOSFET shown in Fig. 1 is tested,
The probe being used for testing in the probe card of the electrical parameter of MOSFET is pricked respectively and is connecting this MOSFET
Grid weld pad on, on the weld pad of the source electrode that connects this MOSFET, connect the drain electrode of this MOSFET
On weld pad, then by probe and weld pad to the grid of this MOSFET, source electrode, undercoat making alive, this
Time this MOSFTE drain electrode output electric current by with prick at the probe stream drained with it on weld pad being connected
To test machine, described test machine is for measuring the current value of MOFET or the instrument of cut-in voltage value, institute
State probe card for connecting test machine and MOSFTE, test 2N MOSFET and with this 2N
After the 2N+1 adjacent for MOSFET MOSFET, can be determined both according to by both measurement results
Matching.
But, in above-mentioned layout, although 2N MOSFET and the 2N+1 MOSFET is adjacent,
But connect their source electrode to differ with the length of the wire of the weld pad for being connected source electrode, connect them
Grid may differ, connect their substrate to use to the length of wire of the weld pad for connecting grid
Length in the wire of the weld pad connecting substrate may differ, and connects their drain electrode to for connecting
Each the length of the wire of the weld pad of drain electrode may differ, and the difference of the length of this wire means wire
The difference of resistance, the difference of this kind of resistance can cause the electrical parameter tested out error occur, therefore, profit
Test MOSFET matching by the layout of test MOSFET matching of the prior art and there is test
The problem that the accuracy of result is the highest.
Summary of the invention
Embodiments provide and a kind of test the integrated circuit layout of MOSFET matching, integrated electricity
Road layout method and method of testing, to solve to test MOSFET matching existence test knot in prior art
The problem that accuracy really is the highest.
A kind of integrated circuit layout testing metal-oxide-semiconductor field effect t MOSFET matching, including:
At least one test cell being positioned on same semiconductor substrate；
Described test cell includes: be positioned at the first weld pad group adjacent on semiconductor base and a MOSFET
Group；
And be positioned on described semiconductor base and described first weld pad group and a MOSFET group mirror image pair
The the second weld pad group claimed and the 2nd MOSFET group；Wherein, a described MOSFET group and second
MOSFET group is adjacent, and described first weld pad group includes the weld pad that 3+N is transversely arranged, and described second
MOSFET group includes that N number of transversely arranged MOSFET, described N are the positive integer more than 1；
And the first wire of being positioned on semiconductor substrate and the second wire, described first wire is respectively by first
3 weld pads in weld pad group respectively with the substrate of N number of MOSFET in a MOSFET group, grid,
Source electrode connect, and respectively by the N number of weld pad of residue in the first weld pad group respectively with in a MOSFET group
N number of MOSFET drain electrode be connected；Described second wire is respectively by 3 weld pads in the second weld pad group
It is connected with the substrate of N number of MOSFET in the 2nd MOSFET group, grid, source electrode respectively, and respectively
By in the second weld pad group remain N number of weld pad respectively with the N number of MOSFET in the 2nd MOSFET group
Drain electrode be connected, and described second wire and described first wire specular.
A kind of integrated circuit layout method testing metal-oxide-semiconductor field effect t MOSFET matching, institute
State integrated circuit layout method to include:
Thering is provided semiconductor base, arrange multiple test cell thereon, wherein, each test cell includes
The first adjacent weld pad group and a MOSFET group；And with described first weld pad group and a MOSFET
Second weld pad group of group specular and the 2nd MOSFET group；Wherein, a described MOSFET group and
2nd MOSFET group is adjacent, and described first weld pad group includes the weld pad that 3+N is transversely arranged, and described the
Two MOSFET groups include N number of transversely arranged MOSFET；Described N is the whole number more than 1；
For each test cell, by the first wire respectively by 3 weld pads in the first weld pad group respectively with
The substrate of N number of MOSFET in oneth MOSFET group, grid, source electrode connect, and respectively by the
In one weld pad group remain N number of weld pad respectively with the leakage of the N number of MOSFET in a MOSFET group
The most connected；By the second wire respectively by 3 weld pads in the second weld pad group respectively with the 2nd MOSFET
The substrate of N number of MOSFET in group, grid, source electrode connect, and respectively by the second weld pad group
Remain the drain electrode respectively with the N number of MOSFET in the 2nd MOSFET group of N number of weld pad to be connected；Described
First wire and described second wire specular.
A kind of method utilizing said integrated circuit layout that the matching of MOSFET is tested, described
Method includes:
By 3 probes in probe card respectively with the grid of the MOSFET being connected in a MOSFET group,
Source electrode, the weld pad contact of substrate；
By probe, the grid of MOSFET in the oneth MOSFET group, source electrode, undercoat are powered up
Pressure；
Another probe in probe card is contacted with the weld pad of the drain electrode connecting a MOSFET；
MOSFET drain electrode electricity under described voltage is obtained by the test machine being connected with probe card
Stream and cut-in voltage, described test machine is for measuring the electric current of the probe output in the probe card being attached thereto
Size；
By 3 probes in probe card respectively with the grid of the MOSFET being connected in the 2nd MOSFET group,
Source electrode, the weld pad contact of substrate；
By probe, the grid of MOSFET in the 2nd MOSFET group, source electrode, substrate are applied institute
State voltage；
Another probe in probe card is contacted with the weld pad of the drain electrode connecting the 2nd MOSFET；
The 2nd MOSFET drain electrode electricity under described voltage is read by the test machine being connected with probe card
Stream and cut-in voltage, a described MOSFET and the 2nd MOSFET specular；
When described MOSFET drain current under described voltage and described 2nd MOSFET are in institute
State the drain current under voltage or cut-in voltage inconsistent time, determine a MOSFET and the 2nd MOSFET
Do not mate.
In the scheme of the embodiment of the present invention, due to described first weld pad group, a MOSFET group,
First wire respectively with the second weld pad group, the 2nd MOSFET group, the second wire specular, it is ensured that
The grid of a MOSFET in oneth MOSFET group, drain electrode, source-substrate are led to corresponding weld pad
The length of line, with the 2nd MOSFET in the 2nd MOSFET group of a MOSFET mirror image
Middle grid, drain electrode, source-substrate are identical to the length of the wire of corresponding weld pad, the identical meaning of length of wire
Resistance identical, therefore, when utilizing this kind of integrated circuit layout to test MOSFET matching, test
The accuracy of result is higher.
Accompanying drawing explanation
Fig. 1 is the integrated circuit layout schematic diagram of the test MOSFET matching in background technology；
Fig. 2 is a kind of integrated circuit layout testing MOSFET matching in the embodiment of the present invention one
Structural representation；
Fig. 3 is the electrical block diagram under the integrated circuit layout in the embodiment of the present invention one；
Fig. 4 is a kind of integrated circuit layout side testing MOSFET matching in the embodiment of the present invention two
Method schematic diagram；
Fig. 5 is the method flow diagram that the matching to MOSFET in the embodiment of the present invention three is tested；
Fig. 6 is the method flow diagram that the matching to MOSFET in the embodiment of the present invention three is tested；
Fig. 7 is the method flow diagram that the matching to MOSFET in the embodiment of the present invention three is tested.
Detailed description of the invention
Combine Figure of description in detail below the embodiment of the present invention is described in detail.
Embodiment one
As in figure 2 it is shown, be a kind of integrated electricity testing MOSFET matching in the embodiment of the present invention one
The structural representation of road layout, including: at least one test cell 11 being positioned on same semiconductor substrate；
Described test cell includes: the first weld pad group the 21, the oneth MOSFET being positioned on semiconductor base
Group the 22, second weld pad group the 23, the 2nd MOSFET group the 24, first wire 25 and the second wire 26；
Described first weld pad group 21 and a MOSFET group 22 are adjacent；
Described second weld pad group 23 and the 2nd MOSFET group 24 and described first weld pad group 21 and first
MOSFET group 22 specular；
A described MOSFET group 22 and the 2nd MOSFET group 24 are adjacent；
Wherein, described first weld pad group 21 includes 3+N transversely arranged weld pad, a described MOSFET
Group includes that N described in N number of transversely arranged MOSFET is the positive integer more than 1；
Due to the second weld pad group the 23, the 2nd MOSFET group 24 and described first weld pad group 21, first
MOSFET group 22 specular, therefore, described second weld pad group 23 also includes that 3+N is individual transversely arranged
Weld pad, described 2nd MOSFET group 24 also includes N number of transversely arranged MOSFET；
Described first wire 25 is identical with the material of the second wire 26；
Described first wire 25 respectively by 3 weld pads in the first weld pad group 21 respectively with a MOSFET
The substrate of N number of MOSFET in group 22, grid, source electrode connect, and respectively by the first weld pad group 21
In N number of weld pad drain electrode with the N number of MOSFET in a MOSFET group 22 respectively that remains be connected；
Described second wire 26 respectively by 3 weld pads in the second weld pad group 23 respectively with the 2nd MOSFET
The substrate of N number of MOSFET in group 24, grid, source electrode connect, and respectively by the second weld pad group
Remain the drain electrode respectively with the N number of MOSFET in the 2nd MOSFET group 24 of N number of weld pad to be connected, and
Described second wire 26 and described first wire 25 specular.
In the plurality of test cell, the size of MOSFET between each test cell can be identical, it is possible to
To differ, such as, the size of the MOSFET in a test cell in multiple test cells is
The a length of 0.5um of the wide 20um of MOSFET, raceway groove, in another test cell in multiple test cells
The size of MOSFET be the wide 10um of MOSFET, a length of 0.5um of raceway groove, described each test is single
MOSFET in unit is all NMOSFET or is all PMOSFET.
In the scheme of the embodiment of the present invention one, due to described first weld pad group, a MOSFET group,
First wire respectively with the second weld pad group, the 2nd MOSFET group, the second wire specular, it is ensured that
The grid of a MOSFET in oneth MOSFET group, drain electrode, source-substrate are led to corresponding weld pad
The 2nd MOSFET in the length of line, with the 2nd MOSFET group (the 2nd MOSFET and described the
One MOSFET specular) in grid, drain electrode, source-substrate identical to the length of the wire of corresponding weld pad,
The length of wire is identical means that resistance is identical, therefore, utilizes this kind of integrated circuit layout to test
During MOSFET matching, test accuracy is higher.
In order to improve the utilization rate of semiconductor substrate, and facilitate follow-up test machine to this kind of integrated circuit layout
The test of the product made, further, the weld pad in described first weld pad group 21 equidistantly arranges, institute
The MOSFET stated in a MOSFET group 22 equidistantly arranges, and a described MOSFET group 22
The perpendicular bisector of the line segment at the perpendicular bisector of the line segment at place and the place of the first weld pad group 21 overlaps.
Due to the second weld pad group the 23, the 2nd MOSFET group 24 and described first weld pad group 21, first
MOSFET group 22 specular, therefore, between MOSFET in described 2nd MOSFET group 22 etc.
Away from arrangement, and the perpendicular bisector of the line segment at described 2nd MOSFET group 22 place and the second weld pad group 21
Place line segment perpendicular bisector overlap.
In order to make the grid of MOSFET more in a MOSFET group and the 2nd MOSFET group
Conductor length between pole, drain electrode, source electrode, substrate and corresponding weld pad is identical, in order to can test simultaneously
Matching between multiple MOSFET, further, described N is the even number more than 1, and the first weldering
In the N/2+1 weld pad in pad group, the N/2+2 weld pad, the N/2+3 weld pad one with this
The grid of all MOSEFT in one MOSEFT group is connected；
This N/2+1 weld pad, the N/2+2 weld pad, the N/2+3 weld pad are not connected with grid
Weld pad in one be connected with the source electrode of all MOSEFT in a MOSEFT group；
This N/2+1 weld pad, the N/2+2 weld pad, the N/2+3 weld pad do not have and grid or source
The weld pad being extremely connected is connected with the substrate of all MOSEFT in a MOSEFT group；
The grid of the n-th MOSEFT in oneth MOSEFT group, source electrode, substrate, drain electrode are with corresponding
The grid of N-n+1 MOSEFT in the layout of the wire between weld pad and a MOSEFT group,
The layout of the wire between source electrode, substrate, drain electrode and corresponding weld pad is identical (includes two kinds of situations: false here
If the grid of the n-th MOSEFT in a MOSEFT group, source electrode, substrate, drain electrode are with corresponding
The layout of the wire between weld pad is first row mode for cloth, the cloth obtained after this first row mode for cloth flip horizontal
Office's mode is second row mode for cloth, then N-n+1 MOSEFT in a MOSEFT group
The layout of the wire between grid, source electrode, substrate, drain electrode and corresponding weld pad is first row mode for cloth or second
All claim during arrangement mode the n-th MOSEFT in its layout and a described MOSEFT group grid,
The layout of the wire between source electrode, substrate, drain electrode and corresponding weld pad is identical).
Under said integrated circuit layout, the n-th MOSFET in a MOSFET group, first
The N-n+1 MOSFET in MOSFET group, the n-th MOSFET in the 2nd MOSFET group,
The grid of N-n+1 MOSFET in 2nd MOSFET group, source electrode, drain electrode, substrate are with corresponding
Weld pad between the identical length of wire be positive integer less than or equal to N/2 more than 0 with, described n.
For MOSFET arrangement closely, save semiconductor-based base space, preferably utilize testing cushion, enter
One step, described integrated circuit layout also includes the privates being positioned on semiconductor substrate；
Described privates by the source electrode of a MOSFET, grid, substrate respectively with the 2nd MOSFET
Source electrode, grid, substrate be connected, a described MOSFET is the MOSFET in a MOSFET group,
Described 2nd MOSFET is the MOSFET in the 2nd MOSFET group, and a MOSFET and
Two MOSFET specular.
After using said integrated circuit layout, due to small-sized (the um level) of MOSFET, therefore,
The n-th MOSFET in oneth MOSFET group, the N-n+1 in a MOSFET group
The length of the wire between the grid of MOSFET, source electrode, substrate with corresponding weld pad, with the 2nd MOSFET
The n-th MOSFET in group, the grid of N-n+1 MOSFET in the 2nd MOSFET group,
Conductor length approximately equal between source electrode, substrate and corresponding weld pad, therefore, it can as calibration tape
Facilitate, in the case of the accuracy ensureing test, the coupling of test MOSFET can be improved simultaneously
The efficiency of property.
When described N is 2, the electrical block diagram under said integrated circuit layout can as it is shown on figure 3,
In figure 3, MOSFET1 and MOSFET2 is a MOSFET group, MOSFET3 and MOSFET
4 is the 2nd MOSFET group, adjacent with a MOSFET group for the first weld pad group, with second
MOSFET group adjacent for the second weld pad group, the line between the first weld pad and a MOSFET group is
First wire, the line between the second weld pad and the 2nd MOSFET group is the second wire, a MOSFET
Line between group and the 2nd MOSFET group is privates.
In the scheme of the embodiment of the present invention, due to described first weld pad group, a MOSFET group,
First wire respectively with the second weld pad group, the 2nd MOSFET group, the second wire specular, it is ensured that
The grid of a MOSFET in oneth MOSFET group, drain electrode, source-substrate are led to corresponding weld pad
The length of line, with the 2nd MOSFET in the 2nd MOSFET group of a MOSFET mirror image
Middle grid, drain electrode, source-substrate are identical to the length of the wire of corresponding weld pad, the identical meaning of length of wire
Resistance identical (while that the material of making wire and conductive wire cross-section size being homogeneous), therefore, utilize this kind
When integrated circuit layout tests MOSFET matching, the accuracy of test result is higher.
Embodiment two
As shown in Figure 4, for a kind of test metal-oxide-semiconductor field effect t in the embodiment of the present invention two
The integrated circuit layout method schematic diagram of MOSFET matching, described integrated circuit layout method includes following
Step:
Step 401: semiconductor base is provided, multiple test cell, wherein, each test are set thereon
Unit includes the first adjacent weld pad group and a MOSFET group；And with described first weld pad group and
Second weld pad group of the oneth MOSFET group specular and the 2nd MOSFET group；Wherein, described first
Weld pad group includes 3+N transversely arranged weld pad, and described 2nd MOSFET group includes N number of transversely arranged
MOSFET；A described MOSFET group and the 2nd MOSFET group are adjacent, and described N is more than 1
Whole number；
Step 402: for each test cell, by the first wire respectively by 3 in the first weld pad group
Weld pad is connected with the substrate of N number of MOSFET in a MOSFET group, grid, source electrode respectively, with
And the first weld pad group will remain N number of weld pad N number of with a MOSFET group respectively respectively
The drain electrode of MOSFET is connected；
Step 403: by the second wire respectively by 3 weld pads in the second weld pad group respectively with second
The substrate of N number of MOSFET in MOSFET group, grid, source electrode connect, and weld second respectively
In pad group remain N number of weld pad respectively with the drain electrode phase of the N number of MOSFET in the 2nd MOSFET group
Even；Described first wire and described second wire specular.
Further, the weld pad in described first weld pad group equidistantly arranges, a described MOSFET group
In MOSFET equidistantly arrange, and the perpendicular bisector of the line segment at a described MOSFET group place
Overlap with the perpendicular bisector of the line segment at the place of the first weld pad group.
Further, described N is the even number more than 1, and the N/2+1 weld pad in the first weld pad group,
In the N/2+2 weld pad, the N/2+3 weld pad one and owning in a MOSEFT group
The grid of MOSEFT is connected；
This N/2+1 weld pad, the N/2+2 weld pad, the N/2+3 weld pad are not connected with grid
Weld pad in one be connected with the source electrode of all MOSEFT in a MOSEFT group；
This N/2+1 weld pad, the N/2+2 weld pad, the N/2+3 weld pad do not have and grid or source
The weld pad being extremely connected is connected with the substrate of all MOSEFT in a MOSEFT group；
The grid of the n-th MOSEFT in oneth MOSEFT group, source electrode, substrate, drain electrode are with corresponding
The grid of N-n+1 MOSEFT in the layout of the wire between weld pad and a MOSEFT group,
The layout of the wire between source electrode, substrate, drain electrode and corresponding weld pad is identical, and described n is little more than or equal to 1
In the positive integer equal to N.
Further, described integrated circuit layout method also includes:
By privates by the source electrode of a MOSFET, grid, substrate respectively with the 2nd MOSFET
Source electrode, grid, substrate be connected, a described MOSFET is the MOSFET in a MOSFET group,
Described 2nd MOSFET is the MOSFET in the 2nd MOSFET group, and a MOSFET and
Two MOSFET specular.
Embodiment three
Common, the system testing the matching of MOSFET includes: probe card, test machine,
Unencapsulated integrated circuit, probe card is used as test interface, by the probe in probe card and integrated circuit
Weld pad contact time, the signal of telecommunication of integrated circuit can be led to test machine, and then by test machine to telecommunications
Number intensity measure.The embodiment of the present invention three is this kind of test system and according to survey in embodiment one
The unencapsulated IC products that the integrated circuit layout of examination MOSFET matching is produced, described
The method that the matching of MOSFET is tested, as it is shown in figure 5, said method comprising the steps of:
Step 501: by 3 probes in probe card respectively be connected in a MOSFET group
The grid of MOSFET, source electrode, the weld pad contact of substrate；
Step 502: by probe to the grid of MOSFET in a MOSFET group, source electrode,
Undercoat making alive；
Step 503: another probe in probe card is connect with the weld pad of the drain electrode being connected a MOSFET
Touch；
Step 504: obtain a MOSFET under described voltage by the test machine being connected with probe card
Drain current and cut-in voltage, described test machine is for measuring the probe output in the probe card that is attached thereto
The size of electric current and the size of cut-in voltage；
By above-mentioned steps 501-step 504 complete to a described MOSFET apply described in
The test of the drain current under voltage and the test of cut-in voltage.
Step 505: by 3 probes in probe card respectively be connected in the 2nd MOSFET group
The grid of MOSFET, source electrode, the weld pad contact of substrate；
Step 506: by probe to the grid of MOSFET in the 2nd MOSFET group, source electrode,
Substrate applies described voltage；
Step 507: another probe in probe card is connect with the weld pad of the drain electrode being connected the 2nd MOSFET
Touch；
Step 508: read the 2nd MOSFET under described voltage by the test machine being connected with probe card
Drain current and cut-in voltage, a described MOSFET and the 2nd MOSFET specular；
By above-mentioned steps 505-step 508 complete to described 2nd MOSFET apply described in
The test of the drain current under voltage and the test of cut-in voltage.
Step 509: when described MOSFET drain current and described second under described voltage
When MOSFET drain current under described voltage or cut-in voltage are inconsistent, determine a MOSFET
Do not mate with the 2nd MOSFET.
Preferably, also include, when described integrated circuit layout, the privates that is positioned on semiconductor substrate；Described
Privates by the source electrode of a MOSFET, grid, substrate respectively with the source electrode of the 2nd MOSFET,
Grid, substrate are connected, and a described MOSFET is the MOSFET in a MOSFET group, described
2nd MOSFET is the MOSFET in the 2nd MOSFET group, and a MOSFET and second
During MOSFET specular, this integrated circuit layout the unencapsulated integrated circuit produced is carried out
Joining property test time, described method of testing as shown in Figure 6, for:
Step 601: by 3 probes in probe card respectively be connected in a MOSFET group
The grid of MOSFET, source electrode, the weld pad contact of substrate；
Step 602: by probe to the grid of MOSFET in a MOSFET group, source electrode,
Undercoat making alive；
Step 603: another probe in probe card is connect with the weld pad of the drain electrode being connected a MOSFET
Touch；
Step 604: obtain a MOSFET under described voltage by the test machine being connected with probe card
Drain current and cut-in voltage；
Step 605: another probe described is contacted with the weld pad of the drain electrode connecting the 2nd MOSFET；
Due in described unencapsulated integrated circuit, described privates by the source electrode of a MOSFET,
Grid, substrate are connected with the source electrode of the 2nd MOSFET, grid, substrate respectively, when 3 probes respectively
When contacting with the grid of MOSFET connected in a MOSFET group, source electrode, the weld pad of substrate, should
3 probes are providing voltage for the grid of MOSFET in a MOSFET group, source electrode, substrate
Meanwhile, also provide voltage for the grid of MOSFET in the 2nd MOSFET group, source electrode, substrate, because of
This, in this step 605, it may not be necessary to by 3 probes respectively be connected in the 2nd MOSFET group
The grid of MOSFET, source electrode, the weld pad contact of substrate, decrease testing procedure, and then improve test
Efficiency.
Step 606: obtain the 2nd MOSFET under described voltage by the test machine being connected with probe card
Drain current and cut-in voltage；
Step 607: when described MOSFET drain current and described second under described voltage
When MOSFET drain current under described voltage or cut-in voltage inconsistent (namely differing), determine
Oneth MOSFET and the 2nd MOSFET does not mates.
Further, in order to improve testing efficiency, described method of testing is as it is shown in fig. 7, be:
Step 701-step 706, described step 701-step 706 is identical with step 601-step 606.
Step 707: another probe described is contacted with the weld pad of the drain electrode connecting the 3rd MOSFET, institute
Stating the 3rd MOSFET is the MOSFET in a MOSFET group, and if a MOSFET be
The n-th MOSFET in one MOSFET group, then the 3rd MOSFET is in a MOSFET group
The N-n+1 MOSFET；
Step 708: obtain the 3rd MOSFET under described voltage by the test machine being connected with probe card
Drain current and cut-in voltage；
Step 709: another probe described is contacted with the weld pad of the drain electrode connecting the 4th MOSFET, institute
Stating the 4th MOSFET is the MOSFET in the 2nd MOSFET group, and if the 2nd MOSFET be
The n-th MOSFET in two MOSFET groups, then the 4th MOSFET is in the 2nd MOSFET group
The N-n+1 MOSFET；
Step 710: obtain the 4th MOSFET under described voltage by the test machine being connected with probe card
Drain current and cut-in voltage；
Step 711: when described MOSFET drain current under described voltage, described second
MOSFET drain current under described voltage, described 3rd MOSFET drain electrode under described voltage
When electric current, described 4th MOSFET drain current under described voltage all differ, determine first
MOSFET, the 2nd MOSFET, the 3rd MOSFET, the 4th MOSFET do not mate；
When described four MOSFET there being two MOSFET drain current under described voltage the most identical
Time, determine that other two MOSFET is not mated with said two MOSFET；
When described four MOSFET there being three MOSFET drain current under described voltage the most identical
Time, determine that remaining MOSFET does not mates with described three MOSFET.
In actual application, it is possible to use the MOSFET of the test cell that said method test is different to size
Test, when passing through probe and the weld pad grid to the MOSFET in test cell, substrate, source
Pole applies different voltage, makes MOSFET be operated in linear zone or saturation region, and test is arrived a large amount of
Result utilizes mathematical statistics method to be analyzed, and obtains the electrical parameter characteristic of MOSFET.
After all NMOSFET test of size a certain in test cell, can obtain and exist
When NMOSFET is operated in linear zone or is operated in saturation region, first under certain grid voltage Vg
The drain current I of the n-th NMOSFET in MOSFET group1nds, in the 2nd MOSFET group
The drain current I of n NMOSFET2nds, by I2ndsWith I1ndsDo difference, obtain sampleDescribed n
For being less than or equal to the positive integer of N more than or equal to 1, calculate sample's
Revising plan；
After various sizes of NMOSFET is tested, said method is utilized to can get the pin under described Vg
Revising plan to this size, and then these data are carried out linear fit to (size, revising plan),
I.e. can get the telecommunications distribution character of NMOSFET.
Obviously, those skilled in the art can carry out various change and modification without deviating from this to the present invention
Bright spirit and scope.So, if the present invention these amendment and modification belong to the claims in the present invention and
Within the scope of its equivalent technologies, then the present invention is also intended to comprise these change and modification.
Claims (10)
1. testing an integrated circuit layout for metal-oxide-semiconductor field effect t MOSFET matching, it is special
Levy and be, including: at least one test cell being positioned on same semiconductor substrate；
Described test cell includes: be positioned at the first weld pad group adjacent on semiconductor substrate and a MOSFET
Group；
And be positioned on described semiconductor substrate and described first weld pad group and a MOSFET group mirror image pair
The the second weld pad group claimed and the 2nd MOSFET group；Wherein, a described MOSFET group and second
MOSFET group is adjacent, and described first weld pad group includes the weld pad that 3+N is transversely arranged, and described first
MOSFET group includes that N number of transversely arranged MOSFET, described N are the positive integer more than 1；
And the first wire of the material being positioned on semiconductor substrate and the second wire, described first wire is respectively
By 3 weld pads in the first weld pad group respectively with the substrate of the N number of MOSFET in a MOSFET group,
Grid, source electrode connect, and respectively by the N number of weld pad of residue in the first weld pad group respectively with a MOSFET
The drain electrode of the N number of MOSFET in group is connected；Described second wire is respectively by 3 in the second weld pad group
Weld pad is connected with the substrate of N number of MOSFET in the 2nd MOSFET group, grid, source electrode respectively, and
Second weld pad group will remain N number of weld pad N number of with the 2nd MOSFET group respectively respectively
The drain electrode of MOSFET is connected, and described second wire and described first wire specular.
2. integrated circuit layout as claimed in claim 1, it is characterised in that
Weld pad in described first weld pad group equidistantly arranges, the MOSFET in a described MOSFET group
Equidistantly arrangement, and the perpendicular bisector of the line segment at a described MOSFET group place and the first weld pad group
Place line segment perpendicular bisector overlap.
3. integrated circuit layout as claimed in claim 2, it is characterised in that described N is more than 1
The N/2+1 weld pad in even number, and the first weld pad group, the N/2+2 weld pad, the N/2+3 weld pad
In one be connected with the grid of all MOSEFT in a MOSEFT group；
This N/2+1 weld pad, the N/2+2 weld pad, the N/2+3 weld pad are not connected with grid
Weld pad in one be connected with the source electrode of all MOSEFT in a MOSEFT group；
This N/2+1 weld pad, the N/2+2 weld pad, the N/2+3 weld pad do not have and grid or source
The weld pad being extremely connected is connected with the substrate of all MOSEFT in a MOSEFT group；
The grid of the n-th MOSEFT in oneth MOSEFT group, source electrode, substrate, drain electrode are with corresponding
The grid of N-n+1 MOSEFT in the layout of the wire between weld pad and a MOSEFT group,
The layout of the wire between source electrode, substrate, drain electrode and corresponding weld pad is identical, and described n is little more than or equal to 1
In the positive integer equal to N.
4. integrated circuit layout as claimed in claim 2 or claim 3, it is characterised in that described integrated circuit
Layout also includes the privates being positioned on semiconductor substrate；
Described privates by the source electrode of a MOSFET, grid, substrate respectively with the 2nd MOSFET
Source electrode, grid, substrate be connected, a described MOSFET is the MOSFET in a MOSFET group,
Described 2nd MOSFET is the MOSFET in the 2nd MOSFET group, and a MOSFET and
Two MOSFET specular.
5. test an integrated circuit layout method for metal-oxide-semiconductor field effect t MOSFET matching,
It is characterized in that, described integrated circuit layout method includes:
Thering is provided semiconductor substrate, arrange multiple test cell thereon, wherein, each test cell includes
The first adjacent weld pad group and a MOSFET group；And with described first weld pad group and a MOSFET
Second weld pad group of group specular and the 2nd MOSFET group；Wherein, a described MOSFET group and
2nd MOSFET group is adjacent, and described first weld pad group includes the weld pad that 3+N is transversely arranged, and described the
Two MOSFET groups include N number of transversely arranged MOSFET；Described N is the whole number more than 1；
For each test cell, by the first wire respectively by 3 weld pads in the first weld pad group respectively with
The substrate of N number of MOSFET in oneth MOSFET group, grid, source electrode connect, and respectively by the
In one weld pad group remain N number of weld pad respectively with the leakage of the N number of MOSFET in a MOSFET group
The most connected；By the second wire respectively by 3 weld pads in the second weld pad group respectively with the 2nd MOSFET
The substrate of N number of MOSFET in group, grid, source electrode connect, and respectively by the second weld pad group
Remain the drain electrode respectively with the N number of MOSFET in the 2nd MOSFET group of N number of weld pad to be connected；Described
First wire and described second wire specular.
6. integrated circuit layout method as claimed in claim 5, it is characterised in that
Weld pad in described first weld pad group equidistantly arranges, the MOSFET in a described MOSFET group
Equidistantly arrangement, and the perpendicular bisector of the line segment at a described MOSFET group place and the first weld pad group
Place line segment perpendicular bisector overlap.
7. integrated circuit layout method as claimed in claim 6, it is characterised in that described N is for being more than
The N/2+1 weld pad in the even number of 1, and the first weld pad group, the N/2+2 weld pad, N/2+3
In weld pad one is connected with the grid of all MOSEFT in a MOSEFT group；
This N/2+1 weld pad, the N/2+2 weld pad, the N/2+3 weld pad are not connected with grid
Weld pad in one be connected with the source electrode of all MOSEFT in a MOSEFT group；
This N/2+1 weld pad, the N/2+2 weld pad, the N/2+3 weld pad do not have and grid or source
The weld pad being extremely connected is connected with the substrate of all MOSEFT in a MOSEFT group；
The grid of the n-th MOSEFT in oneth MOSEFT group, source electrode, substrate, drain electrode are with corresponding
The grid of N-n+1 MOSEFT in the layout of the wire between weld pad and a MOSEFT group,
The layout of the wire between source electrode, substrate, drain electrode and corresponding weld pad is identical, and described n is little more than or equal to 1
In the positive integer equal to N.
Integrated circuit layout method the most as claimed in claims 6 or 7, it is characterised in that described integrated
Circuit arrangement method also includes:
For each test cell, by privates by the source electrode of a MOSFET, grid, substrate
Being connected with the source electrode of the 2nd MOSFET, grid, substrate respectively, a described MOSFET is first
MOSFET in MOSFET group, described 2nd MOSFET is in the 2nd MOSFET group
MOSFET, and a MOSFET and the 2nd MOSFET specular.
9. one kind utilizes the claim 1-3 arbitrary described integrated circuit layout matching to MOSFET
The method carrying out testing, it is characterised in that described method includes:
By 3 probes in probe card respectively with the grid of the MOSFET being connected in a MOSFET group,
Source electrode, the weld pad contact of substrate；
By probe, the grid of MOSFET in the oneth MOSFET group, source electrode, undercoat are powered up
Pressure；
Another probe in probe card is contacted with the weld pad of the drain electrode connecting a MOSFET；
MOSFET drain electrode electricity under described voltage is obtained by the test machine being connected with probe card
Stream and cut-in voltage, described test machine is for measuring the electric current of the probe output in the probe card being attached thereto
Size；
By 3 probes in probe card respectively with the grid of the MOSFET being connected in the 2nd MOSFET group,
Source electrode, the weld pad contact of substrate；
By probe, the grid of MOSFET in the 2nd MOSFET group, source electrode, substrate are applied institute
State voltage；
Another probe in probe card is contacted with the weld pad of the drain electrode connecting the 2nd MOSFET；
The 2nd MOSFET drain electrode electricity under described voltage is read by the test machine being connected with probe card
Stream and cut-in voltage, a described MOSFET and the 2nd MOSFET specular；
When described MOSFET drain current under described voltage and described 2nd MOSFET are in institute
State the drain current under voltage or cut-in voltage inconsistent time, determine a MOSFET and the 2nd MOSFET
Do not mate.
10. method as claimed in claim 9, it is characterised in that when described integrated circuit layout also includes
The privates being positioned on semiconductor substrate；Described privates by the source electrode of a MOSFET, grid,
Substrate is connected with the source electrode of the 2nd MOSFET, grid, substrate respectively, and a described MOSFET is
MOSFET in one MOSFET group, described 2nd MOSFET is in the 2nd MOSFET group
MOSFET, and when a MOSFET and the 2nd MOSFET specular, described method is:
By 3 probes in probe card respectively with the grid of the MOSFET being connected in a MOSFET group,
Source electrode, the weld pad contact of substrate；
By probe, the grid of MOSFET in the oneth MOSFET group, source electrode, undercoat are powered up
Pressure；
Another probe in probe card is contacted with the weld pad of the drain electrode connecting a MOSFET；
MOSFET drain electrode electricity under described voltage is obtained by the test machine being connected with probe card
Stream and cut-in voltage, described test machine is for measuring the electric current of the probe output in the probe card being attached thereto
Size；
Another probe described is contacted with the weld pad of the drain electrode connecting the 2nd MOSFET；
The 2nd MOSFET drain electrode electricity under described voltage is obtained by the test machine being connected with probe card
Stream and cut-in voltage；
When described MOSFET drain current under described voltage and described 2nd MOSFET are in institute
State the drain current under voltage or cut-in voltage inconsistent time, determine a MOSFET and the 2nd MOSFET
Do not mate.
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| CN107422242A (en) * | 2016-05-23 | 2017-12-01 | 北大方正集团有限公司 | The test device and method of a kind of VDMOS chip |
| CN110187249A (en) * | 2018-02-22 | 2019-08-30 | 河南省无线发射传输管理中心 | A kind of high-power MOS tube detection system and method |
| CN111562481B (en) * | 2020-05-25 | 2022-08-02 | 中国电子科技集团公司第十三研究所 | Compound semiconductor chip on-chip test circuit based on power-on probe |
| US11892499B2 (en) | 2020-12-21 | 2024-02-06 | Changxin Memory Technologies, Inc. | Testing machine and testing method |
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| CN1979205A (en) * | 2005-12-08 | 2007-06-13 | 国际商业机器公司 | Methods for variability measurement of integrated circuit components and integrated circuit components |
| CN101281877A (en) * | 2007-04-03 | 2008-10-08 | 中芯国际集成电路制造(上海)有限公司 | Method for measuring MOS transistor dismatching features, territory pattern and forming method thereof |
| CN101883989A (en) * | 2007-12-06 | 2010-11-10 | 高通股份有限公司 | Method and apparatus for estimating resistance and capacitance of metal interconnects |
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| US7408372B2 (en) * | 2006-06-08 | 2008-08-05 | International Business Machines Corporation | Method and apparatus for measuring device mismatches |
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| CN1979205A (en) * | 2005-12-08 | 2007-06-13 | 国际商业机器公司 | Methods for variability measurement of integrated circuit components and integrated circuit components |
| CN101281877A (en) * | 2007-04-03 | 2008-10-08 | 中芯国际集成电路制造(上海)有限公司 | Method for measuring MOS transistor dismatching features, territory pattern and forming method thereof |
| CN101883989A (en) * | 2007-12-06 | 2010-11-10 | 高通股份有限公司 | Method and apparatus for estimating resistance and capacitance of metal interconnects |
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