CN106898562A - The method of the breakdown voltage of semiconductor structure and test grid oxic horizon - Google Patents
The method of the breakdown voltage of semiconductor structure and test grid oxic horizon Download PDFInfo
- Publication number
- CN106898562A CN106898562A CN201510960964.5A CN201510960964A CN106898562A CN 106898562 A CN106898562 A CN 106898562A CN 201510960964 A CN201510960964 A CN 201510960964A CN 106898562 A CN106898562 A CN 106898562A
- Authority
- CN
- China
- Prior art keywords
- transistor
- grid
- semiconductor structure
- voltage
- pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
Abstract
The method that the present invention provides the breakdown voltage of a kind of semiconductor structure and test grid oxic horizon, semiconductor structure includes:Multiple transistors, multiple diodes, multiple fuses, multiple first measurement pads and at least one second measurement pads;Each transistor includes being formed at the grid on a substrate and the source electrode in the substrate of the grid both sides and drain electrode, has a grid oxic horizon between the grid and the substrate;The positive pole of each diode connects the grid of a transistor, the negative pole of each diode is connected same first measurement pad with the grid of the transistor, one fuse, substrate connection the second measurement pad are set between the first measurement pad of the grid connection of the grid of each transistor and the transistor.In the present invention, breakdown voltage that can be simultaneously to multiple transistors is detected, shortens test period.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of semiconductor structure and test grid
The method of the breakdown voltage of oxide layer.
Background technology
With developing rapidly for semiconductor technology and greatly improving for microelectronic chip integrated level, integrated circuit sets
Meter and level of processing come into the nanoscale MOS epoch, influence the factor of device reliability to continuously emerge, thus
Cause nanometer MOS devices performance degradation.The pressure-resistant performance of grid oxic horizon is MOS device reliability assessment
Importance.Grid oxic horizon time-varying dielectric breakdown (Time-Dependent Dielectric Breakdown,
TDDB) it is one of important indicator of the pressure-resistant performance of grid oxic horizon, wherein, time-varying dielectric breakdown is and the time
Relevant a kind of dielectric punch-through.
With reference to shown in Fig. 1, the knot of the time-varying medium breakdown phenomenon of test grid oxic horizon of the prior art
Structure includes:Substrate 1, it is formed in substrate 1 and has source electrode 2, the source electrode 4 being formed in source electrode 2 and leakage
Pole 5, the grid 3 being formed on source electrode 2, the grid oxic horizon between grid 3 and substrate 1 are (in figure not
Show), metal level 6 and connector 7.With reference to shown in Fig. 1 and Fig. 2, using connector 7 respectively by grid 3,
Source electrode 4, drain electrode 5 and metal level 6 are drawn, and form an equivalent structure for metal-oxide-semiconductor, wherein, metal
Connector 7 on layer 6 draws substrate.
With reference to shown in Fig. 2, when the test of time-varying dielectric breakdown is carried out, source S, drain D and substrate B
Ground terminal is all connected with, voltage or electric current, and the gradually size of increase and decrease voltage or electric current is applied with grid G,
Until grid oxic horizon punctures, so as to test out a time-varying dielectric breakdown for sample grid oxide layer.
However, due to needing to carry out multiple reliability on multiple transistors in Fig. 1 in existing method of testing
Property measurement, the data to multiple transistors carry out statistical analysis, so as to obtain the voltage endurance of grid oxic horizon.
The content of the invention
It is an object of the present invention to provide the breakdown voltage of a kind of semiconductor structure and test grid oxic horizon
Method, solve the problems, such as to need in the prior art to measure a large amount of samples and obtain grid oxic horizon breakdown voltage.
In order to solve the above technical problems, the present invention provides a kind of semiconductor structure, including:Multiple transistors,
Multiple diodes, multiple fuses, multiple first measurement pads and at least one second measurement pads;
Each transistor includes being formed at the grid on a substrate and in the substrate of the grid both sides
Source electrode and drain electrode, between the grid and the substrate have a grid oxic horizon;
The positive pole of each diode connects the grid of a transistor, negative pole and the transistor of each diode
The same first measurement pad of grid connection, the of the grid connection of the grid of each transistor and the transistor
One fuse, substrate connection the second measurement pad are set between one measurement pad.
Optionally, the transistor is nmos pass transistor.
Optionally, p-well is formed with the substrate, the source electrode and drain electrode are formed in the p-well.
Optionally, the source electrode and the drain electrode is all connected with the second measurement pad.
Optionally, the number of the transistor is 25~30, and the number of the first measurement pad is 25
~30.
Optionally, the resistance of the diode is 5k Ω~10k Ω.
Optionally, the material of the fuse is polysilicon or metallic aluminium.
Optionally, the rated current of the fuse is 10-3Ampere~10-2Ampere.
Optionally, the first measurement pad is aluminium welding pad or copper pad, the second measurement pad for aluminium welding pad or
Copper pad.
Optionally, the semiconductor structure is located in the dicing lane of the substrate.
Accordingly, the present invention also provides a kind of method of the breakdown voltage for testing grid oxic horizon, using above-mentioned
Semiconductor structure, specifically include:
Apply first voltage on the described first measurement pad, apply and described first on the described first measurement pad
The second voltage of voltage reversal, and measure the current value of each transistor;
Increase the size of the first voltage successively, and accordingly measure the current value of each transistor, it is right
The breakdown voltage of the grid oxic horizon of each transistor should be drawn, grid oxic horizon described in statistical analysis
Voltage endurance.
Optionally, the second measurement pad earth terminal.
Optionally, after the grid oxic horizon of the transistor punctures, the fuse being connected with the transistor
Fusing.
Compared with prior art, breakdown voltage of the semiconductor structure that the present invention is provided in test grid oxic horizon
During, first applying a first voltage on the first measurement pad, electric current is flowed through by fuse, then first
Apply a reverse second voltage on measurement pad, and measure the electric current of each transistor.So apply repeatedly
Plus first voltage or second voltage, gradually increase the size of first voltage, and it is corresponding to test each transistor
Current value.After the grid oxic horizon of a certain transistor punctures, electric current increases suddenly so that with the crystal
The blown fuse of pipe connection, the first voltage is the breakdown voltage of the transistor gate oxide layer.However,
Path conducting where diode, it is ensured that remain to measure the electric current of the transistor.Finally, according to crystal
The current value of pipe, draws the breakdown voltage of each transistor, and statistical analysis draws the pressure-resistant of grid oxic horizon
Characteristic.In the present invention, time-varying medium breakdown phenomenon that can be simultaneously to multiple transistors is detected, is shortened
Test period.
Brief description of the drawings
Fig. 1 is the structural representation that test grid oxic horizon time-varying of the prior art punctures;
Fig. 2 is the structural representation of the transistor that test grid oxic horizon time-varying of the prior art punctures;
Fig. 3 is the schematic diagram of the semiconductor structure in one embodiment of the invention;
Fig. 4 is the cross-sectional view of the transistor in one embodiment of the invention;
Fig. 5 is the structural representation of the fuse in one embodiment of the invention;
Fig. 6 is the current direction schematic diagram of applying forward voltage on measuring and pad first in one embodiment of the invention;
Fig. 7 is the current direction schematic diagram of applying negative voltage on measuring and pad first in one embodiment of the invention.
Specific embodiment
Below in conjunction with schematic diagram to semiconductor structure of the invention and the breakdown voltage of test grid oxic horizon
Method be described in more detail, which show the preferred embodiments of the present invention, it should be appreciated that this area
Technical staff can change invention described herein, and still realize advantageous effects of the invention.Therefore,
Description below is appreciated that widely known for those skilled in the art, and is not intended as to the present invention
Limitation.
Core concept of the invention is, in parallel between the grid of each transistor and the first measurement pad to insure
Silk and diode, during the time-varying medium breakdown phenomenon of test grid oxic horizon, first in the first measurement
Apply a first voltage on pad, carry out stress test, electric current is flowed through by fuse, then on the first measurement pad
Apply a reverse second voltage, and measure the electric current of each transistor.So repeatedly apply first voltage or
Second voltage, gradually increases the size of first voltage, and tests the electric current of each transistor.When a certain crystal
After the grid oxic horizon of pipe punctures, electric current increases suddenly, the blown fuse being connected with the transistor, and this
One voltage is the breakdown voltage of the transistor gate oxide layer.However, the path conducting where diode,
The electric current for remaining to measure the transistor can be ensured.Finally, according to the current value of transistor, show that each is brilliant
The breakdown voltage of body pipe, and statistical analysis draws the voltage endurance of grid oxic horizon.In the present invention, Ke Yitong
When the time-varying medium breakdown phenomenon of multiple transistors is detected, shorten test period.
Semiconductor structure of the invention is described in detail below in conjunction with Fig. 3-Fig. 5.Semiconductor structure shows
It is intended to reference to shown in Fig. 3, semiconductor structure includes multiple transistors 10, the multiple transistor 10 is arranged
In one direction.With reference to shown in Fig. 3 and Fig. 4, each described transistor 10 includes substrate 11, is located at
Grid 17 on the substrate 11 and the source electrode in the substrate of the both sides of grid 17 15 and drain electrode 16,
There is a grid oxic horizon 13 between the grid 17 and the substrate 11.Therefore, each transistor 10 is
One four-terminal device, respectively including source S, drain D, grid G and substrate B.
Wherein, well region 12 and fleet plough groove isolation structure 14, the source electrode 15 are formed with the substrate 11
It is formed in the well region 12 with drain electrode 16, the fleet plough groove isolation structure 14 is used to isolate adjacent crystal
Pipe 10.By taking nmos pass transistor as an example, the well region 12 is p-well.By taking PMOS transistor as an example, institute
Well region 12 is stated for N traps.Certainly, other well known structure can also be formed with the substrate 11, herein
Repeat no more.
With continued reference to shown in Fig. 3, the grid 17 of each transistor 10 is all connected with one first measurement pad 21,
In the present embodiment, multiple transistors 10 are arranged in order, and multiple first measures pad 21 arranges successively, and accordingly
Arrangement in a same direction so that the transistor of more can be prepared on same device, and is saved
Save the area of device.In the present embodiment, the first measurement pad 21 is aluminium welding pad or copper pad, for surveying
Voltage is applied with during examination, the grid 17 to transistor 10 provides voltage or electric current.Additionally, the crystalline substance
The number of body pipe 10 is 25~30, also, the number of the first measurement pad 21 is 25~30.
For example, the number of transistor 10 is 26, the number of the first measurement pad 21 is 26.Certainly,
It will be appreciated by those skilled in the art that the number of transistor be not limited to 25~30, transistor 10
Number is more so that the result of test more prepares reliability.
The diode 30 be connected to each transistor 10 grid 17 and with transistor 10 this described
The first measurement pad 21 for being connected of the correspondence of grid 17 between, the connection of the positive pole of the diode 30 is described
Grid 17, negative pole connection the first measurement pad 21.
The fuse 40 be connected to each transistor 10 grid 17 and with transistor 10 this described
Grid 17 correspondence be connected it is described first measurement pad 21 between, that is to say, that fuse 40 and diode
30 is in parallel.In the present embodiment, the material of the fuse 40 is polysilicon or metal, its structural reference Fig. 5
It is shown, including narrow portion 42 and the portion wide 41 positioned at the both sides of narrow portion 42, in test process, fuse 40
Certain load current value, such as 10 can be born-3A~10-2A, when the electric current for passing through is more than the load current value
When, the narrow portion 42 of fuse 40 will fuse so that the branch road where fuse 40 disconnects.Need explanation
It is that the resistance of the diode 30 in the present embodiment is larger, such as 5K Ω~10k Ω, and it is far longer than fuse
40 resistance so that after diode 30 is in parallel with fuse 40, the electric current of the branch road where diode 30
Very little, branch road of the electric current mainly from where fuse 40 flows through, so that in test process, fuse 40
Current value where branch road is closer with the current value of transistor 10 so that follow-up on the first measurement pad 21
It is as a result more accurate when applied voltage carries out stress test.
Additionally, substrate 11 is connected with the described second measurement pad 22 so that the substrate B ends of each transistor 10
Uniform ground terminal connection.Also, the source electrode 15 of each transistor 10 and drain electrode 16 are padded with the second measurement
22 are connected.In the present embodiment, the second measurement earth terminal of pad 22 so that the source of each transistor 10
Pole 15, drain electrode 16 and substrate 11 are grounded.In the present embodiment, the second measurement pad 22 can be aluminium
Weld pad or copper pad.
Wherein, the semiconductor structure can be formed on the Cutting Road of Semiconductor substrate (or dicing lane),
Avoid taking the area of device region.All parts in the semiconductor structure (for example grid, source electrode, drain electrode,
Grid oxic horizon) shape can it is identical with all parts shape of the device in the device region to be measured or
It is similar.
Accordingly, the present invention also provide it is a kind of test grid oxic horizon breakdown voltage method, below in conjunction with Fig. 6,
Fig. 7 is specifically described to it, likewise, also entering so that transistor is as nmos pass transistor as an example in the present invention
Row explanation,
With reference to shown in Fig. 6, apply first voltage for a period of time on the described first measurement pad 21, for example
0.05s~0.10s, and gradually increase the size of first voltage, i.e., stress is carried out to each nmos pass transistor 10
Test.In the present embodiment, first voltage is forward voltage, and the of forward direction is applied with the first measurement pad 21
After one voltage, sense of current is as indicated by the arrows in fig. 6, that is to say, that in the every of semiconductor structure
The two ends of grid oxic horizon 13 of individual nmos pass transistor 10 are applied with voltage, and grid oxic horizon 13 forms electric capacity
Structure.Afterwards, with reference to shown in Fig. 7, one reverse second is applied with the described first measurement pad 21
Voltage, that is, be applied with the second voltage of negative sense, now, in the sense of current such as Fig. 7 in semiconductor structure
Shown in arrow.Meanwhile, measure the size of the current value of each nmos pass transistor 10.In test process,
Circulate in and first voltage and second voltage are applied with the first measurement pad 21, and gradually increase the big of first voltage
It is small, also, when negative voltage is applied, measure the current value of each nmos pass transistor 10.When certain
When the grid oxic horizon 13 of nmos pass transistor 10 punctures, electric current increases suddenly so that brilliant with the NMOS
The fuse 40 of the connection of body pipe 10 fuses, so that it is determined that the corresponding first voltage of point is nmos pass transistor
10 breakdown voltage.Hereafter, continue to increase the value of first voltage, by hitting for each nmos pass transistor 10
Wear voltage all to test out, finally, the breakdown voltage to all nmos pass transistors 10 carries out statistical analysis,
Draw the voltage endurance of the grid oxic horizon 13 of nmos pass transistor 10.
It should be noted that when the first voltage on the first measurement pad 21 reaches certain value, nmos pass transistor
After the fuse 40 of 10 connections melts, when being applied with the second voltage of negative sense on the first measurement pad 21, two
The conducting of pole pipe 30 so that the nmos pass transistor 10 can still form path, not influence to the NMOS
The measurement of the electric current of transistor 10, so as to draw the breakdown voltage of the nmos pass transistor 10.
In the present embodiment, illustrated so that transistor is as NMOS tube as an example, however, it is of the invention its
In his embodiment, transistor can also use PMOS transistor, the structure in its structure for being formed and Fig. 3
It is identical, it is same including source electrode, drain electrode, grid, substrate and grid oxic horizon in PMOS transistor,
This is appreciated that for those skilled in the art, will not be described here.When being tested using PMOS,
According to the characteristic of PMOS transistor, the voltage of negative sense is first applied with the first measurement pad, it is brilliant to PMOS
Body pipe carries out stress test, afterwards, is applied with the voltage of forward direction on the first measurement pad, and measure each PMOS
The current value of transistor, and the process is circulated, test draws the grid oxic horizon of each PMOS transistor
Breakdown voltage, the voltage endurance of statistical analysis grid oxic horizon.
In sum, in the present invention, during the time-varying medium breakdown phenomenon of test grid oxic horizon,
Diode and fuse are connected in parallel between the grid of transistor and the first measurement pad for being connected with the transistor, when
The grid oxic horizon of the transistor is breakdown, and after blown fuse, the path conducting where diode is protected
Card can measure the current value of transistor.In the present invention, time-varying medium that can be simultaneously to multiple transistors hits
Wear phenomenon to be detected, shorten test period.
Obviously, those skilled in the art can carry out various changes and modification without deviating from this hair to the present invention
Bright spirit and scope.So, if it is of the invention these modification and modification belong to the claims in the present invention and
Within the scope of its equivalent technologies, then the present invention is also intended to comprising these changes and modification.
Claims (13)
1. a kind of semiconductor structure, it is characterised in that including:Multiple transistors, multiple diodes, multiple
Fuse, multiple first measurement pads and at least one second measurement pads;
Each transistor includes being formed at the grid on a substrate and in the substrate of the grid both sides
Source electrode and drain electrode, between the grid and the substrate have a grid oxic horizon;
The positive pole of each diode connects the grid of a transistor, negative pole and the transistor of each diode
The same first measurement pad of grid connection, the of the grid connection of the grid of each transistor and the transistor
One fuse, substrate connection the second measurement pad are set between one measurement pad.
2. semiconductor structure as claimed in claim 1, it is characterised in that the transistor is NMOS brilliant
Body pipe.
3. semiconductor structure as claimed in claim 2, it is characterised in that be formed with p-well in the substrate,
The source electrode and drain electrode are formed in the p-well.
4. semiconductor structure as claimed in claim 3, it is characterised in that the source electrode and the drain electrode are equal
Connect the second measurement pad.
5. semiconductor structure as claimed in claim 1, it is characterised in that the number of the transistor is 25
Individual~30, the number of the first measurement pad is 25~30.
6. semiconductor structure as claimed in claim 1, it is characterised in that the resistance of the diode is
5k Ω~10k Ω.
7. semiconductor structure as claimed in claim 1, it is characterised in that the material of the fuse is many
Crystal silicon or metallic aluminium.
8. semiconductor structure as claimed in claim 1, it is characterised in that the rated current of the fuse
It is 10-3Ampere~10-2Ampere.
9. semiconductor structure as claimed in claim 1, it is characterised in that the first measurement pad is aluminium weldering
Pad or copper pad, the second measurement pad is aluminium welding pad or copper pad.
10. semiconductor structure as claimed in claim 1, it is characterised in that the semiconductor structure is located at institute
State in the dicing lane of substrate.
A kind of 11. methods of the breakdown voltage for testing grid oxic horizon, it is characterised in that using such as claim
Semiconductor structure in 1-9 described in any one, specifically includes:
Apply first voltage on the described first measurement pad, apply and described first on the described first measurement pad
The second voltage of voltage reversal, and measure the current value of each transistor;
Increase the size of the first voltage successively, and accordingly measure the current value of each transistor, it is right
The breakdown voltage of the grid oxic horizon of each transistor should be drawn, grid oxic horizon described in statistical analysis
Voltage endurance.
The method of the breakdown voltage of 12. test grid oxic horizons as claimed in claim 11, it is characterised in that
The second measurement pad earth terminal.
The method of the breakdown voltage of 13. test grid oxic horizons as claimed in claim 11, it is characterised in that
After the grid oxic horizon of the transistor punctures, the blown fuse being connected with the transistor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201510960964.5A CN106898562A (en) | 2015-12-18 | 2015-12-18 | The method of the breakdown voltage of semiconductor structure and test grid oxic horizon |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201510960964.5A CN106898562A (en) | 2015-12-18 | 2015-12-18 | The method of the breakdown voltage of semiconductor structure and test grid oxic horizon |
Publications (1)
Publication Number | Publication Date |
---|---|
CN106898562A true CN106898562A (en) | 2017-06-27 |
Family
ID=59191315
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201510960964.5A Pending CN106898562A (en) | 2015-12-18 | 2015-12-18 | The method of the breakdown voltage of semiconductor structure and test grid oxic horizon |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN106898562A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109427601A (en) * | 2017-08-25 | 2019-03-05 | 中芯国际集成电路制造(天津)有限公司 | Dielectric breakdown tests circuit and system |
CN111220887A (en) * | 2018-11-23 | 2020-06-02 | 三星电子株式会社 | Semiconductor device and method of operating the same |
CN111562476A (en) * | 2019-01-28 | 2020-08-21 | 中芯国际集成电路制造(上海)有限公司 | Test structure and test method of semiconductor device |
CN111785656A (en) * | 2020-07-28 | 2020-10-16 | 哈尔滨工业大学 | Method for detecting fixed negative charge trap in oxide layer of electronic device |
CN112002651A (en) * | 2020-06-18 | 2020-11-27 | 上海华力集成电路制造有限公司 | MOM structure and metal interlayer dielectric breakdown testing method |
CN113092977A (en) * | 2021-03-30 | 2021-07-09 | 长江存储科技有限责任公司 | Time-lapse breakdown test structure and method and time-lapse breakdown test sample |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101178423A (en) * | 2006-11-07 | 2008-05-14 | 中芯国际集成电路制造(上海)有限公司 | Integrate circuit testing structure and method of use thereof |
CN101252119A (en) * | 2008-03-25 | 2008-08-27 | 上海宏力半导体制造有限公司 | Characteristic measuring structure of MOS device |
US20090140763A1 (en) * | 2007-12-03 | 2009-06-04 | Yeo-Hwang Kim | Method of measuring on-resistance in backside drain wafer |
CN204144249U (en) * | 2014-10-29 | 2015-02-04 | 中芯国际集成电路制造(北京)有限公司 | GOI_TDDB test circuit structure |
CN204241624U (en) * | 2014-10-21 | 2015-04-01 | 中芯国际集成电路制造(北京)有限公司 | The test structure of voltage breakdown |
-
2015
- 2015-12-18 CN CN201510960964.5A patent/CN106898562A/en active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101178423A (en) * | 2006-11-07 | 2008-05-14 | 中芯国际集成电路制造(上海)有限公司 | Integrate circuit testing structure and method of use thereof |
US20090140763A1 (en) * | 2007-12-03 | 2009-06-04 | Yeo-Hwang Kim | Method of measuring on-resistance in backside drain wafer |
CN101252119A (en) * | 2008-03-25 | 2008-08-27 | 上海宏力半导体制造有限公司 | Characteristic measuring structure of MOS device |
CN204241624U (en) * | 2014-10-21 | 2015-04-01 | 中芯国际集成电路制造(北京)有限公司 | The test structure of voltage breakdown |
CN204144249U (en) * | 2014-10-29 | 2015-02-04 | 中芯国际集成电路制造(北京)有限公司 | GOI_TDDB test circuit structure |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN109427601A (en) * | 2017-08-25 | 2019-03-05 | 中芯国际集成电路制造(天津)有限公司 | Dielectric breakdown tests circuit and system |
CN109427601B (en) * | 2017-08-25 | 2020-09-29 | 中芯国际集成电路制造(天津)有限公司 | Dielectric breakdown test circuit and system |
CN111220887A (en) * | 2018-11-23 | 2020-06-02 | 三星电子株式会社 | Semiconductor device and method of operating the same |
CN111562476A (en) * | 2019-01-28 | 2020-08-21 | 中芯国际集成电路制造(上海)有限公司 | Test structure and test method of semiconductor device |
CN112002651A (en) * | 2020-06-18 | 2020-11-27 | 上海华力集成电路制造有限公司 | MOM structure and metal interlayer dielectric breakdown testing method |
CN111785656A (en) * | 2020-07-28 | 2020-10-16 | 哈尔滨工业大学 | Method for detecting fixed negative charge trap in oxide layer of electronic device |
CN111785656B (en) * | 2020-07-28 | 2023-08-15 | 哈尔滨工业大学 | Method for detecting fixed negative charge trap in oxide layer of electronic device |
CN113092977A (en) * | 2021-03-30 | 2021-07-09 | 长江存储科技有限责任公司 | Time-lapse breakdown test structure and method and time-lapse breakdown test sample |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN106898562A (en) | The method of the breakdown voltage of semiconductor structure and test grid oxic horizon | |
US7825679B2 (en) | Dielectric film and layer testing | |
US20030213953A1 (en) | Integrated circuit chips and wafers including on-chip test element group circuits, and methods of fabricating and testing same | |
CN103033728B (en) | Time dependent dielectric breakdown test circuit and method of testing | |
CN102004218B (en) | Chip acceptability testing method | |
US20140354325A1 (en) | Semiconductor layout structure and testing method thereof | |
CN106653732A (en) | Test line structure and method for performing wafer acceptance test | |
US6894524B1 (en) | Daisy chain gang testing | |
CN100362642C (en) | Detecting structure for simultaneously detecting hot carriers of multiple metal-oxide-semiconductor device | |
US7573687B2 (en) | Power semiconductor device | |
CN103837809B (en) | The IC layout of test MOSFET matching and method of testing | |
JP5529611B2 (en) | Semiconductor device and resistance measuring method | |
CN205900538U (en) | Reliability test structure | |
CN108051722A (en) | The lifetime estimation method and system of hot carrier injection effect | |
WO2023029440A1 (en) | Resistance value acquisition circuit, method and device | |
US6867580B1 (en) | Structures and methods for determining the effects of high stress currents on conducting layers and contacts in integrated circuits | |
US9831139B2 (en) | Test structure and method of manufacturing structure including the same | |
CN107015133A (en) | The test structure and method of metal-oxide-semiconductor conducting resistance | |
CN212540578U (en) | Test structure | |
US9470719B2 (en) | Testing semiconductor devices | |
US6836106B1 (en) | Apparatus and method for testing semiconductors | |
US20090001368A1 (en) | Semiconductor device including semiconductor evaluation element, and evaluation method using semiconductor device | |
US6825671B1 (en) | Integrated electromigration length effect testing method and apparatus | |
Ashton | Modified transmission line pulse system and transistor test structures for the study of ESD | |
Terada et al. | Measurement of the MOSFET drain current variation under high gate voltage |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
RJ01 | Rejection of invention patent application after publication | ||
RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170627 |