CN107422242A - The test device and method of a kind of VDMOS chip - Google Patents

The test device and method of a kind of VDMOS chip Download PDF

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Publication number
CN107422242A
CN107422242A CN201610346382.2A CN201610346382A CN107422242A CN 107422242 A CN107422242 A CN 107422242A CN 201610346382 A CN201610346382 A CN 201610346382A CN 107422242 A CN107422242 A CN 107422242A
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CN
China
Prior art keywords
vdmos
chip
pin card
wafer
test
Prior art date
Application number
CN201610346382.2A
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Chinese (zh)
Inventor
赵圣哲
Original Assignee
北大方正集团有限公司
深圳方正微电子有限公司
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Priority to CN201610346382.2A priority Critical patent/CN107422242A/en
Publication of CN107422242A publication Critical patent/CN107422242A/en

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Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26Testing of individual semiconductor devices
    • G01R31/2601Apparatus or methods therefor
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02General constructional details
    • G01R1/06Measuring leads; Measuring probes
    • G01R1/067Measuring probes
    • G01R1/073Multiple probes
    • G01R1/07307Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card

Abstract

The embodiments of the invention provide a kind of test device of VDMOS chip and method, described device includes:At least two pin cards being arranged side by side;Wherein, connected between at least two pins card by wire, and the spacing between the spacing between two neighboring pin card and two neighboring vertical DMOS field-effect transistor VDMOS chip on the first direction of wafer is equal.The present invention can realize while carry out concurrent testing at least two chips of same row on wafer, then on the premise of any cost is not increased newly, substantially reduces the testing time of small chip, reduce the cost during device production.

Description

The test device and method of a kind of VDMOS chip

Technical field

The present invention relates to the test device and method in small chip testing technology field, more particularly to a kind of VDMOS chip.

Background technology

Vertical double diffused metal-oxide semiconductor field effect transistor (vertical double-diffused MOSFET, VDMOS) it is currently used power transistor, as a kind of voltage-controlled device, in suitable grid voltage control Under system, semiconductor surface transoid, conducting channel is formed.VDMOS has the advantages of bipolar transistor and common MOS device concurrently.Therefore, Whether switch application or linear applications, VDMOS are preferable power devices.With the hair of semiconductor design and technique Exhibition, VDMOS device is less and less, by taking 1 ampere of device as an example, only thousands of individual devices on early stage a piece of 6 cun of wafers, but current The device of individual same performances up to ten thousand can be produced on 6 cun of wafers.The cost of device is greatly reduced.The positive court of current VDMOS device Low cost and high reliability direction to develop.

The cost of VDMOS device mainly includes the cost of raw material, processes (technique) cost, testing cost.With device skill The development of art, more and more with the number of chips on wafer, this is substantially nothing for the cost of raw material and processing cost Influence.Influence maximum is testing cost.For the device of early stage, a piece of 6 cun of wafers (by taking 1,000 chips as an example) are tested, Probably only need more than ten minutes.For current device, a piece of 6 cun of wafers (by taking 10,000 tube cores as an example) are tested, using same Method of testing, testing time then need to put ten times greater, reach more than one hours.This allows for testing cost and is multiplied.

Current measurement direction is:Wafer and chip as shown in Figure 1, tested using single pin card.Specific test When, as shown in figure 1, can be wagged the tail mode (1~14) chip testing one by one backward in sequence from 1# chips using dragon.System can be received Collect the data of each chip and arrange to together.The schematic diagram for showing single pin card as shown in Fig. 2 a, Fig. 2 b, Mei Gedan One pin card includes a grid probe 101 and four source electrode probes 102.During test, pin card is pressed onto on 1# chips by automatic arm, After gathered data, according to the design (spacing) of chip, 2# chips are stepped to, gathered data, are tested one by one backward afterwards.Thus may be used See, this test mode is for the wafer of small chip, such as 10,000 chips of representative value, using current test equipment with And method of testing can greatly increase testing cost.

The content of the invention

The defects of for prior art, the invention provides a kind of test device of VDMOS chip and method, solves existing When having in technology using the test of single pin card, if the VDMOS chip quantity on wafer causes asking for testing cost waste when larger Topic.

In a first aspect, the invention provides a kind of test device of VDMOS chip, described device includes:It is arranged side by side At least two pin cards;

Wherein, connected between at least two pins card by wire, and spacing and wafer between two neighboring pin card First direction between two neighboring vertical double diffused metal-oxide semiconductor field effect transistor VDMOS chip between Away from equal.

Preferably, described device includes:First pin card, the second pin card and the 3rd pin card;

Wherein, the first pin card is connected with the second pin card by wire, the second pin card and the 3rd pin Card is connected by wire, and the first pin card is connected with the 3rd pin card by wire.

Preferably, the step distance of each pin card is arranged to:It is two neighboring on the first direction of step distance=wafer Spacing × pin card quantity between VDMOS chip.

Preferably, the VDMOS chip array arrangement on the wafer, the VDMOS chip form more in a first direction Row, forms multiple rows of in a second direction;The first direction is vertical with second direction;

The quantity of the pin card is less than or equal on the first direction of the wafer quantity for often arranging VDMOS chip.

Preferably, each pin card includes:One grid probe and at least one source electrode probe.

Second aspect, the invention provides a kind of VDMOS cores of the test device based on any one above-mentioned VDMOS chip Chip test method, including:

N number of VDMOS chip is tested simultaneously using the test device of the VDMOS chip including N number of pin card, and gathers the N The data of individual VDMOS chip;N is more than or equal to 2;

Based on default step distance, the test device of the VDMOS chip is controlled to test another N number of VDMOS chip and adopt Collect data, until completing the data acquisition of all VDMOS chips on wafer;

Wherein, N number of pin card is connected by wire between any two, and spacing between two neighboring pin card and wafer Spacing on first direction between two neighboring VDMOS chip is equal.

Preferably, methods described also includes:

Along the first direction of wafer, the test device of the VDMOS chip is controlled line by line described in sequential testing on wafer VDMOS chip.

Preferably, the default step distance is:Two neighboring VDMOS cores on the first direction of step distance=wafer Spacing × pin card quantity between piece.

Preferably, the VDMOS chip array arrangement on the wafer, the VDMOS chip form more in a first direction Row, forms multiple rows of in a second direction;The first direction is vertical with second direction;

The quantity N of the pin card is less than or equal on the first direction of the wafer quantity for often arranging VDMOS chip.

Preferably, each pin card includes:One grid probe and at least one source electrode probe.

As shown from the above technical solution, the present invention provides a kind of test device and method of VDMOS chip, by will at least Two pin cards to together, are connected by wire between any two parallel, and according to often being arranged on wafer between two neighboring VDMOS chip Away from the spacing between two neighboring pin card is set, it so, it is possible to realize and multiple chips of same row on wafer surveyed parallel Examination, the testing time is saved, reduce the small chip testing costs of VDMOS.

Brief description of the drawings

In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing There is the required accompanying drawing used in technology description to be briefly described, it should be apparent that, drawings in the following description are only this Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can be with Other accompanying drawings are obtained according to these figures.

Fig. 1 is multiple VDMOS chip testing sequence schematic diagrames on wafer in the prior art;

Fig. 2 a are the schematic top plan views of existing VDMOS testing needles card;

Fig. 2 b are the schematic side views of existing VDMOS testing needles card;

Fig. 3 is a kind of schematic top plan view of the test device for VDMOS chip that one embodiment of the invention provides;

Fig. 4 is a kind of schematic side view of the test device for VDMOS chip that another embodiment of the present invention provides;

Fig. 5 is a kind of schematic flow sheet of the method for testing for VDMOS chip that one embodiment of the invention provides;

Fig. 6 is the schematic diagram of the method for testing chips testing sequence for the VDMOS chip that another embodiment of the present invention provides;

Description of symbols in Fig. 2 a~Fig. 4:101- grid probes;102- source electrode probes;The probes of 301- first;302- second Probe;The probes of 303- the 3rd.

Embodiment

Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete Site preparation describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.It is based on Embodiment in the present invention, those of ordinary skill in the art are obtained every other under the premise of creative work is not made Embodiment, belong to the scope of protection of the invention.

One embodiment of the invention provides a kind of overlooking the structure diagram of the test device of VDMOS chip, test dress Put including:At least two pin cards being arranged side by side.

Wherein, connected between at least two pins card by wire, and spacing and wafer between two neighboring pin card First direction between two neighboring vertical double diffused metal-oxide semiconductor field effect transistor VDMOS chip between Away from equal.

It will be appreciated that at least two pins card is arranged side by side, and it is parallel with the first direction of wafer.

Specifically, multiple VDMOS chips are included on wafer, on the first direction of multiple VDMOS chips on the wafer Into multiple rows of, into multiple rows of in the second direction of the wafer, wherein, first direction is vertical with second direction.For example, a certain crystalline substance The spacing of two neighboring VDMOS chip of often being gone on circle is 100um, then by least two pin card arrangement in a row in the test device, And the spacing between two neighboring pin card is arranged to 100um.In actual applications, according to often arranging two neighboring VDMOS cores on wafer The spacing of piece sets the spacing between two neighboring pin card.

As can be seen here, the test device of the VDMOS chip in the present embodiment, by by least two pin cards parallel to one Rise, connected between any two by wire, and set according to the spacing that two neighboring VDMOS chip is often arranged on wafer two neighboring Spacing between pin card, it so, it is possible to realize multiple chips progress concurrent testing to same row on wafer, save the testing time, Reduce the small chip testing costs of VDMOS.

For example, the test device of a kind of VDMOS chip as shown in Figure 3, Figure 4, Fig. 3 are VDMOS in the present embodiment The schematic top plan view of the test device of chip, Fig. 4 are the schematic side view of the test device of VDMOS chip in the present embodiment.This The test device of VDMOS chip in embodiment includes:Three pin cards being arranged side by side.Specifically, as shown in Figures 3 and 4, should Test device includes:First pin card 301, the second pin card 302 and the 3rd pin card 303.

Wherein, the first pin card 301 is connected with the second pin card 302 by wire, the second pin card 302 and institute State the 3rd pin card 303 to connect by wire, the first pin card 301 is connected with the 3rd pin card 303 by wire.

In this way, it is only necessary to which a stepping can test the tube core of three VDMOS chips respectively simultaneously, drop significantly The low testing time.

It should be noted that if equipment processing data ability is stronger, more pin cards, such as 10 can be set parallel.

In the present embodiment, the step distance of each pin card is arranged to:Adjacent two on the first direction of step distance=wafer Spacing × pin card quantity between individual VDMOS chip.For example, if test device includes three pin cards being arranged side by side, and wafer First direction on spacing between two neighboring VDMOS chip be 100um, then the step distance of each pin card is arranged to 300um。

Further, the VDMOS chip array arrangement described in the present embodiment on wafer, the VDMOS chip is first Side is upwardly formed multiple rows of, is formed in a second direction multiple rows of;The first direction is vertical with second direction.

Then correspondingly, the quantity of the pin card is less than or equal on the first direction of the wafer number for often arranging VDMOS chip Amount.

Wherein, each pin card includes:One grid probe and at least one source electrode probe.As shown in Fig. 2 each pin Ka Bao Including 1 grid probe and 4 source electrode probes, it will be appreciated that ground, the quantity of specific source electrode probe are set according to by the size of electric current, Electric current is bigger, then the source electrode probe set is more.

The invention provides a kind of test of the VDMOS chip of test device based on any one above-mentioned VDMOS chip by Fig. 5 The schematic flow sheet of method, as shown in figure 5, the method for testing comprises the following steps:

S1:N number of VDMOS chip is tested simultaneously using the test device of the VDMOS chip including N number of pin card, and gathers institute State the data of N number of VDMOS chip.

Wherein, N is the positive integer more than or equal to 2.Specifically, the test device of VDMOS chip includes N number of be arranged side by side Pin card, N number of pin card is connected by wire between any two, and the spacing and the first of wafer between two neighboring pin card Spacing on direction between two neighboring VDMOS chip is equal.Thus, the test device of the VDMOS chip can test N number of simultaneously VDMOS chip, greatly save the testing time.

S2:Based on default step distance, the test device of the VDMOS chip is controlled to test another N number of VDMOS chip simultaneously Gathered data, until completing the data acquisition of all VDMOS chips on wafer.

Specifically, based on default step distance, tested on wafer after the VDMOS chip of a row, it is brilliant to continue test The VDMOS chip of next row on circle, until completing the test to all VDMOS chips on wafer.

As can be seen here, the method for testing of the VDMOS chip in the present embodiment, the VDMOS chip including N number of pin card is passed through Test device tests N number of VDMOS chip simultaneously, then can realize while N number of chip of same row on wafer is surveyed parallel Examination, in this way, on the premise of any cost is not increased newly, the testing time of small chip is substantially reduced, reduces device production mistake Cost in journey.

In an alternate embodiment of the present invention where, also included based on the method for testing described in above-described embodiment, this method:

Along the first direction of wafer, the test device of the VDMOS chip is controlled line by line described in sequential testing on wafer VDMOS chip.

Specifically, as shown in fig. 6, in test, along the first direction (direction i.e. from left to right) of wafer, control The test device of the VDMOS chip VDMOS chip on sequential testing (such as according to 1~14 sequential testing) wafer line by line. For example, when the test device of VDMOS chip includes 3 pin cards being arranged side by side, the test device of VDMOS chip is controlled first 1#~3# pin cards are tested simultaneously, and are tested line by line according to 4#~6#, 7#~9#, 10#~12# ... order successively.

Specifically, the default step distance is:Two neighboring VDMOS cores on the first direction of step distance=wafer Spacing × pin card quantity between piece.For example, if test device includes three pin cards being arranged side by side, and the first direction of wafer Spacing between upper two neighboring VDMOS chip is 100um, then the step distance of each pin card is arranged to 300um.

In the present embodiment, the VDMOS chip array arrangement on the wafer, VDMOS chip shape in a first direction Into multiple rows of, formed in a second direction multiple rows of;The first direction is vertical with second direction.

Correspondingly, the quantity N of the pin card is less than or equal on the first direction of the wafer number for often arranging VDMOS chip Amount.

Wherein, each pin card includes:One grid probe and at least one source electrode probe.

It should be noted that in all parts of the system of the present invention, according to the function that it to be realized to therein Part has carried out logical partitioning, and still, the present invention is not only restricted to this, all parts can be repartitioned as needed or Person combines, for example, can be single part by some component combinations, or can be further broken into some parts more Subassembly.

The all parts embodiment of the present invention can be realized with hardware, or to be run on one or more processor Software module realize, or realized with combinations thereof.It will be understood by those of skill in the art that it can use in practice Microprocessor or digital signal processor (DSP) realize some or all portions in system according to embodiments of the present invention The some or all functions of part.The present invention is also implemented as the part or complete for performing method as described herein The equipment or program of device (for example, computer program and computer program product) in portion.Such program for realizing the present invention It can store on a computer-readable medium, or can have the form of one or more signal.Such signal can be with Download and obtain from internet website, either provide on carrier signal or provided in the form of any other.

It should be noted that the present invention will be described rather than limits the invention for above-described embodiment, and ability Field technique personnel can design alternative embodiment without departing from the scope of the appended claims.In the claims, Any reference symbol between bracket should not be configured to limitations on claims.Word "comprising" does not exclude the presence of not Element or step listed in the claims.Word "a" or "an" before element does not exclude the presence of multiple such Element.The present invention can be by means of including the hardware of some different elements and being come by means of properly programmed computer real It is existing.In if the unit claim of equipment for drying is listed, several in these devices can be by same hardware branch To embody.The use of word first, second, and third does not indicate that any order.These words can be explained and run after fame Claim.

Embodiment of above is only of the invention suitable for explanation, and not limitation of the present invention, about the common of technical field Technical staff, without departing from the spirit and scope of the present invention, it can also make a variety of changes and modification, thus it is all Equivalent technical scheme falls within scope of the invention, and scope of patent protection of the invention should be defined by the claims.

Claims (10)

1. a kind of test device of VDMOS chip, it is characterised in that described device includes:At least two pin cards being arranged side by side;
Wherein, connected between at least two pins card by wire, and the spacing and the of wafer between two neighboring pin card Spacing phase on one direction between two neighboring vertical double diffused metal-oxide semiconductor field effect transistor VDMOS chip Deng.
2. device according to claim 1, it is characterised in that described device includes:First pin card, the second pin card and the 3rd Pin card;
Wherein, the first pin card is connected with the second pin card by wire, the second pin card and the 3rd pin cartoon Wire connection is crossed, the first pin card is connected with the 3rd pin card by wire.
3. device according to claim 1, it is characterised in that the step distance of each pin card is arranged to:Step distance= Spacing × pin card quantity on the first direction of wafer between two neighboring VDMOS chip.
4. device according to claim 1, it is characterised in that the VDMOS chip array arrangement on the wafer, it is described VDMOS chip forms multiple rows of in a first direction, is formed in a second direction multiple rows of;The first direction hangs down with second direction Directly;
The quantity of the pin card is less than or equal on the first direction of the wafer quantity for often arranging VDMOS chip.
5. device according to claim 1, it is characterised in that each pin card includes:One grid probe and at least one Source electrode probe.
A kind of 6. VDMOS chip test side of the test device based on VDMOS chip according to any one of claims 1 to 5 Method, it is characterised in that including:
N number of VDMOS chip is tested simultaneously using the test device of the VDMOS chip including N number of pin card, and gathered described N number of The data of VDMOS chip;N is more than or equal to 2;
Based on default step distance, the test device of the VDMOS chip is controlled to test another N number of VDMOS chip and gather number According to until completing the data acquisition of all VDMOS chips on wafer;
Wherein, N number of pin card is connected by wire between any two, and the spacing and the first of wafer between two neighboring pin card Spacing on direction between two neighboring VDMOS chip is equal.
7. according to the method for claim 6, it is characterised in that methods described also includes:
Along the first direction of wafer, the test device of the VDMOS chip VDMOS described in sequential testing on wafer line by line is controlled Chip.
8. according to the method for claim 6, it is characterised in that the default step distance is:Step distance=wafer First direction on spacing × pin card quantity between two neighboring VDMOS chip.
9. according to the method for claim 6, it is characterised in that the VDMOS chip array arrangement on the wafer, it is described VDMOS chip forms multiple rows of in a first direction, is formed in a second direction multiple rows of;The first direction hangs down with second direction Directly;
The quantity N of the pin card is less than or equal on the first direction of the wafer quantity for often arranging VDMOS chip.
10. according to the method for claim 6, it is characterised in that each pin card includes:One grid probe and at least one Source electrode probe.
CN201610346382.2A 2016-05-23 2016-05-23 The test device and method of a kind of VDMOS chip CN107422242A (en)

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