JP2020150116A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

To provide a semiconductor device with high electrical reliability.SOLUTION: A manufacturing method of a semiconductor device according to an embodiment includes a step of sealing a semiconductor chip 10, a first lead SL1, and a second lead SL2 with a sealing body MR such that a part of a first lead SL1 and a second lead SL2 is exposed, and a step of connecting a measurement terminal to a part of the first lead SL1 and the second lead SL2 exposed from the sealing body MR after the sealing step, and measuring a resistance value of a conductive path 100 composed of the first lead SL 1, a source bonding wire SW connected to the first lead SL1, a first electrode 12, a source bonding wire SW connected to the second lead SL2, and the second lead SL2.SELECTED DRAWING: Figure 1

Description

The present invention relates to a semiconductor device and a technique for manufacturing the same, and relates to, for example, a technique applicable to a method for manufacturing a semiconductor device including a step of inspecting the electrical characteristics of the semiconductor device.

Japanese Patent Application Laid-Open No. 09-266226 (Patent Document 1) describes a technique for dividing a source electrode into a plurality of regions in order to detect a defect due to a disconnection of a bonding wire commonly connected to the source electrode.

Japanese Unexamined Patent Publication No. 09-266226

When the bonding wire is sealed by the sealing body, it becomes difficult to visually confirm that the bonding wire is broken or poorly contacted due to the resin stress at the time of forming the sealing body. For example, as described in Patent Document 1, in the method of confirming the disconnection or poor contact of the bonding wire by the method of measuring the on-resistance, the chip resistance is one digit or more larger than the resistance of the bonding wire, and therefore bonding. Since the change in resistance value due to wire breakage or poor contact is absorbed within the range of variation in chip resistance, there is a concern that it may be difficult to determine the bond wire breakage or poor contact.

Other challenges and novel features will become apparent from the description and accompanying drawings herein.

The method for manufacturing a semiconductor device in one embodiment includes a step of preparing a lead frame including a chip mounting portion and first leads and second leads arranged around the chip mounting portion, and a semiconductor having a first electrode. A step of arranging the chip on the chip mounting portion, a step of electrically connecting the first electrode of the semiconductor chip and the first lead and the second lead by individual bonding wires, and a step of electrically connecting the first lead and the second lead, respectively. It has a step of sealing the semiconductor chip and the first lead and the second lead with a sealing body so that a part of them is exposed. In the method of manufacturing a semiconductor device, after the sealing step, the measurement terminals are further connected to a part of the first lead and the second lead exposed from the sealing body, and the bonding is connected to the first lead and the first lead. It includes a step of measuring the resistance value of a conductive path composed of a wire, a first electrode, a bonding wire connected to a second lead, and a second lead.

Further, the semiconductor device according to the embodiment includes a semiconductor chip, a plurality of leads arranged around the semiconductor chip, a plurality of bonding wires for electrically connecting the plurality of leads and the semiconductor chip, and a sealing body. And have. The sealant seals the semiconductor chip, each part of the plurality of leads, and the plurality of bonding wires. The plurality of leads include a first lead and a second lead. The first lead has a first portion and a second portion that are separated from each other outside the encapsulant, and a third portion that integrally connects the first portion and the second portion inside the encapsulant. The first lead and the second lead are individual bonding wires among the plurality of bonding wires, and are electrically connected to the semiconductor chip.

Further, the semiconductor device according to the embodiment includes a semiconductor chip having a first electrode, a plurality of leads arranged around the semiconductor chip and arranged at predetermined intervals, and a plurality of first electrodes of the semiconductor chip. It has a plurality of bonding wires for electrically connecting the leads of the above and a sealant. The sealant seals the semiconductor chip, each part of the plurality of leads, and the plurality of bonding wires.

The semiconductor device further has a high resistance connection that is located between the leads and connects each of the leads inside the enclosure. In plan view, the high resistance connection has a narrow width as compared to the width of each of the plurality of leads projecting to the outside of the encapsulant.

According to the method for manufacturing a semiconductor device according to one embodiment, it is possible to carry out an electrical reliability inspection for each bonding wire in the electrical property test of the semiconductor device even after the resin sealing step. .. Further, it is possible to provide a semiconductor device having high electrical reliability.

FIG. 1 is a diagram showing an example of a configuration of a semiconductor device according to an embodiment. FIG. 2 is a cross-sectional view taken along the line AA of FIG. FIG. 3 is a flowchart showing an example of a manufacturing process showing a manufacturing method of the semiconductor device according to the embodiment. FIG. 4 is a diagram showing an example of the configuration of another semiconductor device according to the embodiment. FIG. 5 is a diagram showing an example of the configuration of another semiconductor device according to the embodiment. FIG. 6 shows a tester for testing a semiconductor device according to an embodiment. FIG. 7 is a diagram showing a connection between the semiconductor device and the measuring device according to the embodiment. FIG. 8 is a diagram showing a connection between the semiconductor device and the measuring device according to the embodiment.

In the following embodiments, when necessary for convenience, the description will be divided into a plurality of sections or embodiments, but unless otherwise specified, they are not unrelated to each other, and one of them is not related to each other. It is related to some or all of the other modifications, details, supplementary explanations, and the like. In addition, in the following embodiments, when the number of elements (including the number, numerical value, quantity, range, etc.) is referred to, when it is specified in particular, or when it is clearly limited to a specific number in principle, etc. Except, the number is not limited to the specific number, and may be more than or less than the specific number. Further, in the following embodiments, the components (including element steps and the like) are not necessarily essential unless otherwise specified and clearly considered to be essential in principle. Similarly, in the following embodiments, when the shape, positional relationship, etc. of a component or the like is referred to, it is substantially the same unless otherwise specified or when it is considered that it is not clearly the case in principle. It shall include those that are similar to or similar to the shape, etc. This also applies to the above numerical values and ranges.

Hereinafter, embodiments will be described in detail with reference to the drawings. In addition, in all the drawings for explaining the embodiment, the members having the same function are designated by the same reference numerals in principle, and the repeated description thereof will be omitted. Further, the repeated description of the same process will be omitted. In addition, in order to make the drawing easy to understand, hatching may be added even if it is a plan view.

(Embodiment 1)
The configuration of the semiconductor device according to the first embodiment will be described below.

FIG. 1 is a diagram showing an example of a configuration of a semiconductor device according to the present embodiment. The inside of the sealed body MR of the semiconductor device PKG is shown through. The semiconductor device PKG in the present embodiment has a rectangular sealed body MR sealed with a sealed body made of resin. Inside the encapsulant MR, a semiconductor chip 10, a chip mounting portion 16 which is a mounting portion of the semiconductor chip 10, a plurality of source leads (also referred to as external terminals) SLs arranged around the chip mounting portion 16, and a gate. A lead GL, a plurality of source lead SLs, a plurality of source bonding wire (also referred to as a source wire) SW for electrically connecting the gate lead GL and the semiconductor chip 10 and a gate bonding wire (also referred to as a gate wire) GW are shown. The chip mounting portion 16 is also referred to as a die frame or a die pad.

The semiconductor device PKG includes a semiconductor chip 10 on which a power MOSFET (also referred to as a power transistor) is formed. In the semiconductor chip 10, the first electrode 12 and the second electrode 14 different from the first electrode 12 are formed on the first main surface, and the third electrode 17 is formed on the second main surface opposite to the first main surface. Is formed by the vertical structure in which is formed. The power MOSFET has a configuration in which a plurality of unit transistors (also referred to as unit cells) are connected in parallel, and has a configuration capable of handling, for example, 1 W or more of electric power.

The plurality of source lead SLs and gate lead GLs are each electrically connected to the semiconductor chip 10 via the plurality of source bonding wire SWs and gate bonding wire GWs. The first electrode 12 indicates a source electrode that is electrically connected to the source formed on the semiconductor chip 10. The second electrode 14 indicates a gate electrode that is electrically connected to the gate formed on the semiconductor chip 10. The third electrode 17 (see FIG. 2) shows a drain electrode electrically connected to the drain formed on the semiconductor chip 10. The outer size of the second electrode 14 is smaller than that of the first electrode 12.

The semiconductor chip 10 is arranged on the chip mounting portion 16. A plurality of source lead SLs and gate lead GLs are arranged on the first long side of the sealing body MR. The lead frame has a structure extending inside and outside the sealing body MR, and includes a chip mounting portion 16, a plurality of source lead SLs, and a gate lead GL. A plurality of source lead SLs and gate lead GLs are arranged around the chip mounting portion 16. A part of the plurality of source lead SLs and gate lead GLs is exposed to the outside of the sealing body MR.

The lead frame is made of a metal, for example, a metal containing copper as a main component. Here, the main component means a material component containing the largest amount of the constituent materials constituting the member. For example, the material containing copper as the main component is the material of the member having the largest amount of copper. It means that it is included. Therefore, although the member is basically composed of copper, it does not exclude the case where impurities are contained in other parts.

The plurality of source lead SLs and gate lead GLs include a plurality of source lead SLs electrically connected to the first electrode 12 and a gate lead GL electrically connected to the second electrode 14. The plurality of source lead SLs are arranged at predetermined intervals and are formed separately from each other. Further, the plurality of source lead SLs include a first lead SL1 and a second lead SL2. Further, each of the plurality of source lead SLs has the same shape.

The plurality of source bonding wire SWs and gate bonding wire GWs include a plurality of source bonding wire SWs connected to the first electrode 12 and a gate bonding wire GW connected to the second electrode 14. Each of the plurality of source lead SLs is electrically connected to the first electrode 12 via individual source bonding wire SWs. Further, the gate lead GL is electrically connected to the second electrode 14 via the gate bonding wire GW. Further, the plurality of source lead SLs and gate lead GLs are arranged so that a part of them is exposed from the sealing body MR. That is, a part of the plurality of source lead SLs and gate lead GLs protrudes to the outside of the sealing body.

The conductive path 100 is a conductive path when the measurement terminal of the tester (also referred to as a test device) is connected to a part of the first lead SL1 and the second lead SL2 to measure the resistance value in the step of measuring the resistance value. Is shown. The conductive path 100 includes a first lead SL1, a source bonding wire SW connected to the first lead SL1, a first electrode 12 on the semiconductor chip 10, a source bonding wire SW connected to the second lead SL2, and a second lead. It is composed of SL2. Further, the number of the plurality of source read SLs is not limited to the number shown in the figure. The number of the plurality of source read SLs may be more or less than shown in the figure as long as it is 2 or more.

Subsequently, the internal structure of the semiconductor device PKG in the present embodiment will be described. FIG. 2 is a cross-sectional view taken along the line AA of FIG. As shown in FIG. 2, the semiconductor chip 10 is mounted on the chip mounting portion 16 which is a part of the lead frame via an adhesive ADH (also referred to as a bond material) such as solder or silver paste. The third electrode 17 is formed on the lower surface of the semiconductor chip 10, that is, the entire second main surface of the semiconductor chip 10. The semiconductor chip 10 and the chip mounting portion 16 are covered with the sealing body MR. At this time, the lower surface of the chip mounting portion 16 is partially exposed from the sealing body MR. The lower surface of the exposed chip mounting portion 16 is a drain terminal DL, and is configured to be connectable to an external device on the mounting board.

Hereinafter, the method for manufacturing the semiconductor device according to the first embodiment will be described with a flowchart of a manufacturing process showing the method for manufacturing the semiconductor device shown in FIG.

In the lead frame preparation step S301, a lead frame including the chip mounting portion 16, a plurality of source lead SLs, and a gate lead GL shown in FIG. 1 is prepared.

In the die bonding step S302, the semiconductor chip 10 shown in FIG. 2 is mounted on the chip mounting portion 16 via the adhesive ADH. The semiconductor chip 10 has a first main surface on which the first electrode 12 and the second electrode 14 are formed, and a second main surface located on the opposite side thereof, and the second main surface is the chip mounting portion 16. Is glued to.

In the wire bonding step S303, the first electrode 12 of the semiconductor chip 10 shown in FIG. 1 is electrically connected to the plurality of source lead SLs via the plurality of source bonding wires SW. Further, the second electrode 14 of the semiconductor chip 10 is electrically connected to the gate lead GL via the gate bonding wire GW.

In the resin sealing step (also referred to as molding step) S304, each part (also referred to as an inner lead portion) of the semiconductor chip 10, the plurality of source bonding wire SWs, the gate bonding wire GW, and the lead frame is sealed with resin. A sealed body MR (also referred to as a resin body) is formed. A part of the plurality of source leads SL and gate lead GL (also referred to as an outer lead portion) is exposed from the sealing body MR. Further, the semiconductor device PKG is made into individual pieces by cutting each of the source lead SL and the gate lead GL exposed to the outside of the sealing body MR.

The resistance value measuring step S305, which is one of the inspection steps (also called a test step), measures a measuring device (also called a tester) on a part of a plurality of source leads SL exposed from the sealing body MR of the semiconductor device PKG. The terminals are connected to measure the electric resistance value of the semiconductor device PKG. The measuring device has two or more measuring terminals, and the terminals are connected to the semiconductor device PKG to be measured. A predetermined current is applied to the semiconductor device PKG from one measurement terminal of the measuring device, and the current passing through the semiconductor device PKG is output from the other measuring terminal. By measuring the voltage value, which is the potential difference between the source lead SLs to which the measurement terminals are connected, the resistance value between the source lead SLs is measured.

The resistance value between the source lead SLs includes the resistance values of the plurality of source lead SLs and the plurality of source bonding wires SW, for example, as shown in the conductive path 100 of FIG. The resistance value of the conductive path 100 changes depending on the state of the source bonding wire SW. That is, when the source bonding wire SW is in a defective state, the resistance value of the conductive path 100 changes.

When the source bonding wire SW is in a defective state, for example, an open defect, a crimping defect in which the source bonding wire SW is not properly connected to the source lead SL or the semiconductor chip 10, and a portion where the source bonding wire SW does not break. This includes a state in which the source bonding wire SW is electrically broken and the source bonding wire SW is electrically broken. At this time, the resistance value of the conductive path 100 is larger than the resistance value of the source bonding wire SW in the normal state.

Further, in order to detect the defective state of each source bonding wire SW by the magnitude of the resistance value, the source lead SL connecting the measurement terminals must be the source lead SL connected to the same electrode by individual source bonding wire SWs. Is desirable. For example, a part of the first lead SL1 and the second lead SL2 electrically connected to the first electrode 12 by individual source bonding wire SW is connected to the measurement terminal of the measuring device, and the resistance value of the conductive path 100 is increased. Be measured.

At this time, the resistance value measuring step S305 is executed for all the source lead SLs. That is, the measurement is performed sequentially for any two source read SLs. Further, the conductive path in that case is the source lead SL to which one measurement terminal is connected, the source bonding wire SW connected to the source lead SL to which one measurement terminal is connected, and the first electrode, similarly to the conductive path 100. 12. It is composed of a source bonding wire SW connected to a source lead SL connected to the other measurement terminal, and a source lead SL connected to the other measurement terminal.

Further, the arrangement of the source lead SLs of the semiconductor device PKG to be measured is not limited to the source lead SLs arranged adjacent to each other, and another source lead SL is arranged between the source lead SLs to which the measurement terminals are connected. It may have been. However, as the distance between the source lead SLs to which the measurement terminals are connected becomes longer, the distance between the source bonding wire SWs connected to the source lead SLs on the semiconductor chip 10 also becomes longer. Considering that the resistance value on the first electrode 12 of the semiconductor chip 10 becomes large as a result, the source lead SL connected to the measurement terminal for measuring the fluctuation of the resistance value of the source bonding wire SW is closer. It is desirable to be between the source lead SLs located at the positions. Further, the number of source lead SLs to which the current is applied is not limited to one, and may be plural.

The source bonding wire SW connected to the first electrode 12 has a resistance value of, for example, 1 mΩ. Further, the source lead SL connected to the first electrode 12 has, for example, a resistance value of 0.1 mΩ. The resistance value between the source bonding wires SW arranged adjacent to each other on the first electrode 12 is, for example, 0.5 mΩ.

Here, as an example, a case of measuring the resistance value of the conductive path 100 will be described. In the resistance value measuring step S305, a current of, for example, 50 A is applied to the first lead SL1 via the measuring terminal. At this time, when the potential difference PD generated between the first lead SL1 and the second lead SL2 arranged adjacent to the first lead SL1 is measured, the voltage value is about 0.135 V in the normal state. That is, the resistance values of the two source bonding wire SWs, the source bonding wire SW connected to the first lead SL1 to which the current is applied and the source bonding wire SW connected to the other second lead SL2, are measured to be about 2.7 mΩ. Will be done. If the manufacturing variation and the error of the measured value that occur even in the normal state are about 10%, it can be determined to be normal if the resistance value is within the range of 10% including the error.

When the source bonding wire SW is in a defective state such as a broken wire, the resistance value is out of the predetermined value range, that is, it becomes larger than the resistance value range of the conductive path in the normal state, so that state is easily maintained. It becomes possible to detect. This makes it possible to accurately determine the presence or absence of a defective state such as a break in the source bonding wire SW of the semiconductor device PKG. When a defective state is detected, the resistance value measuring step S305 after that may be omitted, and the process may proceed to the next non-defective product determination / shipping step S306. This makes it possible to shorten the time of the inspection process. Further, although only the resistance value measuring step S305 is shown as one of the inspection steps, various visual inspection steps, various electrical characteristic inspection steps, and the like may be included in addition to the resistance value measuring step S305.

Further, in the resistance value measuring step S305, a predetermined potential, for example, 0 V is supplied to the drain terminal DL connected to the third electrode 17 (see FIG. 2) and the gate lead GL connected to the second electrode 14. .. Further, the source lead SLs other than the first lead SL1 and the second lead SL2 whose resistance value is to be measured are not connected to the measuring device because they affect the measured values.

When the second electrode 14 is configured to be connected to a plurality of gate bonding wires GW with respect to the plurality of gate lead GLs, it is possible to carry out the resistance value measuring step S305 similar to the present embodiment. Become. As a result, not only the source bonding wire SW connected to the first electrode 12 but also the gate bonding wire GW connected to the second electrode 14 can be detected in a defective state such as disconnection.

In the non-defective product determination / shipping process S306, it is determined whether the product is a non-defective product that can be shipped or a defective product in which an abnormality such as disconnection has occurred, based on the resistance value measured in the resistance value measuring step S305. If the resistance value is within the predetermined range, it is determined to be a non-defective product, and if it is outside the predetermined range, for example, if the resistance value is large, it is determined to be a defective product.

In addition, the non-defective product discrimination / shipping process S306 conforms to a predetermined evaluation standard based on the results of performing an electrical characteristic inspection of the semiconductor device, that is, various electrical characteristic inspections including the resistance value measurement step S305. Good products to be selected (also called discrimination or judgment) are selected. Good semiconductor devices are shipped and mounted on a mounting board. For example, a semiconductor device in which a resistance value larger than a normal value is detected in the resistance value measuring step S305 is selected as a defective product, that is, a non-conforming product for shipment in the non-defective product determination / shipping process S306, and shipped. Is forgotten.

In the present embodiment, a plurality of source lead SLs are connected to the first electrode 12 by individual source bonding wire SWs. At that time, by measuring the resistance value of the conductive path via the source lead SL, it is possible to detect a defective state such as a disconnection of the source bonding wire SW, and it is possible to improve the reliability of the semiconductor device.

Further, in the present embodiment, as compared with the configuration in which a plurality of source bonding wire SWs are connected to a common source lead SL, the source lead SLs are formed separately from each other and are formed by individual source bonding wire SWs. It will be connected. As a result, the change in resistance value in a defective state such as disconnection of the source bonding wire SW can be measured as a larger value. That is, it can be measured as a value larger than the change (for example, 10%) caused by the manufacturing variation and the error of the measured value. As a result, it becomes possible to detect the defective state more efficiently. Further, since the source lead SL only needs to be separated, it is possible to avoid the addition of unnecessary configurations at the design / manufacturing stage, and the semiconductor device and the test configuration suppress the increase in cost in terms of cost and mounting. Can be realized.

(Embodiment 2)
FIG. 4 is a diagram showing an example of the configuration of the semiconductor device according to the second embodiment. In the following description, the differences from the first embodiment will be mainly described.

In the present embodiment, the plurality of source lead SLs of the semiconductor device PKG2 have a first lead SL1. Here, the first lead SL1 intersects the first direction SL1a extending in the first direction and the second portion SL1b extending in the first direction and located next to the first portion. It consists of a third portion SL1c that extends in the second direction and is located between the first portion SL1a and the second portion SL1b. Further, the first portion SL1a and the second portion SL1b of the first lead indicate a portion protruding from the sealing body MR, that is, an outer lead portion. Further, the first portion SL1a and the second portion SL1b of the first lead are separated from each other outside the sealing body MR. Further, the third portion SL1c of the first lead indicates an inner portion of the sealing body MR, that is, an inner lead portion. The third portion SL1c integrally connects the first portion SL1a and the second portion SL1b inside the sealing body. Further, the first lead SL1 and the second lead SL2 are separated inside the sealing body MR. The first lead SL1 (first part SL1a, second part SL1b, third part SL1c) of the present embodiment is also a part corresponding to the first lead SL1 in the first embodiment.

Here, the first portion SL1a, the second portion SL1b, and the third portion SL1c of the first lead are integrally formed by one lead frame as shown in FIG. The first portion SL1a and the second portion SL1b of the first lead have a shape in which the inner lead portion is integrated by the third portion SL1c, and the outer lead portion is a branched source lead. The third portion of the first lead is formed on the first main surface of the semiconductor chip 10 by, for example, two source bonding wires SW so as to correspond to the first portion SL1a and the second portion SL1b of the first lead. It is electrically connected to the first electrode 12.

The first lead SL1 is arranged next to the second lead SL2. Further, a second portion SL1b of the first lead is arranged between the first portion SL1a of the first lead and the second lead SL2. That is, the second lead SL2 is located next to the first portion SL1a of the first lead via the second portion SL1b of the first lead. Further, the first lead SL1 and the second lead SL2 are the first electrode 12 formed on the first main surface of the semiconductor chip 10 via individual source bonding wire SWs among the plurality of source bonding wire SWs. Connected to.

In the present embodiment, the first lead SL1 (first portion SL1a, second portion SL1b, third portion SL1c) having an integrated inner lead portion and two similar shapes are arranged. The arrangement of the source lead SL is not limited to the arrangement shown in FIG. 4, and the source lead having the same shape as the first lead SL1 (first portion SL1a, second portion SL1b, third portion SL1c) in which the inner lead portion is integrated is formed. 3 or more may be arranged. Further, next to the first lead SL1 (first portion SL1a, second portion SL1b, third portion SL1c) in which the inner lead portion is integrated, a non-branched source lead, that is, the first described with reference to FIG. Two or more source leads having the same shape as the two-lead SL2 may be arranged. Further, only one first lead SL1 (first portion SL1a, second portion SL1b, third portion SL1c) in which the inner lead portion is integrated may be arranged. In these cases, from the viewpoint of detection accuracy, the connection between the inner lead portion and the first electrode 12 is configured such that the number of source bonding wire SWs equal to or less than the number of source lead SLs in the outer lead portion is connected. desirable.

Hereinafter, the method for manufacturing the semiconductor device according to the second embodiment will be described with reference to a flowchart of a manufacturing process showing the method for manufacturing the semiconductor device shown in FIG. In the following description, the differences from the first embodiment will be mainly described.

In the lead frame preparation step S301, a lead frame including the first lead SL1 (first portion SL1a, second portion SL1b, third portion SL1c) having an integrated inner lead portion is prepared. Further, another source lead SL has a shape without branching as in the first embodiment.

In the wire bonding step S303, the source bonding wire SW is connected to the third portion SL1c of the first lead so as to correspond to the first portion SL1a and the second portion SL1b of the first lead shown in FIG. At this time, the source bonding wire SWs are arranged at equal intervals as much as possible so that the source bonding wire SWs arranged in close proximity do not come into contact with another source bonding wire SW to cause a defective state at the time of resin sealing. It is desirable to connect to the source lead SL. For example, the source bonding wire SW may be connected at the same interval as the center line in the width direction of the first portion of the first lead, SL1a, and the outer lead portion of the second portion SL1b. However, the connection interval of the source bonding wire SW is not limited to this, and any arrangement may be made as long as it is on the third portion SL1c of the first lead as long as it does not come into contact with other source bonding wire SW.

In the resistance value measuring step S305, for example, the first portion SL1a and the second portion SL1b of the first lead and each of the second lead SL2 are connected to the measurement terminal of the measuring device as targets for resistance value measurement. A current is applied to the first portion SL1a and the second portion SL1b of the first lead via the measurement terminal. The current is flowing in the semiconductor device via the conductive path 101.

At this time, the conductive path 101 is connected to the first portion SL1a and the second portion SL1b of the first lead, the source bonding wire SW connected to the first portion SL1a of the first lead, and the second portion SL1b of the first lead. The source bonding wire SW, the first electrode 12, the source bonding wire SW connected to the second lead SL2, and the second lead SL2 are included. The resistance on these paths is measured as the resistance value in the conductive path 101.

Further, in the following equations, a reference numeral is added to the resistance R to indicate the respective resistance values. The resistance value of the source bonding wire SW is shown in combination with the code of the connected source lead SL. Here, regarding the description of the resistance value of the first lead SL1, it is assumed that the first lead SL1 is divided into two in order to avoid complication of the description. That is, when measuring the first portion SL1a and the second portion SL1b, the resistance is measured including the third portion. The resistance value on the first portion SL1a side, which is one of the first lead SL1, is indicated by Rsl1a, and the resistance value on the second portion SL1b side, which is the other side of the first lead SL1, is indicated by Rsl1b. Similarly, for the source bonding wire SW connected to the source lead SL, the resistance value of the source bonding wire SW connected to the first portion SL1a side of the first lead SL1 is shown as Rsw-sl1a. Further, the resistance value of the source bonding wire SW connected to the second portion SL1b side, which is the other side of the first lead SL1, is shown as Rsw-sl1b.

For example, the resistance value of each source lead SL is 0.1 mΩ (Rsl1a, Rsl1b, Rsl2). The resistance value of each source bonding wire SW is 1 mΩ (Rsw-sl1a, Rsw-sl1b, Rsw-sl2). Between adjacent source bonding wires SW on the first electrode 12, for example, source bonding wire SW connected to the first portion SL1a side of the first lead and source bonding connected to the second portion SL1b side of the first lead. When the resistance value between the wire SW and the wire SW is 0.5 mΩ (R12), it is shown as follows.

Rtotal = (Rsl1a // Rsl1b) + ((Rsw-sl1a + R12) // Rsw-sl1b) + R12 + Rsw-sl2 + Rsl2 ... (A1)
The total resistance value Rtotal in the conductive path 101 under normal conditions obtained from the above equation is 2.25 mΩ.

At this time, when the manufacturing variation and the error of the measured value (for example, about 10% in total) are taken into consideration, the resistance value is a value including an error of 0.225 mΩ with respect to the normal resistance value, for example, 2.475 mΩ or more. It is possible to determine that some kind of defect has occurred on the conductive path 101. For example, when the source bonding wire SW connected to the first portion SL1a side of the first lead is broken,
Ropen (sw-sl1a) = (Rsl1a // Rsl1b) + Rsw-sl1b + R12 + Rsw-sl2 + Rsl2 ... (A2)
The resistance value Ropen (sw-sl1a) is 2.65 mΩ.

Further, when the source bonding wire SW connected to the second portion SL1b side of the first lead is broken,
Ropen (sw-sl1b) = (Rsl1a // Rsl1b) + (Rsw-sl1a + R12) + R12 + Rsw-sl2 + Rsl2 ... (A3)
The resistance value Ropen (sw-sl1b) is 3.15 mΩ. Therefore, in each case, the resistance value is larger than the resistance value of 2.475 mΩ in the normal state including the manufacturing variation and the error of the measured value. This makes it possible to easily determine that a defect has occurred in the conductive path 101.

Similar to the first embodiment, in the resistance value measuring step S305, the resistance values of all the source lead SLs are measured. At this time, the first lead SL1 (first portion SL1a, second portion SL1b, third portion SL1c) in which the inner lead portion is integrated is not measured individually, but is the first in which the inner lead portion is integrated. The measurement is performed by combining the lead SL1 (first portion SL1a, second portion SL1b, third portion SL1c) with another source lead SL. Further, if a resistance value different from the normal state is measured even once, the resistance value measurement step S305 is completed even before the measurement for all the source lead SLs is completed, and the resistance value measurement step S305 is promptly completed. You may move to the non-defective product determination / shipping process S306 and execute the step of determining a defective product.

Further, as in the first embodiment, the gate lead GL connected to the second electrode 14 and the drain terminal DL connected to the third electrode 17 to which the current is not applied may supply a predetermined potential, for example, 0 V. .. Further, the source lead SL, which is not the measurement target, is not connected to the measuring device because it affects the applied current.

As described above, the semiconductor device has a plurality of source lead SLs and connected to the first lead SL1 (first portion SL1a, second portion SL1b, third portion SL1c) in which the inner lead portion is integrated. It is possible to measure a plurality of source bonding wire SWs at once, and it is possible to shorten the time of the resistance value measuring step S305.

In the case of the second embodiment, a plurality of source bonding wires SW connected to the first lead SL1 (first portion SL1a, second portion SL1b, third portion SL1c) in which the inner lead portion is integrated are connected to the first electrode 12. Since they are connected, the resistance change when one source bonding wire SW becomes defective is smaller than that in the first embodiment. However, in the present embodiment, it is possible to determine whether a plurality of source bonding wires SW are in a normal state or a defective state by measuring the resistance value once. This makes it possible to shorten the time of the resistance value measuring step S305. Actually, the number of source bonding wires connected to the source lead SL is determined so as to shorten the measurement process time in consideration of the detection sensitivity, that is, the amount of resistance change of one source bonding wire SW. Is desirable.

(Embodiment 3)
FIG. 5 is a diagram showing an example of the configuration of the semiconductor device according to the third embodiment. It should be noted that the points different from the configurations of the semiconductor devices according to the first and second embodiments will be mainly described, and the duplicated description will not be repeated.

In the semiconductor device PKG3 according to the third embodiment, the plurality of source lead SLs are source lead SL4s having high resistance connection portions 30 (30a to 30d). The plurality of source leads SL4 are arranged around the semiconductor chip 10 and are arranged at predetermined intervals. Further, a high resistance connection portion 30 is located between the plurality of source leads SL4. Each of the plurality of source leads SL4 has a high resistance connecting portion 30 for connecting each of the source leads SL4 inside the sealing body MR. That is, the plurality of source leads SL4 are connected to each other via the high resistance connection portion 30. The source lead SL4 having the high resistance connection portion 30 is individually connected to the semiconductor chip 10 by a plurality of source bonding wire SWs. Further, the plurality of source leads SL4 and the high resistance connection portion 30 are integrally formed by one lead frame as shown in FIG.

Further, in a plan view, the high resistance connection portion 30 has a narrow width as compared with the width of each of the plurality of source leads SL4 protruding to the outside of the sealing body MR. In the source lead SL4 formed of the same material, the resistance value of the high resistance connection portion 30 is compared with the resistance value of the source lead SL4 protruding to the outside of the sealing body MR by forming the source lead SL4 with a partially narrow width. Can be increased.

Each of the source leads SL4 having the high resistance connection portion 30 is shown as SL4a, SL4b, SL4c, SL4d, SL4e. Further, the plurality of high resistance connection portions 30 are shown as 30a, 30b, 30c, and 30d, respectively.

The manufacturing method of the semiconductor device PKG3 of the third embodiment will be described with reference to the flowchart of the manufacturing process showing the manufacturing method of the semiconductor device of FIG. In the following description, the differences from the first embodiment and the second embodiment will be mainly described.

In the lead frame preparation step S301, the high resistance connection portion 30 is formed by leaving a part of the lead frame terminals without completely cutting the lead frame terminals during press molding of the lead frame.

In the wire bonding step S303, the source bonding wire SW is connected to the source lead SL4 having the high resistance connecting portion 30 respectively. At this time, each source bonding wire SW may be connected to the vicinity of the center line in the width direction of the inner lead portion of the source lead SL4 having the high resistance connecting portion 30 to be connected. As a result, each source bonding wire SW can be connected to the source lead SL4 having the high resistance connecting portion 30 at approximately equal intervals. However, the connection position of the source bonding wire SW is not limited to this, and may be anywhere on the source lead SL4 as long as it does not come into contact with other source bonding wire SW.

In the resin sealing step S304, the source lead SL4 having the high resistance connecting portion 30 is resin-sealed by the sealing body MR together with the source bonding wire SW and the semiconductor chip 10. At this time, since the lead frame is connected by the high resistance connecting portion 30, it is possible to prevent the lead frame from moving during resin sealing, that is, the lead frame from flowing by the sealing body MR. Become. That is, as compared with the case where the source leads SL are individually arranged, the source leads SL4 having the high resistance connecting portion 30 are connected to each other and have an integrated configuration, and therefore are arranged at the time of sealing with the resin. The possibility of moving the position is reduced. This makes it possible to suppress the occurrence of defects in the manufacturing process of the semiconductor device. Further, since the source leads SL4 having the high resistance connecting portion 30 are connected to each other, it is less likely that the source lead SL4 will fall off from the encapsulant MR, so that the semiconductor device may be defective. It becomes possible to suppress.

In the resistance value measuring step S305, for example, the measuring terminal of the measuring device is connected to two source leads SL4a and SL4b which are current input / output terminals of the conductive path 102. A current is applied to the source lead SL4a, which is one of the current input / output terminals, via the connected measurement terminal. The resistance value of the conductive path 102 is calculated by measuring the voltage value which is the potential difference between the source leads SL4a and SL4b.

At this time, the conductive path 102 includes a source lead SL4a which is one current input / output terminal, a source bonding wire SW connected to the source lead SL4a which is one current input / output terminal, and a first electrode 12 on the semiconductor chip 10. The source bonding wire SW connected to the source lead SL4b, which is the other current input / output terminal, the source lead SL4b, which is the other current input / output terminal, and the respective high resistance connection portions 30 (30a to 30d), and The source bonding wire SW connected to them and a parallel connection component via the first electrode 12 are included.

Further, the resistance value of the conductive path 102 is connected to the source lead SL4a which is one current input / output terminal, the source bonding wire SW connected to the source lead SL4a which is one current input / output terminal, and the first electrode 12. The resistance between two adjacent source bonding wire SWs, the source bonding wire SW connected to the source lead SL4b which is the other current input / output terminal, the source lead SL4b which is the other current input / output terminal, and a plurality of high resistance connections. The resistance values of the parts 30 (30a to 30d), the source bonding wire SW connected to them, and the parallel connection component via the first electrode 12 are measured.

Here, the resistance values Rsl4a to Rsl4e of the source leads SL4 (SL4a to SL4e) having the high resistance connection portion 30 are 0.1 mΩ, the resistance value Rsw of the source bonding wire SW is 1 mΩ, and they are connected to and adjacent to the first electrode 12. The resistance value R12 between the two source bonding wires SW is 0.5 mΩ, and the resistance values R30a to R30d of the high resistance connection portion 30 are 1 mΩ. Further, the resistance value of the source bonding wire SW is shown in combination with the code of the connected source lead SL4. For example, the resistance value of the source bonding wire SW connected to the source lead SL4a is shown as Rsw-sl4a.

The resistance value of the conductive path 102 when the source bonding wire SW is in the normal state is
Rtotal = Rsl4a + Rsl4b + (R30a // (Rsw-sl4a + R12 + Rsw-sl4b) // (Rsw-sl4a + 2R12 + Rsw-sl4c + R30b) // (Rsw-sl4a + 3R12 + Rsw-sl4d + R30c + R30b) // (Rsw-sl4a + 4R12 + Rsw-sl4e + R30d + R30c + R30b)) ··· (A4)
Parallel component = (1 / R30a + 1 / (Rsw-sl4a + R12 + Rsw-sl4b) + 1 / (Rsw-sl4a + 2R12 + Rsw-sl4c + R30b) + 1 / (Rsw-sl4a + 3R12 + Rsw-sl4d + R30c + R30b + R30c + R30b + R30c + R30b)・ (A5)
It is expressed as. The resistance value of the conductive path 102 is determined to be 0.7064 mΩ from the above equations (A4) and (A5). Assuming that the manufacturing variation and the error of the measured value that occur even in the normal state are about 10%, it becomes 0.07064 mΩ.

Here, if a defect such as disconnection occurs in the source bonding wire SW connected to the source lead SL4a on the conductive path 102, the resistance value is Ropen (sw-sl4a) = Rsl4a + Rsl4b + R30a ... (A6).
It is represented by. In this case, the resistance value of the conductive path 102 is determined to be 1.2 mΩ, which is sufficiently high resistance with respect to the resistance value in the normal state.

Further, if a defect such as disconnection occurs in the source bonding wire SW connected to the source lead SL4b on the conductive path 102, the resistance value is determined.
Ropen (sw-sl4b) = Rsl4a + Rsl4b + (R30a // (Rsw-sl4a + 2R12 + Rsw-sl4c + R30b) // (Rsw-sl4a + 3R12 + Rsw-sl4d + R30c + R30b) + R4 + R30b + R30b) // R30c + R30b
The resistance value of the conductive path 102 is 0.8350 mΩ.

From these results, when a defect such as disconnection occurs, the difference from the resistance value in the normal state is at least 0.1286 mΩ or more. That is, the difference in resistance value is larger than the manufacturing variation of about 10% of the resistance value and the error in the measured value. As a result, it is sufficiently possible to detect a defective state. As a result, even if any of the source bonding wires SW is broken and becomes defective, the defect can be easily determined by applying the present embodiment.

Here, the case where the source leads SL4a and SL4b having the high resistance connection portions 30 are connected to the measuring device is shown, but as in the first and second embodiments, the source having all the high resistance connection portions 30 is shown. The resistance value is measured for the lead SL4.

Further, the high resistance connection portion 30 needs to have a resistance value sufficiently larger than the resistance value of the source lead SL4 having the high resistance connection portion 30. For example, it is desirable that the resistance value is 10 times or more the resistance value of the source lead SL4 having the high resistance connection portion 30.

In the present embodiment, for example, the resistance value of the source bonding wire SW and the resistance value of the high resistance connection portion 30 are set to about 1 mΩ, but the resistance value is not limited thereto. That is, by setting the resistance value of the high resistance connection portion 30 to the same resistance value as or higher than that of the source bonding wire SW, it is possible to detect the disconnection of each source bonding wire SW.

(Embodiment 4)
FIG. 6 shows a measuring device 800 for testing the semiconductor device PKG in the resistance value measuring step S305 according to the first to third embodiments. As a configuration at the time of actual measurement, a configuration in which the semiconductor device PKG of FIG. 1 is connected is shown, and the reference numeral thereof is also shown with reference to FIG. Further, the inside of the sealed body MR of the connected semiconductor device PKG is shown through. In the fourth embodiment, the semiconductor device PKG is applied, but the semiconductor device PKG described in another embodiment may be applied.

The measuring device 800 includes a voltage / current application measuring device (also referred to as a source / measure unit) SMU1 to SMU5, probe terminals (700 to 705, 709 to 710) connected to a lead frame, each probe terminal and a voltage / current application measuring device SMU1. It has a switching matrix 802 for arbitrarily connecting to SMU5, and a package jig 801 equipped with each probe terminal (700 to 705, 709 to 710).

The package jig 801 is configured to be able to connect semiconductor devices PKG having various shapes. The probe terminals (700 to 705, 709 to 710) include probe terminals 700 to 705 and 709 for connecting to a lead frame to probe, and probe terminals 710 for connecting to a drain terminal DL on the back surface of the semiconductor device PKG. including. Further, the probe terminals (700 to 705, 709 to 710) correspond to the measurement terminals of the first to third embodiments.

FIG. 7 shows a path such as an electric current when the semiconductor device PKG is measured by using the measuring device 800 in FIG. As an example, a method of connecting the probe terminal 701 and the probe terminal 702 to the semiconductor device PKG and measuring the resistance value will be shown. In addition, some routes are omitted for convenience of explanation.

First, the measuring device 800 and the semiconductor device PKG are connected. Controlling the switching matrix 802, the drain terminal DL of the semiconductor device PKG is connected to the voltage / current application measuring device SMU5 via the probe terminal 710. Further, the gate lead GL is connected to the voltage / current application measuring device SMU4 via the probe terminal 700. Further, one source lead SL is connected to the voltage / current application measuring device SMU2 via the probe terminal 701. Yet another source lead SL is connected to the voltage / current application measuring device SMU1 via the probe terminal 702.

Further, the connection path 900 indicates a connection path between the voltage / current application measuring device SMU5 and the probe terminals 710 and 709. The connection path 901 indicates a connection path between the voltage / current application measuring device SMU4 and the probe terminal 700. The connection paths 902 and 903 and the conductive path 904 indicate a connection path between the voltage / current application measuring devices SMU2 and SMU1 and the probe terminals 701 to 702 and a conductive path in the semiconductor device PKG.

Next, the measuring device 800 sets the outputs of the voltage / current application measuring devices SMU5, SMU4, and SMU1 to 0V. A voltage of 0 V is supplied from the voltage / current application measuring device SMU5 to the probe terminal 710 and the probe terminal 709 via the connection path 900. A voltage of 0 V is supplied to the probe terminal 700 from the voltage / current application measuring device SMU4 via the connection path 901. A voltage of 0 V is supplied from the voltage / current application measuring device SMU1 to the probe terminal 702 via the connection path 903.

Next, the voltage-current application measuring device SMU2 applies a current of, for example, 50 A, and after a predetermined standby time elapses, measures the potential PV of the voltage-current application measuring device SMU2. The measuring device 800 cancels the application of current and voltage.

Next, the resistance value of the conductive path 904 is calculated by dividing the measured potential PV by the applied current 50A. When the calculated resistance value is within a predetermined range, the semiconductor device PKG is selected as a non-defective product. If the resistance value exceeds a predetermined range and shows a high value, it is selected as a defective product in which defects such as disconnection have occurred.

Next, current application and voltage measurement are performed by the measuring device 800 for all the source lead SLs. For example, by controlling the switching matrix 802, the probe terminal 703 and the probe terminal 704 are connected to the voltage / current application measuring devices SMU1 to SMU2 as shown in FIG. 6, and the current is applied to the semiconductor device PKG.

When connecting to yet another source lead SL, the combination of the voltage / current application measuring device SMU and the probe terminals (700 to 705, 709 to 710) is switched by controlling the switching matrix 802. By repeating these operations, the resistance value of the source bonding wire SW is measured and the presence or absence of a defective state is detected.

The connection between the semiconductor device PKG and the voltage / current application measuring device SMU has a switching matrix configuration using a switching matrix 802. As a result, it is sufficient to prepare a smaller number of voltage / current application measuring devices SMU than the number of gate lead GLs and source lead SLs, and it is possible to simplify the configuration of the device of the measuring device 800.

(Embodiment 5)
FIG. 8 shows another embodiment of the measuring device 800 for testing the semiconductor device PKG in the resistance value measuring step S305 according to the first to third embodiments. As an example of the configuration to be actually measured, the configuration in which the semiconductor device PKG2 of FIG. 4 is connected is shown, and the reference numeral thereof is shown with reference to FIG. Further, FIG. 8 shows the inside of the sealed body MR of the connected semiconductor device PKG2 as a perspective view. The connection unit 803 is applied instead of the switching matrix 802. Further, although the semiconductor device PKG2 is applied in the fifth embodiment, the semiconductor device PKG described in another embodiment may be applied.

In the following description, the differences from the fourth embodiment will be mainly described. The voltage / current application measuring device SMU3 is connected to the probe terminals 701 to 702 and the first lead SL1 having an integrated inner lead portion. The voltage / current application measuring device SMU2 connects the probe terminal 703 and the second lead SL2. The voltage / current application measuring device SMU1 connects the source lead SL having the inner lead portion integrated with the probe terminals 704 to 705.

The connection paths 905 and 907 show the connection paths between the voltage / current application measuring devices SMU2 to SMU3 and the probe terminals 701 to 703, and the conductive paths 906 show the conductive paths between the probe terminals 701 to 703 and the semiconductor device PKG2. The connection paths 907 and 909 indicate the connection paths between the voltage / current application measuring devices SMU1 to SMU2 and the probe terminals 703 to 705, and the conductive paths 908 indicate the conductive paths between the probe terminals 703 to 705 and the semiconductor device PKG2.

The measuring device 800 applies a current of, for example, 50 A to the voltage / current application measuring device SMU3. The current at this time flows in the order of the connection path 905, the conductive path 906, and the connection path 907. After the elapse of a predetermined standby time, the potential PV of the voltage / current application measuring device SMU3 is measured. The measuring device 800 cancels the application of current and voltage. Next, the resistance value of the conductive path 906 is calculated by dividing the measured potential PV by the applied current of 50 A.

Next, as with the first lead SL1, the other source lead SL having the shape in which the inner lead portion is integrated is measured. The measuring device 800 applies a current of, for example, 50 A to the voltage / current application measuring device SMU1. The current at this time flows in the order of the connection path 909, the conductive path 908, and the connection path 907. After the elapse of a predetermined standby time, the potential PV of the voltage / current application measuring device SMU1 is measured. The measuring device 800 cancels the application of current and voltage. Next, the resistance value of the conductive path 908 is calculated by dividing the measured potential PV by the applied current of 50 A.

Since the connection unit 803 fixedly connects the probe terminals 700 to 705 and 709 to 710 with the voltage and current application measuring devices SMU1 to SMU5, the voltage and current application measuring device required for performing the resistance value measuring step S305. The number of SMU1 to SMU5 increases. However, since the switching matrix control for connecting the probe terminals 700 to 705 and 709 to 710 and the voltage / current application measuring devices SMU1 to SMU5 is not required, the time required for the control can be reduced.

In the present embodiment, the connection unit 803 for connecting the probe terminals 700 to 705 and 709 to 710 and the voltage / current application measuring devices SMU1 to SMU5 is prepared according to the configuration of the source lead SL. The source lead SL connected to the source bonding wire SW whose resistance is to be measured and the voltage / current application measuring devices SMU1 to SMU5 are connected via the connection portion 803. As a result, it is possible to apply and measure a current to the target source bonding wire SW, and it is possible to determine the non-defective product.

Although the invention made by the present inventor has been specifically described above based on the embodiment, the present invention is not limited to the embodiment and can be variously modified without departing from the gist thereof. Needless to say.

PKG, PKG2, PKG3 Semiconductor device MR sealant 12 1st electrode 14 2nd electrode 17 3rd electrode 10 Semiconductor chip 16 Chip mounting part ADH adhesive GL Gate lead DL Drain terminal SL, SL4, SL4a to SL4e Source lead SL1 1st 1 lead SL2 2nd lead SL1a 1st part SL1b 2nd part SL1c 3rd part SW Source bonding wire GW Gate bonding wire SMU, SMU1 to SMU5 Voltage / current application measuring device 100, 101, 102, 904, 906, 908 Conductive path 700 ~ 710 Probe terminal 800 Measuring device 801 Package jig 802 Switching matrix 803 Connection part 900 ~ 903, 905, 907, 909 Connection path

Claims (12)

Manufacturing method of semiconductor device including the following steps;
(A) A step of preparing a lead frame including a chip mounting portion and first leads and second leads arranged around the chip mounting portion;
(B) A step of arranging a semiconductor chip having a first electrode on the chip mounting portion;
(C) A step of electrically connecting the first electrode of the semiconductor chip and the first lead and the second lead by individual bonding wires;
(D) A step of sealing the semiconductor chip and the first lead and the second lead with a sealant so that the first lead and a part of the second lead are exposed;
(E) After the step (d), the measurement terminal was connected to a part of the first lead and the second lead exposed from the sealing body, and was connected to the first lead and the first lead. A step of measuring the resistance value of a conductive path composed of the bonding wire, the first electrode, the bonding wire connected to the second lead, and the second lead. In the method for manufacturing a semiconductor device according to claim 1,
After the step (e), the step of (f) selecting the semiconductor device as a non-defective product when the measured resistance value is within a predetermined value range is included. In the method for manufacturing a semiconductor device according to claim 2,
The step (f) further includes a step of selecting the semiconductor device as a defective product when the measured resistance value is out of the predetermined value range. In the method for manufacturing a semiconductor device according to claim 1,
In the step (a), a lead frame including the first lead and the second lead in which the first lead and the second lead are formed separately from each other and formed in the same shape is prepared. Has a process. In the method for manufacturing a semiconductor device according to claim 1,
In the step (b), the first electrode and the second electrode different from the first electrode are formed on the first main surface of the semiconductor chip, and the second main surface opposite to the first main surface is formed. The process includes forming a third electrode and arranging the semiconductor chip on which the first to third electrodes are formed on the chip mounting portion. With semiconductor chips
With a plurality of leads arranged around the semiconductor chip,
A plurality of bonding wires for electrically connecting the plurality of leads and the semiconductor chip,
With the sealant
Have,
The encapsulant seals the semiconductor chip, each part of the plurality of leads, and the plurality of bonding wires.
The plurality of leads include a first lead and a second lead.
The first lead includes a first portion and a second portion that are separated from each other outside the sealing body, and a third portion that integrally connects the first portion and the second portion inside the sealing body. Have and
A semiconductor device in which the first lead and the second lead are individual bonding wires among the plurality of bonding wires and are electrically connected to the semiconductor chip. In the semiconductor device according to claim 6,
The first lead and the second lead are connected to a first electrode formed on the first main surface of the semiconductor chip via the individual bonding wires. In the semiconductor device according to claim 7,
A second electrode different from the first electrode is formed on the first main surface of the semiconductor chip, and a third electrode is formed on the second main surface opposite to the first main surface. A semiconductor chip having a first electrode and
A plurality of leads arranged around the semiconductor chip and arranged at predetermined intervals,
A plurality of bonding wires for electrically connecting the first electrode of the semiconductor chip and the plurality of leads,
With the sealant
Have,
The encapsulant seals the semiconductor chip, a part of each of the plurality of leads, and the plurality of bonding wires.
It has a high resistance connection located between the plurality of leads and connects each of the plurality of leads inside the sealant.
In a plan view, the high resistance connection portion is a semiconductor device having a narrow width as compared with the width of each of the plurality of leads protruding to the outside of the sealing body. In the semiconductor device according to claim 9,
The resistance value of the high resistance connection portion is larger than the resistance value of each of the plurality of leads. In the semiconductor device according to claim 10,
The resistance value of the high resistance connection portion is 10 times or more the resistance value of each of the plurality of leads. In the semiconductor device according to claim 10,
The first electrode and a second electrode different from the first electrode are formed on the first main surface of the semiconductor chip, and the third electrode is formed on the second main surface opposite to the first main surface. To.