JP2012163466A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of easily detecting disconnection of wiring for connection between itself and another device.SOLUTION: A semiconductor chip 1 comprises: a power supply node 5; a ground node G1; a pad 11 for connecting a wire 13; and a detection circuit 14 for detecting a poor electrical connection by the wire 13 between a semiconductor chip 51 and a semiconductor chip 52. The detection circuit 14 comprises: a voltage generation circuit 14a provided between the power supply node 5 and the pad 11; and a switch circuit SW provided between the power supply node 5 and the ground node G1, which is turned on by application of a predetermined voltage to the pad 11. When a poor electrical connection between the semiconductor chip 51 and the semiconductor chip 52 is caused by the wire 13, the voltage generation circuit 14a applies voltage for turning on the switch circuit SW to the pad 11.

Description

  The present invention relates to a semiconductor device having a plurality of semiconductor chips. In particular, the present invention relates to a semiconductor device having a function of detecting the quality of a wiring connecting two semiconductor chips.

  There is a semiconductor product in which a plurality of semiconductor chips are mounted in the same package. Such products are required to reduce the number of terminals (pins) of the package. Therefore, it is difficult to couple a signal transmitted between two semiconductor chips to an external pin of the package. For these reasons, these two chips are connected by internal wiring, that is, wiring provided inside the package.

  Even if two semiconductor chips are non-defective products, if there is a defect in the internal wiring that connects them, the semiconductor product is defective. Internal wiring is not connected to external terminals. For this reason, the quality of the internal wiring has been confirmed by confirming the operation of the two chips by a function test.

  However, in the case of a function test, it is difficult to distinguish between a defective semiconductor chip and a defective internal wiring. For this reason, when analyzing a semiconductor product that has been determined to be defective by a functional test, a great deal of labor is required to identify the cause of the defect.

  Therefore, a technique for easily detecting the disconnection of the wiring connecting the two semiconductor chips has been proposed. For example, in the inspection method disclosed in Japanese Patent Application Laid-Open No. 2008-122338 (Patent Document 1), a static current is caused to flow through wirings connecting between ICs (integrated circuits) or between circuit blocks, and wiring abnormalities are caused by changes in the currents. Is detected.

  For example, Japanese Patent Laid-Open No. 11-183548 (Patent Document 2) discloses a test method for testing a connection between two ICs. That is, in the test method, a voltage difference is generated between the power supply of the preceding IC and the power supply of the subsequent IC. If the connection between the two ICs is normal, the current (from the power supply of the preceding IC to the power supply of the subsequent IC via the output terminal, wiring, and input terminal of the subsequent IC from the previous IC) Leak current) flows. Based on this current, the connection state is confirmed.

JP 2008-122338 A JP 11-183548 A

  According to the methods described in Japanese Patent Application Laid-Open No. 2008-122338 (Patent Document 1) and Japanese Patent Application Laid-Open No. 11-183548 (Patent Document 2), when the wiring between the two semiconductor chips is normal, current is supplied. Whereas current flows, no current flows when the wiring is disconnected. In such an inspection method, when the number of wirings between two semiconductor chips is large, the total value of currents flowing through the wirings becomes large. When one wire is disconnected, the total value decreases. However, the amount of decrease in current is smaller than the total value of current in the normal case. For this reason, according to the above method, it is difficult to easily detect that the internal wiring is disconnected.

  An object of the present invention is to provide a semiconductor device capable of easily detecting a disconnection of a wiring for connecting the semiconductor device to another semiconductor device.

  According to an embodiment of the present invention, a semiconductor device connects a power supply node, a ground node, and a conductor to be connected between the semiconductor device and another semiconductor device to the semiconductor device. And a detection circuit for detecting a failure in electrical connection between the semiconductor device and another semiconductor device due to the conductor. The detection circuit is provided between the power supply node and the pad, and applies a predetermined voltage to the pad when the electrical connection between the semiconductor device and the other semiconductor device by the conductor is poor. And a switch circuit provided between the power supply node and the ground node and configured to be turned on when a predetermined voltage is applied to the pad by the voltage generation circuit. Including.

  According to another embodiment of the present invention, a semiconductor device includes a first semiconductor chip, a second semiconductor chip, and a conductor connected between the first semiconductor chip and the second semiconductor chip. With. The first semiconductor chip includes a first power supply node, a ground node, a first pad connected to the conductor, and an electrical connection between the first semiconductor chip and the second semiconductor chip by the conductor. And a detection circuit for detecting a connection failure. The detection circuit is provided between the first power supply node and the first pad, and when the electrical connection between the first semiconductor chip and the second semiconductor chip by the conductor is poor, A voltage generation circuit configured to apply a predetermined voltage to the first pad and a first power supply node and a ground node are provided, and the voltage generation circuit applies a predetermined voltage to the first pad. And a switch circuit configured to be turned on when given.

  According to the above embodiment, it is possible to realize a semiconductor device capable of easily detecting a disconnection of a wiring for connecting itself to another semiconductor device.

1 is a block diagram showing a schematic configuration of a semiconductor device according to a first embodiment. It is the figure which showed an example of the package with which the semiconductor chips 51 and 52 shown in FIG. 1 were mounted. 1 is a diagram illustrating a configuration of a disconnection detection circuit according to a first embodiment and a peripheral portion thereof. It is a figure for demonstrating operation | movement of the detection circuit 14 when the wire which connects the pads 11 and 12 is normal. It is a figure for demonstrating operation | movement of the detection circuit 14 when the wire which connects the pads 11 and 12 is disconnected. It is the figure which showed the structure of the disconnection detection circuit which concerns on Embodiment 2, and its peripheral part. FIG. 7 is a diagram showing a configuration of a circuit for generating a signal Vref shown in FIG. 6. FIG. 10 is a diagram for explaining an operation of a detection circuit 14 according to the second embodiment. FIG. 6 is a diagram illustrating a configuration of a disconnection detection circuit according to a third embodiment and its peripheral portion. FIG. 10 is a plan view schematically illustrating PMOS transistors 15 and 30 shown in FIG. 9. FIG. 6 is a diagram schematically showing a configuration of a semiconductor device according to a fourth embodiment. FIG. 10 is a diagram illustrating an example of a package of a semiconductor product according to a fifth embodiment. FIG. 16 is a diagram showing another example of a semiconductor product package according to the fifth embodiment. FIG. 10 is a block diagram showing a schematic configuration of a semiconductor device according to a sixth embodiment. It is the figure which showed the structure of the disconnection detection circuit which concerns on Embodiment 6, and its periphery part.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

[Embodiment 1]
FIG. 1 is a block diagram showing a schematic configuration of the semiconductor device according to the first embodiment. Referring to FIG. 1, the semiconductor device 50 includes semiconductor chips 51 and 52. The type of the semiconductor chips 51 and 52 is not particularly limited.

  The semiconductor device 50 further includes a plurality of wires 13. Each of the plurality of wires 13 is connected between the semiconductor chip 51 and the semiconductor chip 52, and transmits a signal between the semiconductor chip 51 and the semiconductor chip 52.

  The semiconductor chip 51 includes a circuit block 51a, an input / output unit 51b, and a plurality of detection circuits 14. The input / output unit 51b includes a plurality of output circuits 1a and 1b, a plurality of input circuits 1c, and a plurality of pads 11 provided corresponding to the plurality of output circuits 1a and 1b and the plurality of input circuits 1c, respectively. .

  The semiconductor chip 52 includes a circuit block 52a and an input / output unit 52b. The input / output unit 52b includes a plurality of input circuits 2a, 2b, a plurality of output circuits 2c, and a plurality of pads 12 provided corresponding to the plurality of input circuits 2a, 2b and the plurality of output circuits 2c, respectively. . The wire 13 is connected between the pad 11 of the semiconductor chip 51 and the pad 12 of the semiconductor chip 52. Therefore, a signal transmitted through the wire 13 is not coupled to an external pin (not shown) of the semiconductor device 50.

  Each of the output circuits 1 a and 1 b outputs a signal sent from the circuit block 51 a to the outside of the semiconductor chip 51 through the pad 11. Each of the plurality of input circuits 2 a and 2 b receives a signal through the corresponding wire 13 and the corresponding pad 12. The circuit block 52a operates in response to a signal received by each of the plurality of input circuits 2a and 2b.

  Each of the plurality of output circuits 2 c outputs a signal sent from the circuit block 52 a to the outside of the semiconductor chip 52 through the pad 12. Each of the plurality of input circuits 1 c receives a signal through the corresponding wire 13 and the corresponding pad 11.

  The plurality of detection circuits 14 are provided in the semiconductor chip 51 corresponding to the plurality of wires 13, respectively, and detect a failure in electrical connection between the semiconductor chips 51 and 52 by the corresponding wires 13. In the following description, a broken wire is shown as an example of such a defect. However, the above-mentioned “defective” may include that the connection between the wire 13 and the pad 11 is defective, or that the connection between the wire 13 and the pad 12 is defective.

  Further, in this specification, “wiring” means a conductor for transmitting a signal between two semiconductor chips, in other words, a conductor for electrically connecting the two semiconductor chips. Therefore, the form of “wiring” is not particularly limited. The wire 13 shown in FIG. 1 is one embodiment of “wiring”.

  Although the semiconductor chip 51 shown in FIG. 1 has two types of output circuits, an output circuit having the same configuration may be used for the semiconductor chip 51. Similarly, an input circuit having the same configuration may be used for the semiconductor chip 52. The configurations of the output circuit and the input circuit are determined depending on the mode of signal transmission between the semiconductor chips 51 and 52. Further, the number of output circuits and corresponding input circuits is not particularly limited.

  FIG. 2 is a view showing an example of a package on which the semiconductor chips 51 and 52 shown in FIG. 1 are mounted. Referring to FIG. 2, semiconductor chips 51 and 52 are mounted in, for example, a QFP (Quad Flat Package) type package. More specifically, the semiconductor chips 51 and 52 are mounted on a die pad 54 and sealed with a resin 53. The semiconductor chips 51 and 52 exchange signals with the outside through the external terminals 55. A signal is transmitted between the semiconductor chips 51 and 52 by the wire 13. However, the wire 13 is not connected to the external terminal 55. Therefore, a circuit for detecting disconnection of the wire 13 is arranged on the semiconductor chip 51.

  FIG. 3 is a diagram illustrating a configuration of the disconnection detection circuit according to the first embodiment and its peripheral portion. Referring to FIG. 3, the detection circuit 14 is provided on the semiconductor chip 51 and connected to a wiring that connects the output circuit 1 a and the pad 11. Detection circuit 14 includes switch circuit SW provided between power supply node 5 and ground node G1, and voltage generation circuit 14a.

  Switch circuit SW includes a PMOS transistor 15 and an NMOS transistor 17 connected in series between power supply node 5 and ground node G1. Each of power supply node 5 and ground node G1 is connected to external terminal 55 shown in FIG.

  A test mode signal / φTM is input to the gate of the PMOS transistor 15. The test mode signal / φTM is generated by, for example, the circuit block 51a (see FIG. 1) of the semiconductor chip 51, and the mode of the semiconductor chip 51 is changed to the test mode for detecting the disconnection of the wire 13 and other modes (for example, the normal mode). Switch between While the signal / φTM is valid in the test mode, the signal / φTM is invalid in modes other than the test mode. In the embodiment of the present invention, the signal / φTM is valid when the level of the signal / φTM is L level, and the signal / φTM is invalid when the level of the signal / φTM is H level.

  The gate of the NMOS transistor 17 is connected to the pad 11 via the node N1. Therefore, the voltage at the node N1 is substantially equal to the voltage at the pad 11.

  When the wire 13 is disconnected, the voltage generation circuit 14a generates a predetermined voltage for turning on the switch circuit SW. The voltage generation circuit 14 a includes a resistance element 18 and a PMOS transistor 16. Resistance element 18 and PMOS transistor 16 are connected in series between power supply node 5 and pad 11. One end of resistance element 18 is connected to a power supply node. The PMOS transistor 16 is connected between the other end of the resistance element 18 and the pad 11. The test mode signal / φTM is input to the gate of the PMOS transistor 16.

  The output circuit 1 a includes a PMOS transistor 3 and an NMOS transistor 4. PMOS transistor 3 and NMOS transistor 4 are connected in series between power supply node 5 and ground node G1.

  On the other hand, the semiconductor chip 52 includes the pad 12 connected to the wire 13 and the input circuit 2a. Input circuit 2 a includes protective diodes 6, 7, PMOS transistor 8, and NMOS transistor 9.

  The anode of the protection diode 6 is connected to the pad 12. The cathode of protection diode 6 is connected to power supply node 10. The anode of protection diode 7 is connected to ground node G2. The cathode of the protection diode 7 is connected to the pad 12.

  PMOS transistor 8 and NMOS transistor 9 are connected in series between power supply node 10 and ground node G2. Both the gate of the PMOS transistor 8 and the gate of the NMOS transistor 9 are connected to the pad 12.

  Next, the operation of the detection circuit 14 shown in FIG. 3 will be described. FIG. 4 is a diagram for explaining the operation of the detection circuit 14 when the wires connecting the pads 11 and 12 are normal. Referring to FIG. 4, when the disconnection of wire 13 is inspected, first, the voltage of power supply node 5 of semiconductor chip 51 is set higher than the voltage of power supply node 10 of semiconductor chip 52. As a specific example, an appropriate predetermined voltage (for example, 3.3V) is applied to the power supply node 5 of the semiconductor chip 51, and the voltage of the power supply node 10 of the semiconductor chip 52 is set to 0V.

  Next, the voltage level of test mode signal / φTM is set to L level. The PMOS transistor 16 is turned on by an L level test mode signal / φTM. When the wire 13 is normal, the pads 11 and 12 are electrically connected by the wire 13. Further, the voltage at power supply node 5 is higher than the voltage at power supply node 10. Therefore, current I 1 flows from power supply node 5 to power supply node 10 through resistance element 18, PMOS transistor 16, pad 11, wire 13, pad 12, and protection diode 6. The dashed arrow shown in FIG. 4 indicates the path of the current I1.

  The resistance value of the resistance element 18 is significantly larger than the resistance value of the protection diode 6 when a forward current flows through the protection diode 6. For example, the resistance value of the resistance element 18 is 10 MΩ. Therefore, when the current I1 flows as shown by the dashed arrow, the voltage generation circuit 14a generates a voltage of approximately 0V at the pad 11. For this reason, the voltage of the node N1 is also approximately 0V.

  The PMOS transistor 15 is turned on by the L level test mode signal / φTM. However, since the voltage at the node N1 is lower than the threshold voltage of the NMOS transistor (almost 0V), the NMOS transistor 17 is off. Therefore, the switch circuit SW is in an off state.

  In this case, the current I1 that flows mainly through the detection circuit 14 is a current that flows through the resistance element 18 and the PMOS transistor 16. However, since the resistance value of the resistance element 18 is high, the current I1 is a minute current. For example, when resistance value of resistance element 18 is 10 MΩ, voltage of power supply node 5 is 3.3 V, and voltage of power supply node 10 is 0 V, current I1 flowing through resistance element 18 is about 0. It is estimated to be 33 (μA).

  FIG. 5 is a diagram for explaining the operation of the detection circuit 14 when the wire connecting the pads 11 and 12 is disconnected. Referring to FIG. 5, when the wire 13 is disconnected for some reason, no current flows from the pad 11 to the pad 12. In this case, the node N1 is charged by the current flowing through the resistance element 18 and the PMOS transistor 16. As a result, the voltage of the pad 11 and the voltage of the node N1 become a voltage (H (High) level voltage) exceeding the threshold voltage of the NMOS transistor 17. For example, the voltage at node N1 is approximately equal to the voltage at power supply node 5 (eg, 3.3 V). In this case, the NMOS transistor 17 is turned on.

  As described above, the PMOS transistor 15 is turned on by the L-level test mode signal / φTM. When the NMOS transistor 17 is turned on, the switch circuit SW is turned on. That is, when the wire 13 is disconnected, the voltage generation circuit 14a applies a predetermined voltage for turning on the switch circuit SW to the pad 11.

  When switch circuit SW is turned on, current I2 flows from power supply node 5 toward ground node G1. Each of the PMOS transistor 15 and the NMOS transistor 17 has a small on-resistance. Therefore, current I2 flowing from power supply node 5 to ground node G1 is larger than current I1 shown in FIG. 4, that is, a current flowing from pad 11 to pad 12 when wire 13 is normal. For example, the current I2 is several mA.

  Thus, the magnitude of the current flowing out from the power supply node 5 varies depending on whether or not the wire 13 is disconnected. Therefore, it is possible to easily detect whether or not the wire 13 is disconnected by measuring the value of the current flowing out from the power supply node 5. The power supply node 5 is connected to an external terminal. Therefore, whether or not the wire 13 is disconnected can be easily detected by applying a predetermined voltage to the external terminal and detecting the current flowing through the terminal.

  As described above, according to the first embodiment, when the wire connecting the first semiconductor chip and the second semiconductor chip is disconnected, it flows out from the power supply node (power supply terminal) of the first semiconductor chip. The current increases. Therefore, by measuring the current flowing out from the power supply node, it is possible to easily detect a wire breakage failure.

  Here, it is assumed that the detection circuit is configured so that the current flowing out from the power supply terminal is reduced when the wire is disconnected. When there are a plurality of wires connecting the first semiconductor chip and the second semiconductor chip and all of the wires are normal, the current flowing out from the power supply terminal is large. The amount of decrease in current when one of the plurality of wires is disconnected is smaller than the current value when all of the plurality of wires are normal. For this reason, it becomes difficult to detect disconnection of one wire.

  On the other hand, according to the first embodiment, the current value when the plurality of wires is normal is small, but the current increases when at least one of the plurality of wires is disconnected. Therefore, according to the first embodiment, it is possible to easily detect a disconnection failure.

  Further, according to the first embodiment, when test mode signal / φTM is valid (when the level of signal / φTM is L level), switch circuit SW is set to the voltage of pad 11 (the voltage of node N1). Turn on and off accordingly. On the other hand, when test mode signal / φTM is invalid (when signal / φTM is at the H level), PMOS transistor 15 is turned off. For this reason, the switch circuit SW is turned off regardless of whether or not the wire 13 is disconnected.

  In this manner, the function of the detection circuit 14 is switched between valid and invalid according to the test mode signal. For example, when the function of the detection circuit 14 is always effective, there is a possibility that the detection circuit 14 may have some influence on the operation of the semiconductor chip 51 or the semiconductor chip 52 in the normal mode. According to the first embodiment, the test mode signal / φTM is invalidated in the normal mode. As a result, the possibility that any influence caused by the detection circuit 14 affects the operation of the semiconductor chip 51 or the semiconductor chip 52 can be reduced.

[Embodiment 2]
The overall configuration of the semiconductor product according to the second embodiment is the same as the configuration shown in FIG. The second embodiment is different from the first embodiment in the configuration of the voltage generation circuit included in the disconnection detection circuit.

  In the first embodiment, the voltage generation circuit includes a resistance element having a high resistance value. However, generally, the higher the resistance value, the larger the layout area of the resistance element. Therefore, in the case of the detection circuit according to the first embodiment, the layout area may be increased. As shown in FIG. 1, the disconnection detection circuit is provided in the semiconductor chip 51 for each wire connecting the semiconductor chip 51 and the semiconductor chip 52. The total layout area of all disconnection detection circuits increases as the number of wires increases. Therefore, according to the configuration of the detection circuit according to the first embodiment, there is a concern that the size of the semiconductor chip 51 increases. In the second embodiment, a configuration capable of reducing the layout area of the disconnection detection circuit will be described.

  FIG. 6 is a diagram showing a configuration of the disconnection detection circuit and its peripheral portion according to the second embodiment. 3 and 6, the disconnection detection circuit according to the second embodiment is different from the disconnection detection circuit according to the first embodiment in that a voltage generation circuit 14b is provided instead of the voltage generation circuit 14a. The voltage generation circuit 14b is different from the voltage generation circuit 14a in that a PMOS transistor 20 is provided instead of the resistance element 18. A signal Vref is input to the gate of the PMOS transistor 20. The signal Vref is generated by a signal generation circuit described below.

  FIG. 7 is a diagram showing a configuration of a circuit for generating signal Vref shown in FIG. Referring to FIG. 7, signal generation circuit 21 and test mode setting circuit 28 are included in circuit block 51a. The signal generation circuit 21 includes a resistance element 22, a PMOS transistor 23, NMOS transistors 24 and 25, and a PMOS transistor 26.

  One end of resistance element 22 is connected to power supply node 5. The resistance element 22 has a high resistance value like the resistance element 18.

  The PMOS transistor 23 is connected between the other end of the resistance element 22 and the drain of the NMOS transistor. A test mode signal / φTM is input to the gate of the PMOS transistor 23. Test mode setting circuit 28 generates test mode signal / φTM. Test mode setting circuit 28 switches the level of test mode signal / φTM between L level and H level by a signal from the outside of semiconductor chip 51, for example. As shown in FIG. 6, the signal Vref is input to the switch circuit SW of the detection circuit 14.

  The NMOS transistors 24 and 25 constitute a current mirror circuit. The drain of the NMOS transistor 24 is connected to the gates of the NMOS transistors 24 and 25. The drain of NMOS transistor 25 is connected to the gate and drain of PMOS transistor 26 at node N2. The source of the PMOS transistor 26 is connected to the power supply node 5. The signal Vref is output from the node N2 and input to the detection circuit 14 (more specifically, the voltage generation circuit 14b) shown in FIG.

  Since the configuration of the other part of the semiconductor product according to the second embodiment is the same as the configuration of the corresponding part of the semiconductor product according to the first embodiment, the following description will not be repeated.

  FIG. 8 is a diagram for explaining the operation of the detection circuit 14 according to the second embodiment. When disconnection of wire 13 is detected, the level of test mode signal / φTM is set to L level. As a result, the PMOS transistor 26 is turned on. When the PMOS transistor 26 is turned on, a current Io flows through the resistance element 22, the PMOS transistor 23, and the NMOS transistor 24. Since the resistance value of the resistance element 22 is high (for example, the resistance value is 10 MΩ), the current Io is a very small current.

  Since the NMOS transistors 24 and 25 constitute a current mirror circuit, a current (denoted as a current Io) having the same magnitude as the current Io flowing through the resistance element 22 flows through the NMOS transistor 25. Since the PMOS transistor 26 and the NMOS transistor 25 are connected in series between the power supply node 5 and the ground node G1, the current flowing through the PMOS transistor 26 is Io.

  The voltage of the signal Vref is equal to the gate voltage of the PMOS transistor 26 for causing the current Io to flow through the PMOS transistor 26. Since the current Io is small, the difference between the voltage of the power supply node 5 and the voltage of the signal Vref is small. That is, the amplitude of the signal Vref is limited.

  Referring to FIG. 6, signal Vref is input to the gate of PMOS transistor 20. Since the amplitude of the signal Vref is limited, the resistance value of the PMOS transistor 20 becomes high. At this time, the current flowing through the PMOS transistor 20 is extremely smaller than the current flowing through the PMOS transistor 20 when the PMOS transistor 20 is fully turned on. That is, the PMOS transistor 20 functions as a resistance circuit in the same manner as the resistance element 18. As in the first embodiment, when the wire 13 is disconnected, the voltage generation circuit 14b generates a predetermined voltage for turning on the switch circuit SW on the pad 11 (node N1).

  The signal generation circuit 21 collectively supplies the signal Vref to the plurality of detection circuits 14. For this reason, the same number of signal generation circuits as the plurality of detection circuits 14 need not be provided. Further, each of the plurality of detection circuits 14 does not include a resistance element that requires a large layout area. Therefore, according to the second embodiment, not only wire breakage can be easily detected, but also increase in chip size can be avoided.

[Embodiment 3]
The overall configuration of the semiconductor product according to the third embodiment is the same as the configuration shown in FIG. The third embodiment is different from the first embodiment in the configuration of the voltage generation circuit included in the disconnection detection circuit.

  FIG. 9 is a diagram showing a configuration of the disconnection detection circuit and its peripheral portion according to the third embodiment. 3 and 9, the disconnection detection circuit according to the third embodiment is different from the disconnection detection circuit according to the first embodiment in that a PMOS transistor 30 is provided instead of the voltage generation circuit 14a. The PMOS transistor 30 has the same function as the voltage generation circuit 14a shown in FIG. A test mode signal / φTM is input to the gate of the PMOS transistor 30.

  FIG. 10 is a plan view schematically illustrating the PMOS transistors 15 and 30 shown in FIG. Referring to FIG. 10, “D” and “S” indicate the drain region and the source region of PMOS transistors 15 and 30, respectively. “G” indicates the gate electrodes of the PMOS transistors 15 and 30.

  The channel width of the PMOS transistor 15 and the channel width of the PMOS transistor 30 are both W. On the other hand, the channel length L2 of the PMOS transistor 30 is larger than the channel length L1 of the PMOS transistor 15 (L2> L1). The PMOS transistors 15 and 30 are formed through the same manufacturing process. Therefore, when the gate voltages applied to the PMOS transistors 15 and 30 are equal to each other, the on-resistance of the PMOS transistor 30 is higher than the on-resistance of the PMOS transistor 15.

  Returning to FIG. 9, when a disconnection failure of the wire 13 is detected, the L-level test mode signal / φTM is input to the gate electrodes of the PMOS transistors 15 and 30. The on-resistance of the PMOS transistor 30 is higher than the on-resistance of the PMOS transistor 15. Therefore, the current flowing through the PMOS transistor 30 is a minute current. That is, when test mode signal / φTM is at L level, PMOS transistor 30 performs the same function as resistance element 18 (see FIG. 3).

  When the level of test mode signal / φTM is H level, PMOS transistor 30 is turned off. That is, in this case, the PMOS transistor 30 performs the same function as the PMOS transistor 16 (see FIG. 3).

  According to the third embodiment, the disconnection of the wire can be easily detected as in the first and second embodiments. Further, as in the second embodiment, in the third embodiment, the resistance element that requires a large layout area is not included in the disconnection detection circuit. In the third embodiment, a PMOS transistor having a large channel length is included in the disconnection detection circuit, but the layout area of the PMOS transistor is significantly smaller than the layout area of the resistance element. Therefore, similarly to the second embodiment, according to the third embodiment, an increase in chip size can be avoided.

  Furthermore, in the second embodiment, a circuit for generating signal Vref from test mode signal / φTM is required. In the third embodiment, such a circuit can be omitted.

[Embodiment 4]
In the fourth embodiment, one specific form of a semiconductor product on which the disconnection detection circuit according to any of the first to third embodiments is mounted will be described.

  FIG. 11 is a diagram schematically showing the configuration of the semiconductor device according to the fourth embodiment. Referring to FIG. 11, semiconductor device 50 </ b> A includes semiconductor chips 61 and 62.

  The semiconductor chip 61 is a logic chip. The semiconductor chip 62 is a memory chip. That is, in the fourth embodiment, the semiconductor device 50A is realized as a SIP (System In Package) on which a logic chip and a memory chip are mounted.

  Specifically, the semiconductor chip 61 includes a logic circuit block 61a that executes various logical operations. On the other hand, the semiconductor chip 62 includes a memory circuit block 62a for storing information.

  The detection circuit 14 is disposed on the logic chip (semiconductor chip 61). The detection circuit 14 is not required for the memory chip (semiconductor chip 62). Therefore, a general-purpose memory chip can be combined with the logic chip (semiconductor chip 61). This makes it easy to obtain a memory chip. Furthermore, various SIP products can be realized at low cost.

[Embodiment 5]
In the fifth embodiment, an example of another package of a semiconductor product on which the disconnection detection circuit according to any of the first to third embodiments is mounted will be described.

  FIG. 12 is a view showing an example of a semiconductor product package according to the fifth embodiment. Referring to FIG. 12, semiconductor device 50B has a BGA (Ball Grid Array) package.

  The semiconductor chips 51 and 52 are mounted on the substrate 56. The substrate 56 is a multilayer wiring substrate and has a plurality of wirings 57. The pad 11 of the semiconductor chip 51 and the pad 12 of the semiconductor chip 52 are connected by the wire 13 and the wiring 57 of the substrate 56. A ball electrode 58 is provided as an external terminal. Each of the semiconductor chips 51 and 52 is connected to the ball electrode 58 via the wire 13 and the wiring 57 of the substrate 56.

  In the case of the example shown in FIG. 12, the cause of the poor connection between the semiconductor chip 51 and the semiconductor chip 52 is, for example, the disconnection of the wire 13, the disconnection of the wiring 57 of the substrate 56, and the wiring of the wire 13 and the substrate 56. 57 or the like. Since the semiconductor chip 51 includes the detection circuit 14, such a defect can be detected.

  FIG. 13 is a view showing another example of the package of the semiconductor product according to the fifth embodiment. Referring to FIG. 13, semiconductor device 50C has a flip chip bond structure. Specifically, each of the semiconductor chips 51 and 52 is connected to the wiring 57 of the substrate 56 by the ball electrode 59. Therefore, the pad 11 of the semiconductor chip 51 and the pad 12 of the semiconductor chip 52 are connected to each other by the ball electrode 59 and the wiring 57 of the substrate 56.

  In the example shown in FIG. 13, the cause of the poor connection between the semiconductor chip 51 and the semiconductor chip 52 is, for example, a poor connection between the ball electrode 59 and the wiring 57 on the substrate 56 or the wiring 57 on the substrate 56 Disconnection or the like. Since the semiconductor chip 51 includes the detection circuit 14, such a defect can be detected.

  As described above, according to the fifth embodiment, it is possible to detect a defect in a wiring connecting two semiconductor chips housed in a package regardless of the package of the semiconductor device.

[Embodiment 6]
FIG. 14 is a block diagram showing a schematic configuration of the semiconductor device according to the sixth embodiment. Referring to FIG. 14, semiconductor device 50 </ b> D is different from semiconductor device 50 in that a plurality of detection circuits 14 are provided in semiconductor chip 52. Specifically, the plurality of detection circuits 14 are provided between the pad 12 and the input circuit 2a (or the input circuit 2b).

  FIG. 15 is a diagram showing a configuration of the disconnection detection circuit according to the sixth embodiment and its peripheral portion. Referring to FIG. 15, the detection circuit 14 is provided on the semiconductor chip 52 and is connected to a wiring that connects the input circuit 2 a and the pad 12. In this respect, the sixth embodiment is different from the first embodiment. Furthermore, the sixth embodiment differs from the first embodiment in the following points. That is, switch circuit SW is provided between power supply node 10 and ground node G2. Further, resistance element 18 and PMOS transistor 16 constituting voltage generation circuit 14 a are connected in series between power supply node 10 and pad 12.

  Since the configuration of other parts of the semiconductor product according to the sixth embodiment is the same as the corresponding contents of the semiconductor product according to the first embodiment, the following description will not be repeated.

  According to the configuration according to the sixth embodiment, when the disconnection of the wire 13 is detected, a predetermined voltage (for example, 3.3 V, 5 V, but not limited thereto) is applied to the power supply node 10, and the power supply Node 5 is grounded. The level of test mode signal / φTM is set to L level.

  When the wire 13 is normal, the PMOS transistor 3 functions as a diode that allows a forward current to flow from the pad 11 to the power supply node 5. Thus, the voltage on pad 12 is approximately equal to 0V. For this reason, the switch circuit SW is turned off. Since the resistance value of resistance element 18 is large, the current flowing out from power supply node 10 is small.

  On the other hand, when the wire 13 is disconnected, the voltage of the pad 12 and the voltage level of the node N2 become H level, and the switch circuit SW (NMOS transistor 17) is turned on. Therefore, a large current flows between power supply node 10 and ground node G2.

  Thus, the operation of the detection circuit 14 is the same both when the detection circuit 14 is arranged on the semiconductor chip 51 and when the detection circuit 14 is arranged on the semiconductor chip 52. Therefore, according to the sixth embodiment, the disconnection failure of the wire 13 can be easily detected by measuring the current flowing out from the power supply node 10.

  Further, the detection circuit according to the second embodiment or the detection circuit according to the third embodiment can be applied to the configuration shown in FIG.

  Further, the type of package of the semiconductor device according to the sixth embodiment is not particularly limited, and may be a QFP package as in the first embodiment, or may be a BGA package or a flip chip bond structure as in the fifth embodiment. .

  The embodiment disclosed this time must be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  1a, 1b, 2c output circuit, 1c, 2a, 2b input circuit, 3, 8, 15, 16, 20, 23, 26, 30 PMOS transistor, 4, 9, 17, 24, 25 NMOS transistor, 5, 10 power supply Node, 6, 7 Protection diode, 11, 12 Pad, 13 wire, 14 Detection circuit, 14a, 14b Voltage generation circuit, 18, 22 Resistance element, 21 Signal generation circuit, 28 Test mode setting circuit, 50, 50A-50D Semiconductor Device, 51, 52, 61, 62 Semiconductor chip, 51a, 52a Circuit block, 51b, 52b Input / output section, 53 Resin, 54 Die pad, 55 External terminal, 56 Substrate, 57 Wiring, 58, 59 Ball electrode, 61a Logic circuit Block, 62a memory circuit block, G1, G2 ground node, N1, N2 node De, SW switch circuit.

Claims (16)

A semiconductor device,
A power node;
A ground node;
A pad for connecting a conductor to be connected between the semiconductor device and another semiconductor device to the semiconductor device;
A detection circuit for detecting a failure in electrical connection between the semiconductor device and the other semiconductor device by the conductor;
The detection circuit includes:
A predetermined voltage is applied to the pad when the electrical connection between the semiconductor device and the other semiconductor device, which is provided between the power supply node and the pad, is poor by the conductor. A voltage generating circuit configured to:
A semiconductor device including a switch circuit provided between the power supply node and the ground node and configured to be turned on when the predetermined voltage is applied to the pad by the voltage generation circuit; . The switch circuit is
A first transistor connected to the power supply node and turned on and off in response to a test mode signal;
A second transistor connected between the first transistor and the ground node and having a gate coupled to the pad;
When the test mode signal indicates that the detection of the electrical connection is valid, the first transistor is turned on, whereas the test mode signal indicates that the detection of the electrical connection is invalid. The semiconductor device according to claim 1, wherein the first transistor is turned off. The voltage generation circuit includes:
The semiconductor device according to claim 2, comprising a resistance circuit connected between the power supply node and the pad. The resistor circuit is
A resistance element connected to the power supply node;
A third transistor connected between the resistive element and the pad and turned on and off in response to the test mode signal;
If the test mode signal indicates that the detection of the electrical connection is valid, the third transistor is turned on, whereas the test mode signal indicates that the detection of the electrical connection is invalid. The semiconductor device according to claim 3, wherein the third transistor is turned off. The resistor circuit is
A third transistor and a fourth transistor connected in series between the power supply node and the pad, each being turned on and off in response to the test mode signal;
The semiconductor device includes:
A signal generating circuit for generating a control signal for driving the third transistor based on the test mode signal when the test mode signal indicates that the detection of the electrical connection is valid; ,
The signal generation circuit generates the control signal such that a current smaller than a current flowing through the third transistor flows through the third transistor when the third transistor is fully turned on;
If the test mode signal indicates that the detection of the electrical connection is valid, the fourth transistor is turned on while the test mode signal indicates that the detection of the electrical connection is invalid. 4. The semiconductor device according to claim 3, wherein the fourth transistor is turned off in a case where it is expressed. The resistor circuit is
A third transistor connected between the power supply node and the pad and turned on when the test mode signal indicates that the detection of the electrical connection is valid;
The semiconductor device according to claim 3, wherein a channel length of the third transistor is larger than a channel length of the first transistor.   The semiconductor device according to claim 1, wherein the semiconductor device and the other semiconductor device are mounted in the same package. The semiconductor device is a logic chip,
The semiconductor device according to claim 7, wherein the other semiconductor device is a memory chip. A first semiconductor chip;
A second semiconductor chip;
A conductor connected between the first semiconductor chip and the second semiconductor chip;
The first semiconductor chip is:
A first power supply node;
A ground node;
A first pad connected to the conductor;
A detection circuit for detecting a failure in electrical connection between the first semiconductor chip and the second semiconductor chip by the conductor;
The detection circuit includes:
The electrical connection between the first semiconductor chip and the second semiconductor chip, which is provided between the first power supply node and the first pad and is made of the conductor, is poor. A voltage generating circuit configured to apply a predetermined voltage to the first pad;
A switch circuit provided between the first power supply node and the ground node and configured to be turned on when the predetermined voltage is applied to the first pad by the voltage generation circuit. And a semiconductor device. The switch circuit is
A first transistor connected to the first power supply node and turned on and off in response to a test mode signal;
A second transistor connected between the first transistor and the ground node and having a gate coupled to the first pad;
When the test mode signal indicates that the detection of the electrical connection is valid, the first transistor is turned on, whereas the test mode signal indicates that the detection of the electrical connection is invalid. The semiconductor device according to claim 9, wherein the first transistor is turned off. The voltage generation circuit includes:
A resistor circuit connected between the first power supply node and the first pad;
The second semiconductor chip is
A second pad connected to the conductor;
A second power supply node;
And a diode connected between the second pad and the second power supply node so that a direction from the second pad to the second power supply node is a forward direction. 10. The semiconductor device according to 10. The resistor circuit is
A resistance element connected to the first power supply node;
A third transistor connected between the resistive element and the first pad;
If the test mode signal indicates that the detection of the electrical connection is valid, the third transistor is turned on, whereas the test mode signal indicates that the detection of the electrical connection is invalid. The semiconductor device according to claim 11, wherein the third transistor is turned off. The resistor circuit is
A third transistor and a fourth transistor connected in series between the first power supply node and the first pad, each being turned on and off in response to the test mode signal;
The first semiconductor chip is:
A signal generating circuit for generating a control signal for driving the third transistor based on the test mode signal when the test mode signal indicates that the detection of the electrical connection is valid; ,
The signal generation circuit generates the control signal such that a current smaller than a current flowing through the third transistor flows through the third transistor when the third transistor is fully turned on;
When the test mode signal indicates that the detection of the electrical connection is valid, the fourth PMOS transistor is turned on while the test mode signal disables the detection of the electrical connection. The semiconductor device according to claim 11, wherein the fourth transistor is turned off in the case where The resistor circuit is
A third transistor connected between the first power supply node and the first pad and turned on when the test mode signal is valid;
The semiconductor device according to claim 11, wherein a channel length of the second PMOS transistor is larger than a channel length of the first transistor.   The semiconductor device according to claim 9, wherein the first and second semiconductor chips are mounted in the same package. The first semiconductor chip is a logic chip;
The semiconductor device according to claim 15, wherein the second semiconductor chip is a memory chip.

Images