JP2006194676A - Semiconductor device and its inspection method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and its inspection method capable of inspecting efficiently and surely under nearly normal use conditions and, once when judged as defective goods, recognizing easily those as defective goods afetrward. <P>SOLUTION: Nonvolatile switch sections NSW1, NSW2, and NSW3 are arranged between a plurality of internal terminals PD1, PD2, and PD3 of the semiconductor device 10 and a power wire 7, respectively. According to the present formation, even when connecting means W1, W2, and W3 are connected in parallel between the power wire 7 and a power wiring 1 on an inspection substrate, breaking of each connecting means W1, W2, and W3 can be inspected separately. On the other hand, by setting all nonvolatile switch sections to open form, the semiconductor device can be shifted to an inoperable state completely. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device including a semiconductor integrated circuit and an inspection method thereof, and more particularly to a semiconductor device including a plurality of power supply terminals and ground terminals and an inspection method thereof.

  In recent years, semiconductor devices sealed in various packages have been widely used. In such a semiconductor device, one or a plurality of semiconductor substrates (hereinafter referred to as semiconductor chips) on which a semiconductor circuit is formed are sealed in a package, and the semiconductor chip is connected via a plurality of external terminals provided on the outer surface of the package. In addition, power supply and signal input / output are performed.

  The internal terminal on the semiconductor chip and the external terminal are electrically connected by a connecting member. As such connection members, bonding wires (hereinafter referred to as wires), bumps, and the like are known.

  However, an abnormal connection state may occur at the connection portion between the connection member and the internal terminal or between the connection member and the external terminal, for example, the adhesive force is reduced. In this case, the connection member may be disconnected from the internal terminal or the external terminal due to mechanical vibration when the semiconductor chip is sealed in the package, and the internal terminal and the external terminal may be electrically disconnected. When the package is a resin mold package, the stress applied to the wire when the periphery of the connection member is filled with resin such as plastic is also a factor of disconnection.

  When such a disconnection of the connecting member occurs, it becomes impossible to exchange power and signals between the external terminal and the internal terminal, so that the semiconductor chip cannot perform normal operation. Therefore, the semiconductor device in which the disconnection of the connection member has occurred needs to be reliably detected as a defective product in the inspection performed after the package is sealed.

  FIG. 8 illustrates a general flow of the inspection. In the example of FIG. 8, first, a connection inspection (in FIG. 8) is performed to inspect whether or not the connection state between an internal terminal and an external terminal of a semiconductor device to be inspected (hereinafter referred to as a DUT (Device Under Test)) is normal. 8 S1) is performed. Next, as a result of the connection inspection, a DC inspection is performed to apply a direct current voltage or direct current to the DUT determined to be non-defective and inspect whether or not the elements on the semiconductor chip are normally formed ( FIG. 8 S2 Yes → S3).

  Subsequently, a power supply and a signal during normal use are input to the DUT that is determined to be non-defective in the DC inspection, and a function inspection is performed to inspect whether the DUT functions normally (FIG. 8, S4 Yes → S5). ). Only the DUTs that are determined to be non-defective items in all the inspection items are finally determined to be non-defective items (FIG. 8, S6 Yes → S7).

  In addition, from the viewpoint of minimizing the inspection time and the inspection cost, the DUT determined as a defective product in each inspection usually ends the inspection when it is determined as a defective product, and the subsequent inspection is not executed (see FIG. 8 S2No → S9, S4No → S9, S6No → S9). From the same point of view, it is preferable that the number of times the DUT is handled is minimum, and each of the above inspections is performed as a series of measurements on an inspection board capable of performing a functional inspection.

  By the way, in recent semiconductor devices, in order to cope with an increase in operating frequency, it is necessary to reduce the impedance (hereinafter referred to as parasitic impedance) of portions other than the semiconductor chip. In order to reduce the parasitic impedance in the high frequency region, it is particularly necessary to reduce the inductance component. For this reason, a package having a relatively small inductance (lead inductance) of an external terminal, such as a CSP (Chip Sized Pakage), is adopted as the package of such a semiconductor device.

  In addition to using a package with a small lead inductance, in order to further reduce the inductance, a plurality of internal terminals are provided for one power supply line (including a ground line to which a ground potential is supplied) on the semiconductor chip. A method is also employed in which each internal terminal is connected to a different external terminal, and these external terminals are shared on the mounting board. According to this method, the power supply line on the semiconductor chip and the power supply wiring on the mounting substrate are connected in parallel by the external terminal and the connection member, and the parasitic inductance can be reduced.

  Furthermore, providing a plurality of internal terminals for the power supply line has a favorable effect from the viewpoint of noise resistance. In recent years, with the high integration of semiconductor circuits, the interval between adjacent wirings on a semiconductor chip is narrowed, and noise is likely to occur in power supply lines due to circuit operation. In this case, if a structure in which the same potential is supplied from a plurality of terminals is adopted, the noise resistance of the power supply line can be improved.

  However, when the above-described inspection is performed on a semiconductor device in which a plurality of internal terminals are formed for one power supply line on a semiconductor chip, the following problems occur.

  FIG. 9 is a schematic configuration diagram when a semiconductor device in which a plurality of internal terminals are formed with respect to a power supply line and a ground line is used as a DUT. In FIG. 9, the description of terminals and wirings that are not involved in the power supply line and the ground line is omitted.

  As shown in FIG. 9, the DUT 100 has a structure in which a semiconductor chip 106 is sealed in a package 104. The semiconductor chip 106 includes a power line 7 to which a predetermined potential is applied and a ground line 8 to which a ground potential is applied, and a digital that realizes the function of the DUT 100 between the power line 7 and the ground line 8. A circuit group 5 such as a circuit or an analog circuit is formed. Here, the circuit group 5 is operated by the power supplied from the power line 7 and the ground line 8.

  In the example of FIG. 9, the power supply line 7 branches into three branch power supply lines 7a, 7b, and 7c, and is connected to pads PD1, PD2, and PD3, which are internal terminals, respectively. Similarly, the ground line 8 branches into three branch ground lines 8a, 8b, and 8c, and is connected to pads PD4, PD5, and PD6, which are internal terminals, respectively.

  On the other hand, the package 104 includes a plurality of external terminals L1 to L6, and the external terminals L1, L2, and L3 are respectively connected to the pads PD1, PD2, and PD3 through the wires W1, W2, and W3 (here, the wires W1) (Disconnection occurs). Similarly, the external terminals L4, L5, and L6 are connected to the pads PD4, PD5, and PD6 via wires W4, W5, and W6, respectively.

  Further, as described above, the wiring on the inspection board corresponding to the external terminals L1 to L3 is shared as the board-side power supply wiring 1, and the wiring on the inspection board corresponding to the external terminals L4 to L6 is also on the board side. The ground wiring 2 is shared.

  Furthermore, the anode sides of surge protection diodes D1, D2, and D3 are connected to the branch power supply lines 7a to 7c, respectively. Here, the ground potential is applied to the cathode side of the diodes D1 to D3 via an external terminal (not shown) and wiring on the inspection board. The substrate-side power supply wiring 1 is connected to a voltage source 31 and an inspection device 3 including an ammeter 32 that measures a current flowing through the voltage source 31.

  Now, as shown in FIG. 9, when the wire W1 is disconnected, it is easy to detect the disconnection if it is not necessary to detect the disconnection in a state where the DUT 100 is disposed on the inspection board capable of performing the function inspection. It can be carried out. For example, when a potential difference at which a forward current starts flowing in the diode D1 is applied between the lead L1 and the cathode of the diode D1, the wire W1 is disconnected if no current flows.

  However, when the DUT 100 is arranged on an inspection board capable of performing a function inspection, the external terminals L1, L2, and L3 are shared by the board-side power supply wiring 1. For this reason, even if the wire W1 is disconnected, the substrate-side power supply wiring 1 and the power supply line 7 are electrically connected via the wires W2 and W3. Therefore, when a potential (for example, −0.8 V) at which the forward current starts flowing to the diodes D1 to D3 is applied to the substrate-side power supply wiring 1 by the voltage source 31, the forward current Ia of the diode D1 is It flows to the inspection apparatus 3 through the power supply lines 7b and 7c. That is, the current I flowing through the ammeter 32 is always the sum of the forward currents Ia, Ib, and Ic flowing through the diodes D1 to D3 unless all the wires W1 to W3 are disconnected. For this reason, it is impossible to detect the disconnection of the wire W1 in a state where the DUT 100 is disposed on the above-described inspection board. For the same reason, it is impossible to detect the disconnection of the wires W4 to W6 on the ground line 8 side of the DUT 100 arranged on the inspection board.

  As a countermeasure against this, in Patent Document 1 described later, a semiconductor chip is connected between the power supply line 7 and a plurality of internal terminals connected to the power supply line 7 and to the ground line 8 and the ground line 8. A configuration has been proposed in which a switch portion is provided between each of the plurality of internal terminals and the power supply line 7 and the ground line 8 are connected via the switch portion.

  FIG. 10 is a schematic configuration diagram of the related art. In addition, the same code | symbol is attached | subjected to the site | part which has the same effect | action and effect as the block diagram shown in FIG.

  As shown in FIG. 10, in the prior art disclosed in Patent Document 1, the pads PD1, PD2, and PD3 of the DUT 110 are connected to the power supply line 7 via the switch units SW1, SW2, and SW3, respectively. The pads PD4, PD5, and PD6 are connected to the ground line 8 through the switch units SW4, SW5, and SW6, respectively. Further, the power supply line 7 and the ground line 8 are connected via the switch unit SWT.

  In addition, the DUT 110 includes a test control circuit 9 on the semiconductor chip 116 that controls opening and closing of the switch units SW1 to SW6 and SWT. Other configurations are the same as those of the DUT 100 shown in FIG. In the following description, it is assumed that the inspection apparatus 3 inputs a control signal for instructing switching of the switch units SW1 to SW6 and SWT to the inspection control circuit 9 via an interface (not shown).

  In the DUT 110 illustrated in FIG. 10, in the above-described connection inspection, the inspection control circuit 9 first closes the switch units SW1, SW4, and SWT (conduction state) based on the control signal input from the inspection device 3. In addition, the switch units SW2, SW3, SW5, and SW6 are opened (disconnected state). In this state, the inspection device 3 applies a predetermined potential to the substrate-side power supply wiring 1 by the voltage source 31.

  At this time, if the wires W1 and W4 are normally connected, the ammeter 32 is connected to the substrate-side power supply wiring 1, the external terminal L1, the wire W1, the pad PD1, and the switch as shown by a two-dot chain arrow in FIG. The current I flowing through the path of the part SW1, the power line 7, the switch part SWT, the ground line 8, the switch part SW4, the pad PD4, the wire W4, the external terminal L4, and the substrate side ground wiring 2 is detected.

  When this current I is detected, the inspection device 3 instructs the inspection control circuit 9 to switch each switch unit for connection inspection of other wires. Here, the inspection control circuit 9 closes the switch units SW2, SW5, and SWT and opens the switch units SW1, SW3, SW4, and SW6. In this state, the inspection apparatus 3 applies a predetermined potential (for example, several mV) to the substrate-side power supply wiring 1 from the voltage source 31.

  At this time, when the ammeter 32 detects a current, the inspection device 3 inputs a control signal to the inspection control circuit 9, closes the switch units SW3, SW6, and SWT, and switches the switch units SW1, SW2, SW4, Open SW5. Then, the inspection device 3 applies a predetermined potential (for example, several mV) to the substrate-side power supply wiring 1 by the voltage source 31.

  When the ammeter 32 detects a current in this state, the wires W1 to W6 of the DUT 110 are normally connected from the above results. On the other hand, if no current is detected by the ammeter 32 in any of the above states, it can be determined that one or both of the corresponding wires are disconnected.

  By the way, in the inspection process, the inspection data acquired for determining a non-defective product (defective product) is usually useful data for grasping the state of the manufacturing process. For example, in the above-described example, it is possible to identify a manufacturing process in which an abnormality has occurred by aggregating the defect occurrence rates in various measurements carried out in connection inspection, DC inspection, and function inspection. is there.

Further, by investigating and analyzing a semiconductor device determined to be a defective product, information such as a manufacturing process and a manufacturing capability can be obtained. For this reason, semiconductor devices determined as defective products are strictly separated and managed so as not to be obtained by a third party.
JP 2001-296336 A

  In the technology disclosed in Patent Document 1, a plurality of internal terminals shared by power supply lines on a semiconductor chip and a plurality of external terminals shared by power supply wirings on a test substrate are respectively connected by connecting members. Even under the condition of being connected in parallel, the disconnection of each connecting member can be detected. For this reason, it is possible to perform all the inspections shown in FIG. 8 with an inspection substrate in which peripheral circuits similar to the substrate on which the semiconductor device is mounted during normal use, which is very effective.

  However, in the above conventional technique, since the inspection control circuit 9 that controls the opening / closing operation of the switch section needs to be configured inside or outside the semiconductor device, the circuit configuration becomes complicated.

  Further, when the semiconductor device is normally used, as shown in FIG. 11, it is necessary to maintain the switch units SW1 to SW6 in the closed state and to maintain the switch unit SWT in the open state. For this reason, it is necessary to always supply power to the inspection control circuit 9, and there is a problem that power consumption increases and power noise is likely to occur.

  Furthermore, in the future, it is expected that the operating frequency of the semiconductor device will be higher and the degree of integration of the semiconductor device will be higher. As described above, since the semiconductor device is easily affected by noise as the degree of integration increases, it is not preferable to provide a circuit that generates power supply noise during normal use on the semiconductor chip, such as the inspection control circuit 9. .

  On the other hand, semiconductor devices that are determined to be defective in the inspection process are strictly separated and managed, but semiconductor devices that are determined to be defective due to unexpected factors are among the semiconductor devices that are determined to be good. The possibility of contamination is not zero. If a defective product is mixed, it is impossible to identify the defective product by its appearance, and it is necessary to re-inspect the semiconductor device again.

  At this time, if an inspection item determined as a defective product can be specified, it is possible to identify the defective product by performing re-inspection only on the inspection item. However, when it is impossible to specify the defective item of the mixed defective product, it is not possible to identify the defective product unless re-inspection is performed for all the inspection items, which requires a large number of man-hours.

  Furthermore, when a situation occurs in which a semiconductor device determined as a defective product flows out to some extent, it is possible to prevent a third party from electrically analyzing the defective product and obtaining information. This is not possible with conventional semiconductor devices.

  The present invention has been made in view of the above-described conventional problems, and an object of the present invention is to provide a semiconductor device and an inspection method thereof that can perform inspection efficiently and reliably in a state close to normal use. In another aspect, once a defective product is determined, it can be easily recognized as a defective product, and when the defective product is obtained by a third party, the third party An object of the present invention is to provide a semiconductor device and an inspection method thereof that can make it impossible to analyze the above.

  The present invention employs the following means in order to achieve the above object. First, the present invention is premised on a semiconductor device in which a semiconductor circuit, a power supply line for supplying power to the semiconductor circuit, and a plurality of internal terminals to which the power is applied are provided on a semiconductor substrate. The semiconductor device according to the present invention includes a switch unit that can selectively maintain a conductive state or a cut-off state without input of a control signal between the internal terminals and the power supply line. ing.

  According to the above configuration, for example, when the semiconductor element is determined to be defective in the inspection process, the power supply path to the semiconductor circuit can be cut off by switching the switch unit to the cut off state. Can be maintained. This blocking process makes the semiconductor device completely inoperable, so that it can be easily confirmed that the semiconductor device is defective. Further, even if a third party obtains a semiconductor device that has been subjected to a blocking process, it is possible to prevent electrical analysis.

  In addition, since the switch unit does not require a control circuit for maintaining a cut-off state (or a conductive state), it is possible to suppress an increase in chip area and suppress noise generation compared to the conventional case. And power consumption can be reduced.

  The semiconductor device may further include an external terminal that is electrically connected to each internal terminal and provided outside the semiconductor substrate, and the power is applied from the external terminal. Good. Here, the external terminal is, for example, a terminal (lead) of a package on which the semiconductor substrate is mounted, a terminal formed on another semiconductor substrate, or the like.

  According to this configuration, it is further determined for each internal terminal whether or not a disconnection has occurred in the connection between the internal terminal and the external terminal by appropriately switching between the conductive state and the cutoff state of the switch unit. Can be inspected.

  Furthermore, the semiconductor device may be configured to include a plurality of power supply lines that supply different power supplies to the semiconductor circuit via internal terminals. That is, when the semiconductor device includes a first power supply line to which the first power is supplied and a second power supply line to which the second power is supplied, the switch unit includes the first power supply. Are applied between each first internal electrode to which the power is applied and the first power supply line, and between each second internal electrode to which the second power is applied and the second power supply line. In this case, it goes without saying that one of the first and second power supply lines may be a ground line.

  As the switch unit, for example, a flash memory element can be adopted. Further, in the above-described semiconductor element, during normal use, each of the switch parts maintains a conductive state.

  On the other hand, from another viewpoint, the present invention can provide an inspection method suitable for the above-described semiconductor device. That is, the inspection method of the present invention inputs an inspection signal to a semiconductor device to be inspected, and determines whether the semiconductor device is a good product or a defective product based on the measured value measured at this time. If the result of the determination is a defective product, all the switch units included in the semiconductor device are switched to the shut-off state.

  In addition, at the start of the above-described inspection, an inspection signal is input without switching the connection state of the switch unit included in the semiconductor device to be inspected, and it is determined whether or not the semiconductor device has already been determined to be defective. Thus, it becomes possible to identify a defective product mixed in for some reason in a short time.

  According to the present invention, the plurality of internal terminals shared by the power supply lines on the semiconductor substrate and the plurality of external terminals shared by the power supply wiring on the inspection board are connected by the plurality of connection members, respectively. Even under circumstances, it is possible to reliably detect disconnection of each connecting member. Accordingly, it is possible to perform a series of inspections on the semiconductor device all on the inspection substrate that can realize a state close to normal use, and the inspections can be performed in a short time.

  In addition, since an inspection control circuit that is conventionally required to maintain the connection state of the switch section is unnecessary, it is not necessary to energize the control circuit during normal use. For this reason, it is possible to reduce the power consumption as compared with the prior art and to reduce the generation of noise.

  Furthermore, once a semiconductor device determined to be defective is mixed into a non-defective product, the defective product can be easily identified, and if the defective product is obtained by a third party. Even if it exists, it can prevent that the third party acquires the information of the failure factor.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described in detail with reference to the drawings. FIG. 1 is a schematic configuration diagram showing an embodiment of a semiconductor device and an inspection device to which the present invention is applied. Further, in the drawing, the same reference numerals are given to portions having the same operations and effects as those of the conventional configuration shown in FIG.

  As shown in FIG. 1, a DUT 10 according to the present invention includes a power line 7 (first power line) and a ground line 8 (second power line) on a semiconductor chip 6 in the same manner as the conventional DUT 110 described above. And a circuit group 5 including a digital circuit and an analog circuit constituting a semiconductor circuit is disposed between the power supply line 7 and the ground line 8.

  The power supply line 7 is branched into branch power supply lines 7a, 7b, and 7c, and pads PD1, PD2, and PD3 (first internal terminals) are provided at the ends of the branch power supply lines 7a, 7b, and 7c, respectively. Yes. The pads PD1, PD2, and PD3 are connected to leads L1, L2, and L3 (first external terminals) included in the package 6 as external terminals by wires W1, W2, and W3.

  Similarly, the ground line 8 is branched into branch ground lines 8a, 8b, and 8c, and pads PD4, PD5, and PD6 (second internal terminals) are provided at the ends of the branch ground lines 8a, 8b, and 8c, respectively. ing. The pads PD4, PD5, and PD6 are connected to leads L4, L5, and L6 (second external terminals) included in the package 6 as external terminals by wires W4, W5, and W6.

  Further, the wiring on the inspection board to which the leads L1 to L3 are connected is shared as the board-side power supply wiring 1, and the wiring on the inspection board to which the external terminals L4 to L6 are connected is also the board-side ground wiring 2 As common. The diodes D1, D2, and D3 whose anode side is connected to the branch power supply lines 7a to 7c are diodes for surge protection.

  In the semiconductor device according to the present invention, switch units NSW1 to NSW3 (first switch units) that can selectively maintain a conductive state or a cut-off state without input of a control signal are provided on the branch power supply lines 7a to 7c, respectively. ing. Similarly, the branch ground lines 8a to 8c are respectively provided with switch units NSW4 to NSW6 (second switch units) capable of selectively maintaining a conduction state or a cutoff state without input of a control signal.

  Note that a switch unit that can selectively maintain a conductive state or a cut-off state without input of a control signal is a switch that does not need to steadily apply a signal from the outside in order to maintain the conductive state or the cut-off state. means. Examples of such an element include a flash memory element. Hereinafter, the switch unit is referred to as a non-volatile switch unit.

  Here, the structure of the flash memory device will be briefly described. FIG. 2 is a schematic cross-sectional view of an N-channel flash memory device.

  As illustrated in FIG. 2, the N-channel type flash memory device includes a source region 41 and a drain region 42 made of an N-type impurity region at a predetermined interval on the surface portion of a P-type semiconductor substrate 40. In the present invention, a channel region 45 made of a predetermined N-type impurity region is provided between the source region 41 and the drain region 42 in order to obtain a normally-on type. On the surface of the semiconductor substrate 40 on the channel region 45, a floating electrode 43 made of a conductive film is provided via a first insulating film 46 (so-called tunnel insulating film) made of a thin film such as an oxide film. Further, a control electrode 44 made of a conductive film is provided on the floating electrode 43 through a second insulating film 47 having a thickness larger than that of the first insulating film 46. A source electrode 48 and a drain electrode 49 made of a conductive film are provided on the upper surfaces of the source region 41 and the drain region 42, respectively.

  2A, for example, the source electrode 48 has a ground potential, the drain electrode 49 has a high potential (eg, + 10V), and the control electrode 44 has a high potential (+ 10V). When applied, activated electrons (so-called hot electrons) are generated in the channel region 45 due to a potential difference between the drain electrode 49 and the source electrode 48. The activated electrons pass through the first insulating film 46 by the potential applied to the control electrode 44 and are taken into the floating electrode 43.

  In this state, when the application of the potential to all the electrodes is stopped, the electrons remain taken in the floating electrode 43, and the floating electrode 43 is charged to a negative potential. At this time, the channel region 45 is opened (blocked) by a potential generated by the potential of the floating electrode 43. In the following, the process of applying a potential for realizing the open state to each electrode in this way is referred to as a writing process.

  The writing process is not limited to the potential condition, and a potential difference in which activated electrons are generated is given between the drain electrode 49 and the source electrode 48, and between the channel region 45 and the control electrode 44, It is only necessary to provide a potential difference at which the activated electrons move to the floating electrode 43.

  On the other hand, in the flash memory device, as shown in FIG. 2B, for example, the source electrode 48 has a ground potential, the drain electrode 49 has a high potential (for example, + 10V), and the control electrode 44 has a low potential (for example, + 5V). Is applied, the electrons taken into the floating electrode 43 due to the potential difference between the drain electrode 49 and the control electrode 44 are extracted to the drain region 42 through the first insulating film 46.

  In this state, when the application of the potential to the drain electrode 49 and the control electrode 44 is stopped, the charge of the floating electrode 43 is removed. At this time, the channel region 45 is in a closed state (conductive state) because the potential is not generated. Hereinafter, the process of applying a potential for realizing the closed state to each electrode in this way is referred to as an erasing process.

  The erasing process is not limited to the potential condition, and electrons in the floating electrode 43 pass through the first insulating film 46 between the drain electrode 49 and / or the source electrode 48 and the control electrode 44. A potential difference that moves to the drain region 42 and / or the source region 41 may be given.

  In the flash memory element, the charged state and the uncharged state of the floating electrode 43 are maintained even after the application of the potential to each electrode is stopped, and thus the state of the channel region 45 is also maintained. In addition, the structure of the nonvolatile switch section is not limited to the structure of the flash memory element described above, and any structure can be adopted as long as the structure can provide an equivalent function. For example, it is possible to employ a flash memory device having a single layer electrode structure.

  In the above description, the N-channel type flash memory device is described. However, in the case of the P-channel type flash memory device, the conductivity types of the semiconductor regions shown in FIG. In this case, the potential applied to each electrode during the writing process and the erasing process has the opposite polarity. Accordingly, when applying a positive potential to each electrode in a P-channel flash memory device, a ground potential is applied to the source electrode and a high potential is applied to the drain electrode and the control electrode, contrary to the N-channel flash memory device. When applied, the erasing process is performed. In addition, a writing process is performed when a ground potential is applied to the source electrode, a high potential is applied to the drain electrode, and a low potential is applied to the control electrode.

  When the flash memory element shown in FIG. 2 is adopted as the nonvolatile switch parts NSW1 to NSW6 shown in FIG. 1, for example, the source electrode of the nonvolatile switch part NSW1 is connected to the power supply line 7, and the drain electrode is Connected to pad PD1. The control electrode is connected to a pad PD7 for applying a potential to the control electrode.

  Similarly, for the nonvolatile switch sections NSW2 and NSW3, the source electrodes of the nonvolatile switch sections NSW2 and NSW3 are connected to the power supply line 7, and the drain electrodes are connected to the pads PD2 and PD3. Further, the control electrode of the nonvolatile switch unit NSW2 is connected to the pad PD8, and the control electrode of the nonvolatile switch unit NSW3 is connected to the pad PD9.

  Similarly, for the nonvolatile switch sections NSW4 to NSW6 provided in the branch ground lines 8a to 8c, the drain electrodes of the nonvolatile switch sections NSW4, NSW5, and NSW6 are connected to the ground line 8, and the source electrode is the pad PD4. It is connected to PD5 and PD6. The control electrode of the nonvolatile switch unit NSW4 is connected to the pad PD10, the control electrode of the nonvolatile switch unit NSW5 is connected to the pad PD11, and the control electrode of the nonvolatile switch unit NSW6 is connected to the pad PD12.

  Further, in the semiconductor device according to the present invention, a pad PD13 directly connected to the power supply line 7 and a pad PD14 directly connected to the ground line 8 are provided.

  The pads PD7 to PD14 are connected to corresponding leads L7 to L14 by wires W7 to W14, respectively. In the example of FIG. 1, from the viewpoint of ease of manufacture, the nonvolatile switch sections NSW1 to NSW3 are configured by P-channel flash memory elements, and the nonvolatile switch sections NSW4 to NSW6 are configured by N-channel flash memory elements. However, it is not particularly limited to this configuration. All the non-volatile switch sections may be composed of the same type of flash memory device.

  Next, a procedure for inspecting the connection state of the wires W1 to W3 will be described with reference to FIG.

  First, the inspection apparatus 3 will be described. In addition to the voltage source 31 described above, the inspection device 3 includes voltage sources 21, 22, 23, and 24 that switch connection states of the nonvolatile switch units NSW <b> 1 to NSW <b> 3. Here, the output terminal of the voltage source 21 is connected to the substrate-side power supply wiring 1. The output terminal of the voltage source 22 is connected to the lead L7 via a wiring on the inspection board. Further, the output terminal of the voltage source 23 is connected to the lead L8 via the wiring on the inspection board, and the output terminal of the voltage source 24 is connected to the lead L9 via the wiring on the inspection board. The lead L13 is connected to the ground potential via a switch 25 that can be opened and closed by the inspection device 3.

  The inspection apparatus 3 first performs an erasing process on the nonvolatile switch unit NSW1 and a writing process on the nonvolatile switch units NSW2 and NSW3 for the connection inspection of the wire W1.

  At this time, the inspection apparatus 3 applies the non-volatile switch unit NSW1 to the pads PD1, PD2, PD3, PD7, PD8, PD9, and PD13 connected to the electrodes of the non-volatile switch units NSW1, NSW2, and NSW3. , NSW2 and NSW3 are applied with a potential that realizes the potential relationship of the electrodes in the writing process or the potential relationship of the electrodes in the erasing process with respect to the P-channel flash memory element described above.

  That is, the inspection apparatus 3 closes the switch 25 to apply a ground potential to the pad PD13, and drives the voltage source 21 to apply a high potential (for example, the pads PD1, PD2, PD3) to the substrate-side power supply wiring 1 (pads PD1, PD2, PD3). + 10V) is applied. In addition, the inspection apparatus 3 drives the voltage sources 22, 23, and 24 to apply a high potential (for example, + 10V) to the pad PD7 and apply a low potential (for example, + 5V) to the pad PD8 and the pad PD9.

  At this time, if the wires W1 to W3 are normally connected, the nonvolatile switch unit NSW1 is in a conductive state, and the nonvolatile switch units NSW2 and 3 are in a cut-off state. Therefore, the substrate-side power supply wiring 1 and the power supply line 7 on the semiconductor chip 6 are connected only by the branch power supply line 7a provided with the nonvolatile switch portion NSW1.

  On the other hand, as shown in FIG. 3, when the wire W1 is disconnected, the potential of the voltage source 21 is not applied to the drain electrode of the nonvolatile switch unit NSW1, and therefore the erasing process of the nonvolatile switch unit NSW1 is not executed. However, the writing process of the non-volatile switch units NSW2 and NSW3 is normally executed, and the non-volatile switch units NSW2 and NSW3 are cut off. That is, when the wire W1 is disconnected, there is no path for electrically connecting the substrate-side power supply wiring 1 and the power supply line 7.

  Further, when the wire W2 is disconnected, the potential of the voltage source 21 is not applied to the drain electrode of the nonvolatile switch unit NSW2, so that the writing process of the nonvolatile switch unit NSW2 is not executed. However, since the erase process of the nonvolatile switch unit NSW1 and the write process of the nonvolatile switch unit NSW3 are executed, the nonvolatile switch unit NSW1 becomes conductive and the nonvolatile switch unit NSW3 enters a cutoff state. That is, even when the wire W2 is disconnected, the substrate-side power supply wiring 1 and the power supply line 7 are electrically connected via the branch power supply line 7a provided with the nonvolatile switch unit NSW1. become. Similarly, when the wire W3 is disconnected, the substrate-side power supply wiring 1 and the power supply line 7 are electrically connected via the branch power supply line 7a provided with the nonvolatile switch unit NSW1. Become.

  As described above, when the switch switching process for performing the connection inspection of the wire W1 is executed, the board-side power supply wiring 1 and the power supply line 7 are electrically connected unless the wire W1 is disconnected. It will be.

  Subsequently, after the inspection apparatus 3 stops the output of the voltage sources 21 to 24 and opens the switch 25, the inspection apparatus 3 drives the voltage source 31 to connect the diodes D 1 to D 3 to the board-side power supply wiring 1. A potential (for example, −0.8 V) is applied so that forward current starts to flow.

  At this time, if the connection of the wire W1 is normal, the potential is applied to the power supply line 7. Therefore, the forward currents Ia, Ib, and Ic flowing through the diodes D1 to D3 are supplied to the voltage source 31 through the wire W1. The ammeter 32 detects a current I (I = Ia + Ib + Ic). On the other hand, when the wire W1 is disconnected, the substrate-side power supply wiring 1 and the power supply line 7 are electrically separated, so that no current is detected by the ammeter 32.

  Therefore, whether or not the current is detected in the ammeter 32 when a potential that allows forward current to flow through the diodes D1 to D3 is applied to the substrate-side power supply wiring 1 after performing the switch switching process described above. Thus, the connection state of the wire W1 can be reliably inspected.

  When the inspection of the connection state of the wire W1 is completed, the inspection device 3 performs an erasing process on the nonvolatile switch unit NSW2 and a writing process on the nonvolatile switch units NSW1 and NSW3 for the connection inspection of the wire W2. I do.

  That is, the inspection apparatus 3 closes the switch 25 and applies a ground potential to the lead L13, and drives the voltage source 21 to apply a high potential (for example, the leads L1, L2, and L3) to the substrate side power supply wiring 1 (leads L1, L2, and L3). , + 10V). The inspection apparatus 3 drives the voltage sources 22, 23, and 24 to apply a high potential (for example, + 10V) to the lead L8 and apply a low potential (for example, + 5V) to the lead L7 and the lead L9.

  At this time, similarly to the description in the inspection of the wire W1, when the wire W2 is normally connected, the substrate-side power supply wiring 1 and the power supply line 7 are connected to the branch power supply in which the nonvolatile switch portion NSW2 is provided. When the wires 7b are electrically connected and the wire W2 is disconnected, the substrate-side power supply wiring 1 and the power supply line 7 are electrically separated.

  Therefore, after the inspection device 3 stops the output of the voltage sources 21 to 24 and opens the switch 25, the voltage source 31 is driven and the forward current flows through the diodes D 1 to D 3 in the substrate side power supply wiring 1. By applying a potential of the starting level, the wire W2 can be inspected for disconnection. That is, when a potential at which forward current flows through the diodes D1 to D3 is applied to the substrate-side power supply wiring 1, the wire W2 is reliably disconnected depending on whether or not the current is detected by the ammeter 32. Can be inspected.

  Subsequently, the inspection apparatus 3 performs a connection inspection of the wire W3. Since the same procedure is performed for the wire W3, the description thereof is omitted here.

  Similarly, as shown in FIG. 4, the output terminals of the voltage source 31 and the voltage source 21 are connected to the lead L14 directly connected to the ground line 8, and directly connected to the control electrodes of the nonvolatile switch sections NSW4 to NSW6. By connecting the output terminals of the voltage sources 22 to 24 to the leads L10 to L12, it is possible to reliably inspect the disconnection of the wires W4 to W6. Such a connection state change can be easily performed by connecting the inspection apparatus 3 and the inspection substrate via a connection switching means such as a matrix switch.

  In this case, since no diode for surge protection is connected to the branch ground lines 8a to 8c, only one of the nonvolatile switch sections NSW4, NSW5, and NSW6 is sequentially turned on, and the voltage source 31 is + A voltage of several mV (or −several mV) may be applied to the lead L14 to detect whether or not a current flows.

  In the inspection of the wires W1 to W3 on the power supply line 7 side, instead of detecting the forward currents of the diodes D1 to D3, an inspection method on the ground line 8 side may be employed. That is, only one of the nonvolatile switch sections NSW1 to NSW3 is sequentially turned on, and the voltage source 31 applies a potential of + several mV (or −several mV) to the substrate-side power supply wiring 1 so that current flows. Whether or not the wires W1 to W3 are broken can also be inspected. In this case, the switch 25 is in a closed state.

  As described above, the nonvolatile switch portions NSW1 to NSW3 are provided between the pads PD1 to PD3 and the power supply line 7, and the nonvolatile switch portions NSW4 to NSW6 are provided between the pads PD4 to PD6 and the ground line 8. Thus, the path through which the current from the voltage source 31 (or the voltage source 21) flows can be limited to only the wires to be inspected from the wires W1 to W3 and the wires W4 to W6 connected in parallel. For this reason, it is possible to test | inspect the disconnection of the wires W1-W6 separately.

  In the above description, in order to facilitate understanding of the present invention, the inspection device 3 uses the voltage sources 21 to 24 for switching the nonvolatile switch sections NSW1 to NSW6 and the currents flowing through the wires W1 to W6. The voltage source 31 to be measured is provided separately. However, the configuration of the inspection apparatus of the present invention is not limited to this configuration, and voltage sources that can be shared, such as the voltage source 31 and the voltage source 21, can be shared as appropriate.

  In the above description, the procedure for individually inspecting the disconnection of the wires W1 to W3 on the power supply line 7 side and the disconnection of the wires W4 to W6 on the ground line 8 side has been described, but the wires W1 to W3 on the power supply line 7 side are described. And the inspection of the wires W4 to W6 on the grounding wire 8 side may be performed in parallel.

  Further, in the above description, the case where the inspection apparatus 3 includes a voltage source and applies a potential to the lead L has been described. However, it goes without saying that a current source may be used as appropriate instead of the voltage source.

  In addition, as described above, the leads L13 and L14 are external terminals for switching the connection state of the nonvolatile switch unit. That is, the terminal is used only when the disconnection of the connecting member is inspected, and may be an open terminal during normal use. Therefore, the leads L13 and L14 do not hinder the function of the semiconductor device.

  In addition, the wires W7 to W14 may be disconnected as well as the wires W1 to W6. However, the disconnection of the wires W7 to W14 can be detected in the above-described connection inspection process by the following method. it can.

  First, the disconnection of the wire W13 can be inspected by detecting the current flowing through the lead L13 when performing the writing process or the erasing process on the nonvolatile switch sections NSW1 to NSW3. For example, during the switch switching process for the above-described connection inspection of the wire W1, if no current flows through the lead L13, the wire W13 is disconnected. The disconnection of the wire W14 can also be detected by the same method.

  Further, the disconnection of the wires W7 to W9 is inspected by detecting the current (leakage current) flowing through each of the leads L7 to L9 when performing write processing or erasure processing on the nonvolatile switch sections NSW1 to NSW3. be able to. For example, if there is a lead in which no current is detected during the switch switching process for the connection inspection of the wire W1, the corresponding wire is disconnected. The disconnection of the wires W10 to W12 can also be detected by the same method.

  When the connection inspection of all the wires W1 to W6 is completed by the above-described procedure and is determined to be a non-defective product, the DC inspection and the functional inspection are sequentially performed on the DUT 10 as in the conventional inspection procedure. . Only the DUT 10 that is determined to be non-defective in all inspections is finally determined to be non-defective.

  At this time, in the semiconductor device inspection method according to the present invention, in addition to the conventional inspection flow shown in FIG. FIG. 5 is a flowchart showing the procedure of the semiconductor device inspection method according to the present invention. In FIG. 5, steps that perform the same processing as in FIG. 8 are given the same reference numerals.

  In the method for inspecting a semiconductor device according to the present invention, as shown as step S10 in FIG. 5, when it is determined that the product is non-defective in the connection inspection (S1 → S2 Yes in FIG. 5), all the nonvolatile switch sections NSW1 provided in the DUT 10 A process for switching the .about.NSW 6 to the closed state is performed.

  At this time, for example, the inspection device 3 closes the switch 25 to apply the ground potential to the pad PD13 and drives the voltage source 21 to connect the substrate side power supply wiring 1 (pads PD1, PD2, PD3) to the high level. Apply potential. In addition, the inspection apparatus 3 drives the voltage sources 22, 23, and 24, and applies a high potential to the pads PD7, PD8, and PD9. As a result, the erasing process is executed on the nonvolatile switch sections NSW1 to NSW3 made of the P-type flash memory elements, and all are closed.

  Further, after changing the connection state between the inspection apparatus 3 and the DUT 10 to the connection state shown in FIG. 4, the same processing is performed on the ground wire 8 side. That is, the inspection apparatus 3 applies a high potential to the pad PD14 and applies a low potential to the pads PD10, PD11, and PD12. As a result, the erasing process is executed on each of the non-volatile switch sections NSW4 to NSW6 composed of the N-type flash memory elements, and all are closed.

  Here, since each of the nonvolatile switch sections NSW1 to NSW6 is kept closed unless a writing process is performed, the connection state of the nonvolatile switch sections NSW1 to NSW6 is maintained during the subsequent inspection and during normal operation. There is no need to supply power for this purpose. Therefore, since a control circuit for maintaining the cut-off state (or the conductive state) is unnecessary, an increase in the area of the semiconductor chip can be suppressed and generation of noise can be suppressed as compared with the conventional case. Furthermore, power consumption can be reduced.

  On the other hand, the DUT 10 determined to be defective in each inspection, including the DUT 10 determined to be defective in the connection inspection, is excluded from the inspection target at the time when it is determined to be defective as in the conventional case (FIG. 5, S2No → S9, S4No → S9, S6No → S9).

  In this case, in the method for inspecting a semiconductor device according to the present invention, as shown as step S11 in FIG. 5, a blocking process for switching all the nonvolatile switch sections NSW1 to NSW6 provided in the DUT 10 to the open state is performed. .

  Here, the inspection apparatus 3 applies a ground potential to the pad PD13 and also applies a high potential to the substrate-side power supply wiring 1 (pads PD1, PD2, PD3) in the connection state shown in FIG. Further, the inspection apparatus 3 applies a low potential to the pads PD7, PD8, and PD9. As a result, the write processing is executed in the nonvolatile switch sections NSW1 to NSW3, and all are opened.

  Further, after changing the connection state between the inspection device 3 and the DUT 10 to the connection state shown in FIG. 4, the inspection device 3 applies a high potential to the lead L14 and drives the voltage sources 22, 23, and 24. A high potential is applied to the pads PD10, PD11, and PD12. As a result, the writing process is executed in the nonvolatile switch sections NSW4 to NSW6, and all the switches are opened.

  For example, as shown in FIG. 6, the above-described blocking process connects the voltage source 22 to each of the leads L7 to L9, connects the voltage source 23 to the lead L14, and connects the voltage source 24 to each of the leads L10 to L12. Can be performed simultaneously for all of the nonvolatile switch sections NSW1 to NSW6.

  By performing the shut-off process as described above, the DUT 10 that is determined to be defective has a power supply path to the power line 7 and the ground line 8 regardless of which inspection item is determined to be defective. It is cut off and this cut off state is maintained.

  Therefore, once the semiconductor device is determined to be defective, the semiconductor device becomes completely inoperable by performing the blocking process. For this reason, even if a defective product is mixed into a non-defective product, for example, it can be easily confirmed that the product is defective by inputting an inspection signal without performing switching processing of the switch unit. Can do. Here, as the inspection signal, for example, a potential may be applied to the substrate-side power supply wiring 1 in order to operate the DUT 10 normally. In this case, no operating current flows in the DUT 10 that has been subjected to the blocking process. For this reason, it becomes possible to identify the defective product mixed in the non-defective product in an extremely short time compared with the conventional product.

  Further, as shown in step S12 in FIG. 7, if the inspection signal is input to the DUT 10 without performing the switching process of the switch unit at the beginning of the inspection process, defective products mixed in the uninspected product can be shortened. Can be identified by time. In this case, if the DUT 10 is an uninspected product, neither the writing process nor the erasing process is performed on the nonvolatile switch sections NSW1 to NSW6. The connection state is undefined. However, since it is extremely unlikely that all the nonvolatile switch sections NSW1 to NSW6 are in the cut-off state without performing the writing process, it is possible to identify defective products by inputting the inspection signal. .

  Furthermore, even if a semiconductor device that is determined to be defective flows out to the outside and the defective product is obtained by a third party, the third party is The characteristic cannot be acquired. For this reason, it is also possible to prevent a defective product from being analyzed and acquiring information such as a failure factor by a third party.

  In the above description, the power source line 7 and the ground line 8 of the semiconductor chip 6 have been described as having a plurality of internal terminals (pads). However, the present invention is not limited to this configuration. When either one of the power supply line 7 or the ground line 8 is connected to a single internal terminal, only the nonvolatile switch sections NSW1 to NSW3 or NSW4 to NSW6 are unnecessary. That is, if the ground line 8 side is a single internal terminal, the nonvolatile switch sections NSW4 to NSW6 are not necessary, and the ground line 8 and a single pad may be directly connected without going through the nonvolatile switch section.

  Further, during normal use, it is not necessary to input a control signal for switching the open state and the closed state of the nonvolatile switch sections NSW1 to NSW6. For this reason, as shown in FIG. 1, the pads PD7 to PD12 are input signals that do not affect the operation of the circuit group 5 when a potential for changing the connection state of the nonvolatile switch sections NSW1 to NSW6 is applied. It can also be used as a pad for use (for example, a pad to which a TTL signal or a clock signal is input). In this way, an increase in chip area can be suppressed.

  Furthermore, in the above description, the semiconductor chip is inspected for connection inspection of a semiconductor device sealed in a package having a lead as an external terminal. However, the present invention is naturally applicable to connection inspection for semiconductor devices having other structures. Is possible.

  For example, when the carrier on which the semiconductor chip is mounted and the semiconductor chip are connected by micro bumps such as C-CSP (ceramic CSP), it is applied to the inspection of the connection between the semiconductor chip and the carrier. Is possible. Or when a semiconductor chip and another semiconductor chip are connected, it is applicable to the connection inspection of both semiconductor chips. Furthermore, when the semiconductor chip and the printed board are directly connected, it can be applied to a connection inspection between the semiconductor chip and the printed board.

  Furthermore, in the above description, the case where the internal terminal and the external terminal are connected one to one has been described. However, the present invention can be applied even when a plurality of internal terminals are connected to a single external terminal by a plurality of connecting members. Such a configuration is a state in which the substrate-side power supply wiring 1 and the substrate-side ground wiring 2 are built in the package, and the operation and effect of the present invention are not impaired at all.

  The semiconductor device and its inspection method according to the present invention can realize measurement on an inspection board close to the LSI mounting state on the application, do not require various performances of the inspection device, and the time required for inspection is short, The disconnection of the power supply terminal and the ground terminal can be inspected at low cost, and it is useful as a semiconductor device used in information communication equipment, office electronic equipment, and the like, and an inspection method thereof.

The schematic block diagram which shows the semiconductor device and test | inspection apparatus to which this invention is applied. Sectional drawing which shows an example of the switch part of this invention. The schematic block diagram which shows the semiconductor device and test | inspection apparatus to which this invention is applied. The schematic block diagram which shows the semiconductor device and test | inspection apparatus to which this invention is applied. The flowchart which shows the inspection method of the semiconductor device of this invention. The schematic block diagram which shows the semiconductor device and test | inspection apparatus to which this invention is applied. The flowchart which shows the inspection method of the semiconductor device of this invention. The flowchart which shows the inspection method of the conventional semiconductor device. 1 is a schematic configuration diagram showing a conventional semiconductor device and an inspection device. 1 is a schematic configuration diagram showing a conventional semiconductor device and an inspection device. 1 is a schematic configuration diagram showing a conventional semiconductor device and an inspection device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Board | substrate side power supply wiring 2 Board | substrate side ground wiring 3 Inspection apparatus 4 Package 5 Circuit group 6 Semiconductor chip 7 Power supply line (1st power supply line)
8 Grounding wire (second power line)
10 DUT (semiconductor device)
L1 to L3 Lead (first external terminal)
L4 to L6 Lead (second external terminal)
NSW1 to NSW3 nonvolatile switch section (first switch section)
NSW4 to NSW6 non-volatile switch part (second switch part)
PD1 to PD3 pads (first internal terminals)
PD4 to PD6 pads (second internal terminals)
W1-W13 wire (connection member)

Claims (8)

In a semiconductor device in which a semiconductor circuit, a power supply line for supplying power to the semiconductor circuit, and a plurality of internal terminals to which the power is applied are provided on a semiconductor substrate,
A semiconductor device comprising a switch portion provided between each internal terminal and the power supply line and capable of selectively maintaining a conduction state or a cutoff state without input of a control signal.   The semiconductor device according to claim 1, further comprising an external terminal electrically connected to each internal terminal and provided outside the semiconductor substrate, wherein the power is applied from the external terminal. A semiconductor circuit; a first power line for supplying a first power to the semiconductor circuit; a power line for supplying a second power to the semiconductor circuit; and a plurality of firsts to which the first power is applied. And a plurality of second internal terminals to which the second power supply is applied are provided on a semiconductor substrate,
A first switch unit provided between each of the first internal terminals and the first power supply line and capable of selectively maintaining a conduction state or a cutoff state without input of a control signal;
A second switch unit provided between each of the second internal terminals and the second power supply line and capable of selectively maintaining a conductive state or a cut-off state without input of a control signal;
A semiconductor device comprising: A first external terminal provided outside the semiconductor substrate, electrically connected to the first internal terminals and to which the first power source is applied;
A second external terminal provided outside the semiconductor substrate, electrically connected to each second internal terminal and to which the second power supply is applied;
The semiconductor device according to claim 3, comprising:   The semiconductor device according to claim 1, wherein each of the switch units is a flash memory element.   The semiconductor device according to claim 1, wherein each of the switch portions maintains a conductive state during normal use. A method for inspecting a semiconductor device according to claim 1,
Inputting an inspection signal to a semiconductor device to be inspected;
Determining whether the semiconductor device is a non-defective product or a defective product based on a measurement value measured when the inspection signal is input; and
If the determination is a defective product, the step of switching all the switch parts to a shut-off state;
A method for inspecting a semiconductor device, comprising: 8. The method according to claim 7, further comprising a step of inputting an inspection signal without switching the switch unit included in the semiconductor device to be inspected at the start of inspection and determining whether or not the semiconductor device has already been determined to be defective. The inspection method of the semiconductor device as described.

Images