JPH07225258A - Semiconductor device - Google Patents

Abstract

PURPOSE:To discriminate a contact abnormality at every signal terminal by a method wherein the potential state of a signal terminal connected to a lead terminal is set at a potential for a test and the potential level of the signal terminal is measured relatively. CONSTITUTION:An MPX changeover signal in a normal mode is set in such a way that multiplexers 12a to 12n select connections of signal terminals 11a to 11n to I/O buffers 13a to 13n. The multiplexers 12a to 12n select a first potential. The first potential is output to the side of the terminals 11a to 11n from the side of a semiconductor chip 1. Then, lead terminals 11 to 1n are scanned by an electron-beam tester EB, and individual potential levels of the lead terminals 11 to 1n corresponding to the first potential are measured. In the same manner, potential levels of individual lead terminals corresponding to a second potential are measured, and both measured levels are compared with a criterion level which is output so as to correspond to both potentials. A compared result is recorded in a computer for the tester EB, and whether bonded parts are disconnected or short-circuited can be discriminated at the individual lead terminals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a test circuit that makes it easy to determine a disconnection or a short circuit in bonding a semiconductor chip, and more particularly, to a good or bad inner lead bonding of a tape carrier package and bonding in a multi-chip module. The present invention relates to a semiconductor device that facilitates the quality judgment of

[0002]

2. Description of the Related Art Conventionally, a semiconductor chip and a lead terminal of a package that houses the semiconductor chip are connected by a so-called wire bonding method, a tape automated bonding (TAB) method,
A flip chip method or the like is used. In these bonding methods, disconnection or short circuit of the bonding portion (for example, contact between adjacent terminals, circuit power supply Vdd, GN)
The presence or absence of (contact with D etc.) can be tested by applying a probe of a tester or an electron beam or a laser beam to a test point (bonding portion) and checking the potential difference and conduction.

However, when the semiconductor chip has a large number of pins and a narrow pitch, it is not easy to apply the probe of the tester to the wiring. If the semiconductor chip is not assembled on the tape carrier so that the tester's probe can be mechanically brought into contact with the semiconductor chip wiring or leads on the tape carrier, for example, the semiconductor chip is mounted on the tape carrier. In this state, if the tape (film) covers part or all of the surface of the semiconductor chip, it is not possible to directly test the quality of the bonding portion. It is also possible to use a socket that accommodates a tape carrier package and draws the wiring from the tape to the outside instead of the probe. However, when the semiconductor chip has a large number of pins at a narrow pitch, the socket is manufactured. Is difficult. In such a case, after mounting the semiconductor device on a substrate, various test pattern signals are given to the semiconductor device to determine whether or not a reference output pattern can be obtained and to estimate an abnormal portion of the semiconductor device. , Boundary scan test and so on.

For these reasons, it may not be possible to directly measure the disconnection or short circuit of the bonding such as the inner lead.

[0005]

However, unless the bonding failure of the semiconductor device is determined at the earliest possible stage, the cost loss after assembling the defective semiconductor device becomes large. Therefore, it is desirable to be able to test the disconnection and short circuit of the inner lead bonding in a tape carrier package state before mounting.

After mounting the semiconductor device on the substrate such as the multi-chip module, the wiring test of the substrate can be conducted by the boundary scan test as described above. However, when the wiring defect occurs, the boundary scan test is performed. Then, it is difficult to specifically specify whether the wiring of the substrate is defective, the contact between the semiconductor chip and the substrate is defective, or the semiconductor chip is defective.

Therefore, it is an object of the present invention to provide a semiconductor device having a built-in function for testing an open / short circuit between a semiconductor chip and a lead terminal.

[0008]

In order to achieve the above object, a semiconductor device of the present invention comprises a test potential generating means formed in a semiconductor chip to generate a test potential, and an internal portion formed in the semiconductor chip. A circuit, a signal terminal formed on the surface of the semiconductor chip and used for connection between an external lead terminal and the internal circuit, and the test potential generating means in response to the presence of a test command signal. Signal switching means connected to the terminal and connecting the internal circuit to the signal terminal in response to the absence of the test command signal.

[0009]

The semiconductor device itself has a function of setting the potential state of the signal terminal (pad) connected to the lead terminal to the test potential. The test potential level set in the signal terminal can be measured by a probe on the lead terminal or lead wire, or by a non-contact probe such as an electron beam.
Abnormality of the contact at each signal terminal is determined by relatively measuring and comparing with a reference value.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a first embodiment of the present invention. In the figure, a semiconductor (LSI) chip 1 is arranged in a device hole 3 of a film carrier tape 2,
Signal terminals 11a to 11n formed by pad electrodes
To inner lead terminals la to ln, respectively.
The other end of each inner lead terminal is connected to an outer lead (not shown). Each of the signal terminals 11a to 11n receives an I signal via a multiplexer (MPX) 12a to 12n, respectively.
It is connected to the O buffers 13a to 13n. The multiplexer is a 1: 3 (1 input, 3 outputs) bidirectional passage, and the signal terminal and any one of the first potential, the second potential and the IO buffer are responsive to the MPX switching signal. Connect selectively. The MPX switching signal, which is a test command signal, is given from an internal control circuit or CPU (not shown), but it can also be supplied from the outside via a signal terminal. Further, for example, the circuit power supply voltage Vdd can be used as the first potential, and the ground potential GND can be used as the second potential. I
The O buffers 13a to 13n are connected to an internal circuit (not shown) that performs signal processing via signal lines D1 to Dn to an internal circuit (not shown) of the LSI. Here, the multiplexers 12a to 12n which are the signal switching means and the circuit power supplies Vdd and GND which are the test potential generating means constitute a test circuit.

In such a configuration, the MPX switching signal in the normal mode has each multiplexer and a signal terminal
It is set to select the connection with the O-buffer.

The lead terminals l1 to ln and the signal terminal 11a
When performing a bonding state test with ~ 11b,
Multiplexers 12a to 12n according to the MPX switching signal
Then, the first potential or the first potential and the second potential are alternately selected, and the first potential or the first potential and the second potential are alternately output from the semiconductor chip 1 side to the signal terminal side. The lead terminals l1 to ln are scanned by an electron beam tester or a laser beam tester, and the potential level of each of the lead terminals l1 to ln corresponding to the first potential is measured. next,
Multiplexers 12a to 12n according to the MPX switching signal
The second potential or the first potential and the second potential are alternately selected to output the second potential or the first potential and the second potential alternately from the semiconductor chip 1 side to the signal terminals 11a to 11b. The lead terminals l1 to ln are scanned by an electron beam tester or a laser beam tester to measure the potential level of each of the lead terminals l1 to ln corresponding to the second potential. Of course, when the electron beam EB irradiates one lead, the potential supplied to the lead terminal may be switched to measure two potentials.

The measured levels of the two potential states at each lead terminal are compared with reference levels to be output corresponding to the first and second potentials. If the potential at the measurement point does not correspond to the first and second potentials,
For example, if the level does not change in response to the switching of the first and second potentials, disconnection or short circuit is considered. The measurement and comparison results are recorded in the tester's computer,
A disconnection or short circuit of the bonding portion is determined for each lead terminal.

Instead of irradiating the lead terminal with the electron beam EB, a tester probe (or probe group) is used.
Can be mechanically contacted with an inner lead, an outer lead, or a test pad connected to the outer lead to detect the potential level.

FIG. 2 shows a second embodiment, in which the portions corresponding to those in FIG. 1 are designated by the same reference numerals. In this embodiment, the signal terminals (pads) 11a to 11n of the semiconductor chip 1 and the lead terminals l1 to ln are connected to each other by bonding wires W1 to Wn. Further, the supply of the first and second potential levels described above is performed by, for example, the flip-flop 14 by a logic circuit.
a to 14n. In this embodiment, the boundary scan flip-flops provided in the semiconductor chip are utilized.

The signals input to the signal terminals 11a to 11n are supplied to the multiplexers 12a to 12n via the buffer amplifiers 12a to 12b, respectively. Outputs from the multiplexers 12a to 12n are buffer amplifiers 16a to 1
It is supplied to the signal output terminal via 6n. Each of the buffer amplifiers 16a to 16n has a gate function, and is activated in response to the supplied gate signal G. Each of the multiplexers 12a to 12n is a 2: 2 (2-input / 2-output) bidirectional passage, and in the normal operation mode, the signal lines D1 to Dn to the internal circuit of the semiconductor chip (not shown) are used.
And buffer amplifiers 15a to 15n or 16a to 1
6n is connected to switch the route of the input signal or the output signal in a time division manner. In the test mode, the output terminal of the flip-flop 14 and the buffer amplifier 16 are connected. Each of the multiplexers 12a to 12n has an MPX switching signal Ma to Mn supplied from a control circuit (not shown).
Controlled by. Multiplexers 12a to 12n,
Flip-flops 14a to 14n, buffer amplifier 16
a to 16n form a test circuit.

Next, the operation of this device will be described.
First, in the signal input state according to the circuit operation in the normal operation mode, the MPX switching signals Ma to Mn are supplied to the multiplexers 12a to 12n and the buffer amplifiers 15a to 15n.
n is connected to the signal lines D1 to Dn to the internal circuit, and the gate signals Ga to Gn turn off the buffer amplifiers 16a to 16n. Further, in the signal output state, the MPX switching signal M
a to Mn are connected to the multiplexers 12a to 12n, the buffer amplifiers 16a to 16n, and the signal lines D1 to D to the internal circuits.
The gate signals Ga to Gn turn on the buffer amplifiers 16a to 16n. As a result, each lead is connected to the wiring inside the semiconductor chip in the signal input state and the signal output state according to the circuit operation.

In the test mode, the gate signals Ga to Gn simultaneously turn on the buffer amplifiers 16a to 16n. The MPX switching signals Ma to Mn are supplied to the multiplexer 12
Buffer amplifiers 16a to 16n and flip-flops 14a to 14n are simultaneously connected to a to 12n, respectively. As a result, each lead is connected to the flip-flop inside the semiconductor chip. In such a state, the logic "0" signal and the logic "1" signal are alternately input to the flip-flop 14a. This signal propagates through the flip-flops 14a to 14n connected in series. The logical output of each flip-flop is led to each of the signal terminals 11a to 11n, and adjacent terminals of the signal output terminals generate complementary potential outputs.

An electron beam EB or a laser beam prober is applied to the lead by a tester (not shown) to measure the first potential of the lead. The measured potential is compared with the comparison reference potential. Next, a transmission clock for one data shift is applied to the flip-flop group, a potential state corresponding to another logic signal is formed in the lead, and the second potential is measured. This potential is compared with the comparison reference potential. From the comparison result of these signal levels, it becomes possible to determine the disconnection / short circuit in the signal path from the flip-flop to the measured lead terminal. Such measurement is repeated for each lead terminal.

It should be noted that, while the potentials of the lead terminals are alternately set to the first potential and the second potential, the EB tester scans each lead terminal to measure the potential, and the potential of each terminal is measured by the computer of the tester. Remember. After that, the potential of each lead terminal is switched, each lead terminal is scanned by the EB tester to measure the potential, and the potential of each terminal is stored in the computer of the tester. Then, it is possible to determine the quality of the wiring of the lead terminal by comparing each of the two measured potentials at each lead terminal with the comparison reference potential.

FIG. 3 shows that the present invention is applied to a semiconductor device mounted on a multi-chip module and the mutual test circuits are appropriately controlled so that not only inner lead bonding failure in the semiconductor device but also multi-chip module substrate. A third embodiment is shown in which it is possible to discriminate a bonding failure between the outer leads and the substrate wiring and a disconnection / short circuit of the wiring board line itself between the semiconductor devices.

In FIG. 3, semiconductor devices 4a and 4b are provided.
Although not shown in the drawing, is mounted on a multi-chip module substrate, and lead terminals of both devices are connected to each other via substrate wiring 22. Although only one set of lead terminals and wiring is shown in FIG. 3, there are a plurality of similar configurations. Each of the semiconductor devices 4a and 4b has a test circuit that enables the above-described bonding portion test. The operation of these test circuits is controlled by the test control circuit 21 mounted on the multichip module.

Next, an explanation will be given of the wiring defect discrimination test in the multi-chip module. First, the test control circuit 21 controls the multiplexers of the test circuits of both semiconductor devices to set the signal terminals of one semiconductor device to the test potential output state and the signal terminals of the other semiconductor device to the signal input state. . The potentials of the lead terminals of the semiconductor devices 4a and 4b respectively connected to both ends of the substrate wiring 22 are measured by using, for example, an electron beam tester or a prober, the potential state is changed, and the potential level is measured again. Next, reverse the input and output states of the signal terminals of both semiconductor devices,
Similarly, the potential is measured at each measurement point. From the result of each measurement, it is determined whether the signal terminal of any of the semiconductor devices or the wiring of any of the substrates causes a disconnection / short circuit. By performing such a measurement for each board wiring, it becomes possible to specifically specify the defective portion.

[0024]

As described above, the semiconductor device of the present invention has the built-in test circuit for supplying the test potential from the semiconductor device side to the signal terminal (pad electrode) of the semiconductor chip. It is possible to easily determine whether the bonding between the signal terminal and the signal terminal is good or bad by measuring the test potential output from the semiconductor chip side to the lead terminal.

When the semiconductor device of the present invention is mounted on a multi-chip module substrate, test potentials are alternately applied from both sides to a signal path connected to a test circuit built in the semiconductor device on both sides, and the signal is applied. Since it becomes possible to confirm disconnection / short circuit of wiring in the route, disconnection / short circuit of substrate wiring from one semiconductor chip to another semiconductor chip, defective bonding between semiconductor chip and lead terminal, lead terminal and substrate It is possible to easily determine a bonding failure or the like between the wirings.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a block circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a block circuit diagram showing a third embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 semiconductor chip 2 film carrier tape 4 semiconductor device 11a-11n signal terminal 12a-12n multiplexer 14a-14n flip-flop 15a-15n, 16a-16n buffer amplifier 21 test circuit 22 substrate wiring

Claims (2)

[Claims] 1. A test potential generating means formed in a semiconductor chip to generate a test potential, an internal circuit formed in the semiconductor chip, and an external lead terminal formed on a surface of the semiconductor chip. A signal terminal used for connection with the internal circuit, the test potential generating means connected to the signal terminal in response to the presence of a test command signal, and the internal circuit in response to the absence of the test command signal. A semiconductor device comprising: a signal switching unit that connects a circuit to the signal terminal. 2. The semiconductor device according to claim 1, wherein the test potential has two levels of high and low.