JP3624717B2 - Multichip module and test method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a multi-chip module (MCM) having a configuration for accurately performing tests such as standby current measurement, in-circuit test, and leak measurement necessary for detecting a faulty chip and checking for openness of a conductor wiring pattern. It relates to the test method.
[0002]
[Prior art]
The LSI or VLSI package includes a normal package having one chip. Semiconductor circuit devices connected by printed wiring using a plurality of normal packages have been known for a long time. In such a semiconductor circuit device using a normal package (hereinafter referred to as a normal package circuit), there is a problem that a signal delay due to a wiring distance between chips is large and an increase in speed is hindered.
In order to improve this, in recent years, development of a multi-chip module in which a thin film wiring layer is formed on a base substrate and a plurality of bare chips are connected to increase the density has rapidly progressed. The present invention relates to this multichip module. In a normal package circuit, a chip package to be used is usually a product that has been tested for the chip itself and is guaranteed to be non-defective. Therefore, testing of the chip itself, such as standby current measurement, is not usually required in a package circuit. On the other hand, in a multi-chip module, a bare chip to be mounted is generally not guaranteed for a good product. Therefore, for example, standby current measurement useful for determining the quality of a mounted bare chip is essential.
As described above, since the normal package circuit and the multi-chip module have different surfaces, the multi-chip module has a unique problem different from that of the normal package circuit. The prior art and its problems will be described in more detail below.
[0003]
Conventionally, in a normal package mounted on a printed circuit board, in an in-circuit test on the printed circuit board, a resistance element or the like has been added in order to perform component isolation (for example, JP-A-3-213000). .
In addition, in a conventional package mounted on a printed circuit board, a control signal is connected to a component under test from another component on the same substrate as a conventional technique improved so that the addition of the resistance element as described above is not required. In order to logically cut off this control signal, a method has been proposed for dealing with components under test that cannot be logically separated when they are present (for example, JP-A-9-159728). Publication).
[0004]
Compared to the normal package circuit, the multi-chip module is subjected to the same DC test and function test as the normal package circuit described above. Analyzes and identifies faulty chips. In general, a multi-chip module substrate has a power plane layer inside and supplies it to each bare chip as a common power source. Therefore, in the standby current measurement, the total current value of each bare chip is obtained, and good / bad determination is performed.
[0005]
[Problems to be solved by the invention]
In the conventional example of the normal package mounted on the printed circuit board (Japanese Patent Laid-Open No. 9-159728), as illustrated in FIG. 12, when power is supplied only from the power supply source P12, the package component PKG1, PKG2 becomes operable, and package parts PKG3 and PKG4 do not operate. Therefore, although physically connected, the package parts PKG3 and PKG4 are logically separated, so that the package parts PKG1 and PKG2 are not affected by the package parts PKG3 and PKG4 and are expected to use test data. Tests that compare values can be reliably implemented. The same operation as described above is performed when power is supplied only from the power supply source P34. However, as the standby current measurement values, two measurement values of the power supply source P12 and the power supply source P34 are obtained. When a failure value indicating failure is returned, each of the two power supply sources P12 and P34 has two values. Since power is supplied to the chip parts, it cannot be determined which chip part is defective. Subsequently, even if the insert kit test is performed, the usage test data does not have access to the failed part, such as insufficient failure detection rate and the input / output voltage levels (VIL, VIH, V0L, VOH) during the in-circuit test. In the case of a defect that does not affect the failure chip, it is not possible to specify a failed chip for the fail value detected by the standby current measurement.
[0006]
A normal package mounted on the printed circuit board is basically guaranteed to be non-defective. In other words, the purpose of performing the in-circuit test is mainly to detect mounting defects. In general, a test point is provided on a printed circuit board, and a prober dedicated to the package under test is used to perform an in-circuit test in a state where the package pins can be directly accessed. For this reason, a defective package can be detected directly. That is, here, DC measurement has no significant meaning.
[0007]
On the other hand, in the multi-chip module, the DC test is an important test item, unlike the normal package mounted on the printed board. The reason is
1. There is a case where a bare chip for which KGB (Knowed Good Die) is not guaranteed is mounted. For this reason, standby current measurement for detecting a bare chip internal failure with high probability is essential.
2. In addition to the demand for smaller packages, the number of bonding wires is generally large. For this reason, the possibility of a defect (open / short) of the wire portion is high. Therefore, it is necessary to detect resistive shorts between pins (measurement of input leakage and HIZ leakage) that cannot be detected by the function test.
[0008]
However, when the multi-chip module substrate wiring and measurement system are configured in a structure in which a plurality of chips use a single power supply as in the past, it is impossible to identify a failed chip only by measuring the standby current. In addition, the tester may not detect a failed multi-chip module in order to determine good / bad (PASS / FAIL) based on the total standby current value of a plurality of chips. The standby current measurement is to determine the failure of the CMOS device by measuring the leak value of the power supply / voltage without operating the input / output pins, the internal logic, and the memory at all locations.
FIG. 7 shows a conventional example in which standby current measurement is performed on two chip components C1 and C2 with one power supply source 5. If the PASS value of each chip component is 10 μA or less and the combined PASS value is 20 μA or less and the value obtained from the current measuring device 4 is 25 μA, a failure result is obtained, but the individual standby current of the chip C1 or C2 It is not possible to determine which chip is defective because it cannot be measured. Further, when the value obtained from the current measuring device 4 is 18 μA, it is determined that the multi-chip module is a non-defective product. However, when the standby current from the chip C1 is 2 μA and the standby current of the chip C2 is 16 μA, the chip C2 as a single chip. Is inferior because it exceeds 10 μA. However, since the stand-by current of each chip is not measured, this individual failure cannot be detected.
[0009]
Also, it is difficult to identify a defective part in the inter-pin resistive short inspection and the pin unit leak inspection of the net having a plurality of pins (pads) in the substrate of the multichip module.
The inter-pin resistive short inspection and the inter-pin single leak inspection are those in which a voltage is applied to the floating pins of the input buffer and the tri-state buffer and the leakage current is measured. At this time, a test pattern is applied to all remaining pins in order to detect inter-pin resistive shorts. The measurement of the leakage current is sequentially performed for each pin.
[0010]
FIG. 9 shows a conventional example of a multichip module in which a single power supply source 15 performs a leak test on a net having a plurality of pins. Leak measurement is performed in the order of pin number 12. At this time, if the outer lead (not shown) and the pin of the bare chip have a one-to-one correspondence, the fault pin becomes clear. However, when it is connected to the input pins 1 of the bare chips C1 and C2 as in the net 10, the failure pin cannot be specified. That is, if the PASS value of each net is 2 μA or less and the value obtained from the current measuring device 13 is 5 μA, a failure result is obtained, but it is not known which pin of the chip C1 or C2 is defective. The net 11 having a configuration in which the output from the output pin 2 of the chip C1 in the multichip module is input to the input pin 1 of the chip C2 in the multichip module is the same situation.
[0011]
In general, multi-chip modules require a large number of leads and test terminals, but it is sufficient if there is enough room to install test terminals, but if this is not enough, the design of the multi-chip module package may be changed. It becomes necessary. This leads to an increase in cost and package size.
[0012]
The present invention has been made to solve the above-described problems of the prior art in the testing of multichip modules.
That is, an object of the present invention is to obtain a multichip module having a structure capable of reliably specifying a faulty chip in a multichip module and specifying a location of a fault location.
It is another object of the present invention to obtain an outer lead structure that can secure a substantial number of terminals even when the number of outer leads is not sufficient.
It is another object of the present invention to provide a test method capable of individually judging pass / fail of each chip mounted on the multichip module.
[0013]
The present invention relates to a multichip module in which a plurality of bare chips are mounted on a substrate. At least two Supply means to supply power to the bare chip individually The power supply means has a lead frame having one lead connected to the power supply terminal of each bare chip and the other connected to the power input pin of the multichip module, and the power supply of two adjacent bare chips. Two lead wires from the terminal are opposed to each other with the insulating layer sandwiched at the terminal pin, and one electrically isolated pin is formed. It is characterized by this.
[0015]
[Action]
Main departure Tomorrow The multi-chip module has a configuration that provides supply means for supplying power separately to multiple bare chips mounted on the board. When testing this multi-chip module, the measurement system supports each bare chip. The power supply source to be connected can be connected to the bare chip individually, and power can be supplied only to the bare chip to be tested, so standby current measurement, leak measurement, in-circuit test and all other tests are affected by other chips Can be implemented without Further, since the measurement is performed with a bare chip alone, it is not necessary to consider the operation of the entire multichip module, and the test program and jig manufacturing time can be shortened. In various tests, it is possible to reliably identify a faulty chip in the multichip module and a fault location.
[0016]
If each bare chip has a separate power supply, the outer leads of the multichip module are required by the number of chips, and if there is not enough space to install them, Mysterious In this way, a plurality of leads are assembled together via an insulating layer with respect to one pin of the outer lead to constitute one pin, and the plurality of leads are connected to terminals of another bare chip, for example, the bare chip C3 of FIG. The power supply lead PN3 and the power supply lead PN4 of the bare chip C4 are wired to adjacent pad positions on the same side of the substrate K1 of the multichip module, and the lead frames are placed up and down with the insulator Z1 sandwiched between the same outer lead positions. By adopting such a structure, the number of pins can be reduced. When the multichip module is mounted on the motherboard used in the actual machine, the plurality of leads PN3 and PN4 are naturally short-circuited by the solder H1, so that there is no problem with the mounting reliability. Preferably, when the number of power supply sources is insufficient with respect to the total number of chips in the multichip module, a switch is provided in the measurement system, and one power supply is provided by sequentially switching the power supply destination and using the power supply. Tests according to the present invention are possible even if they have only the source. Further, since the configuration for switching the power supply is provided in the measurement system, the size of the multichip module can be prevented from being increased and the reliability can be prevented, and the measurement procedure can be simplified.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Ma Semiconductor integrated circuit with multichip module Example Will be described. FIG. 1 is a diagram showing an outline of the electrical wiring connection relationship of the multichip module, and FIG. 2 is a diagram showing an image of the power supply path of the multichip module and the in-substrate configuration of the multichip module. As shown in Figs. Example In the multichip module module M1, four bare chips C1 to C4 are mounted in a multichip module substrate K1 having a thin film multilayer wiring layer, and are connected with high density by the thin film multilayer wiring layer.
[0018]
All the conductor wiring patterns of the thin film wiring layer in the substrate K1 are connected to signal input / output pads provided in the periphery of the substrate K1, and each pad is connected to the outer lead R2 via the lead frame R1. The nodes N1 to N9 formed by the outer leads R2 are used for observing the operation state of the bare chip and the wiring when testing the multichip module. Nodes N1, N2, and N5 are nodes for signals only for input operations, nodes N3 and N4 are nodes for only signal output operations, and N6 to N9 are nodes having bidirectional attributes capable of inputting and outputting signals. At this time, the node having the bidirectional attribute, for example, N6 gives the bidirectional attribute by a combination of the output of the bare chip C1 and the input of the bare chip C3.
The power supply unit in the substrate K1 is individually provided for each chip as a power supply plane VP1 to VP4 or a power supply mesh on any thin film wiring layer. 1 and 22, the power supply path is drawn with a thick line, and the power supply portion of each chip is connected to an independent and separate pad so that power can be individually supplied to each chip. Is connected to the outer lead R2 via the lead frame R1 as in the case of the signal. In the test of the multichip module, the power supply sources P1 to P4 to each chip are connected to the outer lead R2 through independent paths PN1 to PN4, and further the power plane P1 through the lead frame R1 and the power pads of each bare chip. With the structure connected to VP4, it is possible to supply power independently to each bare chip.
[0019]
In the substrate K1, an independent power supply line is connected from the measurement system to the chip using a conductor wiring pattern dedicated to each chip, a power supply inner layer connection via hole, an inner layer divided region for power supply, and the like for the power supply source. Connect to the power pad.
According to this configuration example, the multi-chip module has a configuration in which supply means for individually supplying power to all bare chips on the multi-chip substrate is provided. In addition, the power supply source corresponding to each bare chip can be individually connected to the bare chip, and power can be supplied only to the bare chip to be tested, so standby current measurement, leak measurement, in-circuit test and all other tests It can be implemented without being affected by the chip. Further, since the measurement is performed with a bare chip alone, it is not necessary to consider the operation of the entire multichip module, and the test program and jig manufacturing time can be shortened. In various tests, it is possible to reliably identify a faulty chip in the multichip module and a fault location.
[0020]
Of the above configuration example The outer leads of the multichip module must be provided with as many power supply types as there are chips. At that time, the number of outer leads (number of pins) need only be enough to install the required number of power supplies, but if the number of pins is insufficient, the multichip module package must be changed. This leads to an increase in cost and package size.
In order to solve this problem, the embodiment of the present invention has a quad flat package (QFP) structure as shown in FIG. 3 and a structure of the outer lead. The power supply lead PN3 of the chip C3 and the power supply lead PN4 of the chip C4 are wired to adjacent pad positions on the same side of the substrate K1, and the respective leads are installed above and below the insulator Z1 at the same outer lead position. By adopting this lead frame configuration, two power supply pins are sufficient, and the number of pins of the multichip module is reduced. The power supply during the test is performed by using probes PB3 and PB4 on the top and bottom of the pin, respectively.
[0021]
When a multichip module is mounted on a motherboard used in an actual machine, the upper and lower leads PN3 and PN4 are naturally short-circuited by the solder H1, so that there is no problem with respect to mounting reliability.
In addition, the lead frame configuration can be used not only as a power supply pin but also as a general signal lead frame. In this case, since they become the same node when mounted on the substrate, logically, test pins that are not used in actual operation are generally targeted.
[0022]
In addition, Example The outer lead has a structure in which two leads are stacked one above the other through an insulator Z1, but the structure is changed to a structure in which a slit is cut in the longitudinal direction with respect to one outer lead and the insulator is sandwiched between the two. It can also be implemented. Further, as shown in FIG. 4, the four leads A, B, C, and D are put together through an insulator Z to form one outer lead, and the end portion of the outer lead can be bent to perform surface mounting. It can also be a structure. According to this structure, the outer lead for testing is the same as having four pins. On the other hand, when mounting, the four leads are electrically and mechanically connected to one outer lead by soldering. Become. Therefore, even when the outer lead installation space is not enough and the number of outer leads for individual power supply cannot be secured with normal outer leads, the above-mentioned outer lead structure makes it possible to provide individual power supply terminals for testing. It can be secured.
[0023]
Further, as shown in FIG. 5, a lead insertion type terminal structure may be adopted. In this case, the two leads A and B are overlapped with an insulator interposed therebetween, bent downward, and the tip is tapered to facilitate insertion into the wiring hole.
[0024]
(Test method for multi-chip module)
FIG. 4 is a flowchart showing an example of a procedure of a test method for a multi-chip module in which a multi-chip module package having a structure in which power can be individually supplied as shown in FIGS.
The bare chips C1, C2, C3, and C4 mounted on the multichip module are sequentially inspected one by one. Therefore, the power supply path is connected to the measurement power supply sources P1, P2, P3, and P4 for each bare chip independently of the remaining bare chips.
[0025]
First, a test start bare chip is set up (step S1). That is, the power supply source corresponding to one bare chip to be tested is turned on, and the power supply sources of the other test bare chips are turned off. For example, when the first chip to be tested is the chip C1, only the power supply source P1 connected exclusively for the chip C1 is activated, power is supplied from the power supply path PN1, and the test of the chip C1 is performed according to the procedure shown in FIG. The
Following the setup of the starting chip, a contact check is performed between the bare chip to be inspected and the measurement system (step S2). When the contact is normal, the static power consumption measurement of the bare chip to be inspected, so-called standby current measurement is performed (step S3). In the standby current measurement, as shown in FIG. 8, a voltage is applied from the voltage supply source 8 to the power supply part VDD1 or VDD2 of the chip C1 or C2, and thereby the current flowing to the chip is measured by the current measuring device 6. It is. The power consumption is calculated from the applied voltage and the measured current value.
[0026]
If the standby current is normal, the leak measurement is performed next (step S4). As shown in FIG. 10, the leakage current is measured by operating the switch 16 and the switch 17 to supply power to the bare chip to be tested, for example, C1 from an individual dedicated power supply source 18. Then, in a state where a test pattern for applying a voltage suitable for the function of each pin is applied to all the outer leads for signals of the bare chip under test to which power is supplied, a voltage (VIL) of a predetermined level is applied from the voltage source 21 to the pin. , VIH, VOL, VOH), and the resulting current is measured by the current measuring device 20. The measurement of the leakage current is sequentially performed for all the input pins 1 in the order of the bin number 12 of the pin 1. The items of the leak measurement test are items that can be measured by a commercially available LSI or board tester.
[0027]
If the standby current is not normal as a result of the standby current measurement in step S3, the subsequent test of the bare chip C1, that is, the leak measurement (step S4) and the in-circuit test (step S5) are not performed, and the next untested chip is not tested. Test preparation is performed (step S6). At this time, if the standby current is abnormally large, the test can be stopped, so that it is possible to prevent destruction due to the occurrence of abnormal current to the measurement system and the chip to be measured.
Next, if the measurement result indicates normal in the leak measurement (step S4), an in-circuit test (step S5) is performed. In the in-circuit test, test data is applied from an input pin, and the quality is determined by comparing the obtained output data with expected value data prepared in advance.
If there is a leak abnormality in the leak measurement, the in-circuit test S5 is not performed, and the next untested chip is prepared for testing (step S6).
If the in-circuit test passes, the chip C1 becomes a non-defective product, and the test is continued in order of the chip C2, the chip C3, and the chip C4.
[0028]
According to the embodiment of the test method of the present invention described above, in order to perform standby current measurement and leak measurement by applying power to each chip individually, a faulty chip is specified by using it together with an in-circuit test. Can do. It is not necessary to perform a failure analysis such as a destructive inspection as in the prior art for the identification. Therefore, the test time can be shortened.
Further, since it is sufficient to apply power to each chip and determine the failure of the chip, the test program for determining the failure is simplified, and the time for creating the program can be shortened. In addition, it is easy to detect multiple faults in which a plurality of chips are faulty.
Since power is not applied to other chips in a test of a certain chip, it is not necessary to be aware of chip control signals from other chips when determining a failure, and standardization of an in-circuit test method is facilitated.
Even in a signal line connected to a plurality of input / output pins of different chips, the signal is valid only for the chip under test, so that the leakage of the input / output pins of a specific chip can be measured.
[0029]
In the test method of the above embodiment, the measurement power supply sources P1, P2, P3, and P4 are installed corresponding to each of the four chips in the multichip module. FIG. 11 shows a configuration in which only one power supply source P1 can be installed for four chips. The power switch SW1 to SW4 corresponding to four chips are installed in the measurement system, and the switch groups SW1 to SW4 are switched to apply the power to the chip to be tested.
[0030]
【The invention's effect】
According to the present invention, the multichip module is The Since it has a configuration with supply means for supplying power separately to the chip, when testing this multichip module, connect the power supply source individually to the bare chip and supply power only to the bare chip to be tested In other words, the failure chip in the multichip module can be identified and the location of the failure location can be reliably determined. According to the present invention, since one outer lead has a structure that functions as a plurality of terminals at the time of testing, power and general signal input / output can be provided with a smaller number of outer leads, that is, the number of pins. it can.
[0031]
Main departure Clearly According to the multi-chip module under test, The Since there is a supply means for individually supplying power to the chip, and the power supply source can be individually connected to the bare chip, various necessary tests can be performed without being affected by other chips. Further, since the measurement is performed with a bare chip alone, it is not necessary to consider the operation of the entire multichip module, and the test program and jig manufacturing time can be shortened. Further, it is possible to reliably identify the defective chip in the multichip module and specify the position of the failed part.
[Brief description of the drawings]
[Figure 1] Ma The figure which shows the structure of the power supply individualization of a multi-chip module board | substrate.
[Figure 2] Ma The image figure which shows the power supply division | segmentation structure of a multichip module.
FIG. 3 is a diagram for explaining an example of a lead structure that bears two nodes with one lead (one pin);
FIG. 4 is a diagram showing an example of a surface mount type split lead structure that takes four nodes with one lead;
FIG. 5 is a diagram showing an example of a lead insertion type divided lead structure that takes two nodes with one lead; The figure which shows an example of the procedure of a test.
FIG. 6 is a flowchart showing an example of a procedure of a test method for a multichip module according to the present invention.
FIG. 7 is a diagram for explaining a standby current measurement of a conventional multichip module.
FIG. 8 is a diagram for explaining standby current measurement of the multichip module of the present invention;
FIG. 9 is a diagram for explaining measurement of a single net (pin) leakage current of a conventional multichip module.
FIG. 10 is a diagram for explaining measurement of a single net (pin) leakage current of the multichip module of the present invention.
FIG. 11 is a diagram for explaining a test method for a multi-chip module when the power supply source of the measurement system is smaller than the number of chips.
FIG. 12 is a diagram showing a conventional power source splitting configuration in a normal package mounted on a printed circuit board.
13 is an image diagram showing a power supply division structure in the conventional example of the normal package of FIG. 12;
[Explanation of symbols]
P1 to P4, P12, P34... Power supply source. M1 is a multi-chip module. M2 ... Printed circuit board.
PN1 to PN4, PN12, PN34... Path from the power supply source to the chip in the multichip module.
C1 to C4: Chips in the multichip module. N1 to N8: Input / output terminals and general signals in the substrate from the outside of each chip. K1 ... substrate. R1: Lead frame. R2: External lead. Z1 is an insulator. PB3, PB4 ... Power supply probes. H1 ... Solder,
DESCRIPTION OF SYMBOLS 1 ... Input pin, 2 ... Output pin, 3 ... Internal circuit, 4, 6, 7, 13, 20 ... Current measuring instrument, 5, 8, 9, 14, 15, 18, 19 ... Power supply source, 10, 11 ... Net, 12 ... Bin number, 16, 17 ... Switch.

Claims (1)

In a multi-chip module mounting a plurality of bare chips on a substrate, for at least two or more bare chips on a substrate, setting the supply means for supplying power individually,
The power supply means has a lead frame having one lead connected to the power supply terminal of each bare chip and the other connected to the power input pin of the multichip module, and from the power supply terminals of two adjacent bare chips. The multi-chip module has a configuration in which two lead wires are opposed to each other at the terminal pin with an insulating layer interposed therebetween to form one electrically isolated pin .

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