WO2001053845A1 - A printed circuit assembly with configurable boundary scan paths - Google Patents
A printed circuit assembly with configurable boundary scan paths Download PDFInfo
- Publication number
- WO2001053845A1 WO2001053845A1 PCT/US2001/000923 US0100923W WO0153845A1 WO 2001053845 A1 WO2001053845 A1 WO 2001053845A1 US 0100923 W US0100923 W US 0100923W WO 0153845 A1 WO0153845 A1 WO 0153845A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- test
- boundary scan
- printed circuit
- circuit assembly
- recited
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/281—Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
- G01R31/2815—Functional tests, e.g. boundary scans, using the normal I/O contacts
Definitions
- FIG. 3 The configuration shown includes two separate single scan paths, each with its own set of test signals (TDI and TDO) and control signals (TMS and TCK) These scan paths may be tested either sequentially or simultaneously
- Figure 1 is a block diagram of an exemplary integrated circuit configured for boundary scan testing
- ICT system 100 upon which a printed circuit assembly with configurable boundary scan paths is tested is shown
- ICT system 100 includes an instrument bay 101 and a test fixture 102
- a fixture interface 103 at the top of instrument bay 101 is configured to electrically couple test fixture 102 to instrument bay 101
- Test fixture 102 includes a plurality of test probes 104 configured to make electrical contact with test points located on printed circuit assembly 200
- Test probes 104 are electrically coupled to fixture interface 103 through fixture wires 105, which are typically arranged as twisted pairs
- a retainer 106 is configured to secure printed circuit assembly 200 m place during testing
- FIG. 8 is a block diagram illustrating an embodiment using switches to configure two parallel shared scan paths into a single scan path
- the embodiment shown mcludes a plurality of IC's 300 configured for boundary scan testing, each including a plurality of boundary scan cells 300, which are monitored through signal pms 320 during testing
- the two separate scan paths share a common TDI input and TDO output Switches 350S enable the two boundary scan paths to be electrically coupled, thus forming a smgle, common boundary scan path
- the separate TMS and TCK signals I e TMS1 and TMS2, TCK1 and TCK2
- test data may be shifted into the boundary scan path through common TDI signal path
- test data may then be shifted through the first path (upper path m the drawing) and then through the second path before exiting the chain through the common TDO signal path
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Tests Of Electronic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP01904832A EP1248953A1 (en) | 2000-01-21 | 2001-01-12 | A printed circuit assembly with configurable boundary scan paths |
AU2001232778A AU2001232778A1 (en) | 2000-01-21 | 2001-01-12 | A printed circuit assembly with configurable boundary scan paths |
KR1020027009124A KR20020087931A (en) | 2000-01-21 | 2001-01-12 | A printed circuit assembly with configurable boundary scan paths |
JP2001554079A JP2003520967A (en) | 2000-01-21 | 2001-01-12 | Printed circuit assembly with configurable boundary scan path |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US48906000A | 2000-01-21 | 2000-01-21 | |
US09/489,060 | 2000-01-21 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2001053845A1 true WO2001053845A1 (en) | 2001-07-26 |
Family
ID=23942238
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2001/000923 WO2001053845A1 (en) | 2000-01-21 | 2001-01-12 | A printed circuit assembly with configurable boundary scan paths |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP1248953A1 (en) |
JP (1) | JP2003520967A (en) |
KR (1) | KR20020087931A (en) |
AU (1) | AU2001232778A1 (en) |
WO (1) | WO2001053845A1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1326082A1 (en) * | 2001-12-27 | 2003-07-09 | Infineon Technologies AG | Integrated circuit with configurable scan path |
DE10238578B4 (en) * | 2001-09-04 | 2010-08-26 | Verigy (Singapore) Pte. Ltd. | Bandwidth adaptation for scan setups in an integrated circuit |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101222737B1 (en) * | 2010-09-27 | 2013-01-15 | 삼성전기주식회사 | Boundary scan testing apparatus for embedded-type substrate and method thereof |
WO2019120590A1 (en) | 2017-12-22 | 2019-06-27 | Lvmh Recherche | Oil-in-water emulsified cosmetic |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5581565A (en) * | 1993-12-01 | 1996-12-03 | U.S. Philips Corporation | Measuring apparatus used for testing connections between at least two subassemblies |
-
2001
- 2001-01-12 AU AU2001232778A patent/AU2001232778A1/en not_active Abandoned
- 2001-01-12 JP JP2001554079A patent/JP2003520967A/en active Pending
- 2001-01-12 KR KR1020027009124A patent/KR20020087931A/en not_active Application Discontinuation
- 2001-01-12 WO PCT/US2001/000923 patent/WO2001053845A1/en not_active Application Discontinuation
- 2001-01-12 EP EP01904832A patent/EP1248953A1/en not_active Withdrawn
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5581565A (en) * | 1993-12-01 | 1996-12-03 | U.S. Philips Corporation | Measuring apparatus used for testing connections between at least two subassemblies |
Non-Patent Citations (2)
Title |
---|
"SN54ACT8997, SN74ACT8997 SCAN PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES SCAN CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCENTRATORS", TEXAS INSTRUMENTS, DALLAS, TEXAS, December 1996 (1996-12-01), pages 1 - 24, XP002166813 * |
MOORE T J: "A WORKSTATION ENVIRONMENT FOR BOUNDARY SCAN INTERCONNECT TESTING", PROCEEDINGS OF THE INTERNATIONAL TEST CONFERENCE,US,NEW YORK, IEEE, 1991, pages 1096 - 1103, XP000272352, ISBN: 0-8186-9156-5 * |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10238578B4 (en) * | 2001-09-04 | 2010-08-26 | Verigy (Singapore) Pte. Ltd. | Bandwidth adaptation for scan setups in an integrated circuit |
EP1326082A1 (en) * | 2001-12-27 | 2003-07-09 | Infineon Technologies AG | Integrated circuit with configurable scan path |
Also Published As
Publication number | Publication date |
---|---|
EP1248953A1 (en) | 2002-10-16 |
KR20020087931A (en) | 2002-11-23 |
AU2001232778A1 (en) | 2001-07-31 |
JP2003520967A (en) | 2003-07-08 |
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