JPH07159483A - Integrated circuit device and its testing method - Google Patents

Abstract

PURPOSE:To inexpensively and easily perform connection tests on an integrated circuit device even when the number of pins increases. CONSTITUTION:Boundary scan cells are provided in corresponding to cascade- connected multiple boundary scan circuits 101,..., 109, scan-in terminal pads for setting data in the circuits 101,..., 10,, scan-out terminal pads for fetching the outputs of the circuits 101,...,109, input terminal pads 27a, 27c1, and 27c2 for inputting data, output terminal pads 27a, 27b1, and 27b2, and input buffers 12b, 161, and 162, which are provided in corresponding to the pads 27a, 27c2 and 27c2, and from which the data from the pads 27a, 27c1, and 27c2, to the inside are sent to the inside through the boundary scan cells. In addition, output buffers 12a, 141, and 142, which are provided in corresponding to the boundary scan cells and which send the data sent from the inside through the boundary scan cells to the pads 27a, 27b1, and 27b2 on the basis of operation controlling signals or which are controlled so that they can become high-impedance states are also provided.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a TAB (Tape Automated
The present invention relates to an integrated circuit device bonded by a bonding technology and a test method thereof.

With the increase in the number of pins in integrated circuit devices, TAB technology, which is more advantageous in increasing the number of pins than the conventional wire bonding technology, is drawing attention. The TAB technology mounts the integrated circuit chip on the leads of the metal foil formed in advance on the film of the TAB tape, and mounts the terminal pads of the integrated circuit chip and the TA
This is a technique of connecting the leads of the B tape, and since the pad pitch can be narrowed, it is suitable for increasing the number of pins.

In TAB, after mounting an integrated circuit chip on a tape, it is mounted on a package, the chip is resin-sealed (TCP: Tape Carrier Package) as it is, or the surface is mounted on an MCM (Multi Chip Module) or a printed circuit board. To be implemented.

Generally, the package, the MCM, and the printed circuit board are more expensive than the integrated circuit chip. Therefore, before they are mounted on the integrated circuit chip, the integrated circuit chip is defective, and the inner lead of the TAB tape is connected to the terminal pad of the integrated circuit chip. It is necessary to check defects and remove defective ones.

If a defect of the integrated circuit chip itself has already been checked by a wafer test, if the integrated circuit chip is mounted on the TAB tape, the TAB is mounted.
It is necessary to conduct a connection test between the inner lead of the tape and the terminal pad of the integrated circuit chip.

Conventionally, in the connection test between the inner lead of the TAB tape and the integrated circuit chip, the test pad connected to the outer lead of the TAB tape is contacted with a socket having a probe terminal, and the socket is connected to the test pad. It has been performed by connecting to an LSI tester through a DC test. For example, as shown in FIG. 5, inner leads of the TAB tape 50 (lead 5 of the TAB tape 50
2 of the side connected to the integrated circuit chip 1) and the integrated circuit chip 1 when performing a connection test, the test socket 6
This is performed by bringing each probe terminal 62 of No. 1 into contact with the test pad 54 of the TAB tape 50. By making such contact, the pad 2 of the integrated circuit chip 1 is
0, TAB tape 50 lead 52, TAB tape 50
Test pad 54, socket 61 probe terminal 6
2, the connection line 67, and the LSI tester 70 are connected. Then, the integrated circuit chip 1 that performs a DC test on each terminal of the integrated circuit chip 1 by the LSI tester 70
I / O buffer connected to each terminal of the
If the current characteristic is shown, the inner lead of the TAB tape 50 is normally connected to the integrated circuit chip 1. If the normal voltage-current characteristic is not shown, the inner lead of the TAB tape 50 and the integrated circuit chip 1 are normally connected. Check whether the probe terminal 62 and TAB of the test socket 61 are not connected.
Either the test pad 54 of the tape 50 is not in normal contact, or the input / output buffer connected to each terminal of the integrated circuit chip 1 is defective, and the inner lead of the TAB tape 50 and the integrated circuit are A connection test with the chip 1 can be performed.

[0007]

As described above, the conventional connection test method requires the socket 61 having the probe terminal 62. In addition, this socket has a problem that the pitch of the probe terminals has to be narrowed with the recent increase in the number of pins of the integrated circuit device, which makes it difficult to manufacture. However, it became expensive and had a practical problem.

Further, the probe terminal 6 of the test socket 61
2. The test pads 54 of the TAB tape 50 must all be normally brought into contact with the corresponding probe terminals 62, but with the recent increase in the number of pins of integrated circuit devices, all the terminals should be brought into normal contact. There was a problem that was becoming difficult.

The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide an integrated circuit device and a test method therefor that can easily perform a connection test at low cost even when the number of pins is increased. And

[0010]

An integrated circuit device according to the first invention comprises a boundary scan circuit in which a plurality of boundary scan cells are cascade-connected, and a scan-in terminal pad for setting data in the boundary scan circuit. , The scan-out terminal pad for taking out the output of the boundary scan circuit, the input terminal pad for inputting the data, the output terminal pad for outputting the data, and the input terminal pad provided corresponding to the input terminal pad, An input buffer that sends data from the terminal pad to the inside via the boundary scan cell, and a data that is provided from the inside via the boundary scan cell based on the operation control signal provided corresponding to the output terminal pad. To the output terminal pad or to control the high impedance state. Characterized in that it and an output buffer to be.

An integrated circuit device according to a second aspect of the present invention is the integrated circuit device of the first aspect, wherein an output-only terminal pad that does not serve as an input terminal pad among the output terminal pads is provided with this output-only terminal pad. An input-only terminal pad that does not double as an output terminal pad is provided with an input buffer that sends the output of the output buffer to the boundary scan cell in order to observe the output of the corresponding output buffer. Is provided with an output buffer that sends data from the boundary scan cell to the input buffer based on the operation control signal in order to set the data to be input to the input buffer provided corresponding to this input-only terminal pad. It is characterized by being.

In the integrated circuit device according to the third invention, when the integrated circuit device of the first invention is mounted on a TAB tape, the outer leads of the input terminal pads and the output terminal pads on the TAB tape are short-circuited. It is characterized in that it is connected to the wiring for.

The test method according to the fourth invention corresponds to the step of setting data in the boundary scan cell and one of the output terminal pads in the integrated circuit device of the third invention. Turning on only the output buffer based on the operation control signal, sending the data set to the corresponding boundary scan cell to the input terminal pad and the input buffer via the wiring for short circuit, and the data corresponding to the input buffer And a step of observing with a boundary scan cell.

In the integrated circuit device according to the fifth aspect of the invention, when the integrated circuit device of the second aspect of the invention is mounted on the TAB tape, the outer leads of the input terminal pads and the output terminal pads on the TAB tape are short-circuited. It is characterized in that it is connected to the wiring for.

The test method according to the sixth aspect of the invention is the fifth aspect.
After performing the test method of the fourth invention by using the integrated circuit device of the invention of the present invention, a step of separating the outer leads of the input terminal pad and the output terminal pad from the short-circuit wiring, The step of setting data in the boundary scan circuit so that the data of the boundary scan cell corresponding to the output buffer of the adjacent terminal pad is different, and turning on the output buffer based on the operation control signal, the corresponding data of the boundary scan cell is output. , A step of sending out to the boundary scan cell corresponding to the input buffer via the input buffer corresponding to the output buffer and observing at the boundary scan cell.

An integrated circuit device according to the seventh invention comprises a plurality of integrated circuit devices of the first invention or the second invention, T
When mounted on an AB tape, the boundary scan circuits of each integrated circuit device are serially connected on the TAB tape, and the input terminal pads and output terminal pads of each integrated circuit device are short-circuited for each integrated circuit device. It is characterized by being connected to wiring.

[0017]

According to the present invention, the boundary scan circuit is provided in the integrated circuit device, and the input terminal pad (including the bidirectional terminal pad) includes the input pad and the output terminal pad (including the bidirectional terminal pad). ) Is provided with an output buffer which is turned on / off based on an operation control signal.

When mounted on a TAB tape, the input terminal pad and the output terminal pad are short-circuited by the wiring for short-circuiting, but the output buffer can be turned on / off based on the operation control signal. For, it is possible to avoid output race conditions. Therefore, after data is set in the boundary scan cell (hereinafter, also referred to as scan cell) via the scan-in terminal, only the output buffer corresponding to one output terminal pad is turned on and the output buffer corresponding to the other output terminal pad is provided. Connects by turning off the output buffer, sending the data set to scan cell to the input terminal pad via the output buffer and the wiring for short circuit, and further observing at the scan cell corresponding to this input pad via the input pad. The test can be conducted.

Data observation is performed via the scan-out terminal pad. As described above, inputting test data to the boundary scan circuit via the scan-in terminal pad and observing the data output from the scan-out terminal pad will show the connection quality. Even when the number of contacts increases, it is not necessary to prepare a test socket (jig) according to the number of pins, and the connection test can be easily performed at low cost.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the integrated circuit device according to the first invention will be described with reference to FIGS. The integrated circuit device of this embodiment has an integrated circuit chip 1 mounted on a TAB tape 50 as shown in FIG. The integrated circuit chip 1 is provided therein with a boundary scan circuit in which boundary scan cells 10 ₁ , 10 ₂ , ... 10 ₉ are cascade-connected as shown in FIG. 1, and as shown in FIG. Power supply terminal pad 2 for driving power supply on the surface
1, a ground terminal pad 22 for grounding, a scan-in terminal pad 23 for scanning in, a scan-out terminal pad 24 for scanning out, a test clock terminal pad (not shown) for inputting a test clock, a test A test mode terminal pad (not shown) for inputting a mode signal and an input / output terminal pad 27 for inputting / outputting data are provided.

Further, each terminal pad on the integrated circuit chip 1 is connected to the TAB tape 5 via the lead 52 as shown in FIG.
0 to the corresponding terminal pad. The TA corresponding to the input / output terminal pad 27 of the integrated circuit chip 1
All the terminal pads 55 of the B tape 50 are short-circuited by the wiring 56, and the other terminal pads 54, that is, the power supply terminal pad 21, the ground terminal pad 22, the scan-in terminal pad 23, the scan-out terminal pad 24, the test clock terminal pad. The terminal pads 54 of the TAB tape 50, which correspond to the test mode terminal pads (not shown), are not connected to the wiring 56.

The input / output terminal pad 27 is, for example, as shown in FIG.
, The bidirectional terminal pad 27a, the output terminal pads 27b ₁ and 27b ₂ , and the input terminal pads 27c ₁ and
There is 27c ₂ . The bidirectional terminal pad 27a passes through the bidirectional buffers 12a and 12b and scan cells 10 ₂ and 10 ₂ .
₃ connected to the output terminal pads 27b ₁ and 27b ₂
Is a scan cell 1 via the output buffers 14 ₁ and 14 _2.
Input terminal pads 27 connected to 0 ₅ and 10 ₇ , respectively.
c ₁ and 27c ₂ are connected to scan cells 10 ₈ and 10 ₉ via input buffers 16 ₁ and 16 ₂ , respectively.

The bidirectional buffer 12a has a scan cell 10a.
It turns on or off based on the output data of ₁ , and enters the enable state or high impedance state. For example, the buffer 12a if the output signal 11 ₁ is "1" in the scan 10 ₁ is turned on, sends an output data of the scan 10 ₂ becomes an enable state to the bidirectional terminal pad 27a, the scan 10 ₁ Output signal 11 ₁
If is "0", the buffer 12a is turned off and enters a high impedance state.

The bidirectional buffer 12b has a bidirectional terminal 27a.
Sends the data inputted via the on scan 10 _3. The output buffer 14 ₁ is turned on or off based on the output signal 11 ₂ of the scan cell 10 ₄ to be in the enable state or the high impedance state. And when it becomes enabled and sends the output data of the scan ₁₀₅ to the output terminal pad 27b _1. Similarly, the output buffer 14 ₂ outputs the output signal 11 _{3 of the} scan cell 10 _6.
It is turned on or off based on the above, and becomes the enable state or the high impedance state. When it is in the enable state, the output data of the scan cell 10 ₇ is sent to the output terminal pad 27b ₂ . Input buffer 1
6 ₁ and 16 ₂ are input terminal pads 27c ₁ and 27c _{2 respectively.}
The data entered via the scan cells 10 ₈ and 10
Send to ₉ respectively. The bidirectional terminal pad 27a, the output terminal pads 27b ₁ and 27b ₂ , and the input terminal pads 27c ₁ and 27c ₂ are short-circuited by the wiring 56 via the lead 52 (see FIG. 2).

On the other hand, each scan cell has a known structure, for example, two multiplexers 101 and 10 as shown in FIG.
4 and two D-type flip-flops 102 and 103. In FIG. 6, the multiplexer 101 receives the input data IN or the shift-in input S sent from the scan cell of the previous stage based on the shift mode signal.
One of I is selected and sent to the flip-flop 102. The flip-flop 102 operates based on the shift clock signal, takes in the data sent from the multiplexer 101, and takes in the data taken in one cycle before,
The shift-out output SO is sent to the scan cell of the next stage and is sent to the flip-flop 103. The flip-flop 103 operates based on the update clock signal, takes in the output of the flip-flop 102,
And the data that was fetched one cycle before is multiplexer 1
Send to 04. The multiplexer 104 operates based on the mode signal, selects either the input data IN or the output of the flip-flop 103 and outputs the output data OUT.
And Therefore, for example, in the scan cell 10 ₂ , the input data IN is transmitted from the inside of the integrated circuit chip 1, the shift-in input SI is transmitted from the scan cell 10 ₁ , the scan-out SO is transmitted to the scan cell 10 ₃ , and the output OUT. Is sent to the buffer 12a. In the scan 10 ₃ input data IN is sent from the buffer 12b, the scan-in input SI is sent from the scan _102, the scan-out output SO
Is sent to scan 10 _4, the output OUT is sent to the interior of the integrated circuit chip 1.

The above shift mode signal, shift clock signal, update clock signal, and mode signal are generated by a TAP (Test Access Port) controller based on the test clock signal and the test mode signal. The TAP controller is provided in the integrated circuit chip 1, and the test clock signal and the test mode signal are input from the outside of the integrated circuit chip 1 via the test clock terminal pad and the test mode terminal pad, respectively.

Next, a test of the integrated circuit device of the present embodiment constructed as described above will be described.

Inner leads of the TAB tape 50 (see FIG. 2)
Then, when conducting a connection test between the integrated circuit chip 1 of the lead 52) and the integrated circuit chip 1, by setting data in the boundary scan cells 10 ₁ , 10 ₂ , ... 10 ₉ , the bidirectional buffer 12 a or the output buffer 1 is set.
One of 4 ₁ and 14 ₂ is enabled, the other bidirectional buffers or output buffers are all set to a high impedance state, and a test signal is input from the enabled buffer to input terminals 27c ₁ and 27c ₂ or bidirectional terminals. It is sent to the wire 12b through the wiring 56 for short circuit. By receiving and observing the transmitted signal with the boundary scan cell connected to the input buffer of the input terminal or bidirectional terminal, if the normal value is observed, the contact is normal and the abnormal value is observed. If so, it means that they are not in contact with each other or are short-circuited to the power supply, the ground or the like.

[0029] For example, when performing a connection test by sending a signal from the bidirectional pin 27a is the data "1" is first to scan 10 ₁ sets a data "0" to scan 10 _4, 10 ₆ to set the test data to scan 10 _2. These data are externally input in the scan path mode via the scan-in terminal 23. Next, after the data is set as described above, the update clock signal and the mode signal are sent to read the set data from the scan cells 10 ₁ , 10 ₂ , 10 ₄ , 10 ₆ . Then, since the data 11 ₂ and 11 ₃ read from the scan cells 10 ₄ and 10 ₆ are “0”, the buffers 14 ₁ and 14 ₂ are turned off and are in a high impedance state, but are sent from the scan cells 10 _1. The data 11 ₁ is “1”, the buffer 12a is turned on,
The enable state is set. This causes the scan cell 10 ₂
The data sent from the device is sent to the bidirectional terminal pad 27a via the buffer 12a, and the lead 52 and the wiring 5
6 and the input terminal pads 27c ₁ and 27c ₂ to the buffers 16 ₁ and 16 ₂ . Here, the scan mode signal and the shift clock signal are scanned 10
₈ and 10 ₉ , send the output data of the buffers 16 ₁ and 16 ₂ to scan cells 10 ₈ and 10 ₉ , respectively, and scan out the received data. By observing the data output from the scan-out terminal 24, the connection test of the terminals 27a, 27c ₁ and 27c ₂ can be performed. For example, scan cells 10 ₈ and 1
0 ₉ both receive a normal signal, that is, a signal having the same value as the test data set in the scan cell 10 ₂ , the terminals 27a, 27c ₁ ,
It shows that all of 27c ₂ are normally contacted. When an abnormal signal is received by both scan cells 10 ₈ and 10 ₉ , that is, when a signal having a value different from the test data set in scan cell 10 ₂ is received, the contact of terminal 27a is Abnormality, or abnormal contact between the _two input terminals 27c ₁ and 27c ₂ , or terminals 27a, 27c ₁ and 27c
All ₂ contacts are abnormal. Further, when only the scan cell 10 ₈ receives an abnormal signal, the contact of the terminal 27c ₁ is abnormal, and when only the scan cell 10 ₉ receives an abnormal signal, the terminal 27c ₂ of the terminal 27c ₂ . Indicates that the contact is abnormal. Similarly, the connection test can be performed on the terminals 27b ₁ and 27b ₂ .

As described above, according to this embodiment, the T corresponding to the input / output terminal pad 27 is used when the connection test is performed.
The terminals on the AB tape 50 do not have to come into contact with the probe terminals of the test socket, and even if the number of pins is increased, it is not necessary to narrow the pitch of the probe terminals of the test socket, and the pads of the TAB tape 50. It is not necessary that all 54 be in contact with the probe terminals. Thereby, the connection test can be easily performed at low cost.

In the above embodiment, all the pads 55 on the TAB tape 50 corresponding to the input / output terminal pads 27 were short-circuited by one wiring 56, but if the connection test can be performed, a plurality of pads 55 can be used. Pad 55 on the TAB tape corresponding to the input / output terminal pad by using individual wiring
May be short-circuited.

Further, in the above embodiment, the output buffer 14 _1, 14 ₂ of the enable signals 11 _2, 11 ₃ although respectively controlled in scan 10 _4, 10 _6, at scan 10 _4, 10 ₆ Instead of controlling, it may be controlled by a test mode signal input via a test mode terminal pad provided on the integrated circuit chip 1.

The TA connected to the short-circuit wiring 56
The terminal 55 of the B tape 50 is connected to the short circuit wiring 5 after the test.
6 is separated.

In the integrated circuit device of the first embodiment described above, a test as to whether the leads 52 of the TAB tape 50 and the input / output terminal pads 27 of the integrated circuit chip 1 are in contact with each other, a driving power supply or a ground power supply is performed. It is possible to test whether or not there is a short circuit, but it is not possible to detect whether or not the adjacent I / O terminal pads are short circuited.

The second embodiment of the integrated circuit device according to the present invention solves this problem as well. The second embodiment will be described with reference to FIG. Input terminal 27c with respect to the second embodiment of the integrated circuit device input terminal 27c with newly provided to the state observation scan 10 ₆ of the output terminal 27 to the output terminal 27b and an input buffer 14a
Output buffer 1 with an enable pin for setting the status of
6a and scan cells 10 ₇ and 10 ₈ for enabling and inputting the output buffer 16a are newly provided, and the other points are the same as in the first embodiment. Then, the input / output terminal pad 27 is attached to the TAB tape 50.
The wiring 56 (see FIG. 2) for short-circuiting via the lead 52 of is formed by a fuse (for example, a temperature fuse or the like), and the fuse 56 is cut after performing the contact test similar to that of the first embodiment. FIG. 3 shows a plan view of the second embodiment in the case where the short-circuit state is resolved by raising the temperature and cutting the fuse (for example, in the case of a thermal fuse).

[0036] In FIG. 3, the input buffer 14a is sent a signal from the output buffer 14 or the output terminal to scan _106, the output buffer 16a is scan 1
It is turned on or off based on the output signal 11 ₃ of 0 ₇ to be in the enable state or the high impedance state.
When the enable state is entered, the scan cell 10
The output data of ₈ is sent to the input buffer 16.

Next, a case where a short circuit test between adjacent terminals in the state shown in FIG. 3 is performed will be described. First, in order to turn on all of the output buffer 12a of the bidirectional terminal 27a, the output buffer 14 of the output terminal 27b, and the output buffer 16a of the input terminal, connect to the enable of each output buffer 12a, 14 and 16a. Data “1” is set in each of the scan cells 10 ₁ , 10 ₄ , and 10 ₇ , and each output buffer 1
Data of "0" and data of "1" are alternately set in scan cells 10 ₂ , 10 ₅ and 10 ₈ connected to 2a, 14 and 16a so that adjacent terminals do not have the same data. To do. For example, if the scan cell 10 ₂ is set to data “0”, the scan cell 10 ₅ is set to data “1” and the scan cell 10 ₈ is set to data “0”. When the data is set in this manner, the output buffers 12a, 14 and 16a are turned on, and the data set in the scan cells 10 ₂ , 10 ₅ and 10 ₈ pass through the output buffers 12a, 14 and 16a. To the input buffers 12b, 14a, and 16 respectively,
Further sent to the scan cells 10 ₃ , 10 ₆ and 10 ₉ . And these data scan cells 10 ₃ , 1
Observed at 0 ₆ and 10 ₉ and if the same data as set is observed, it means that there is no short-circuit with the adjacent terminal, and if different data is observed, it is short-circuited.

As described above, the integrated circuit device of the second embodiment has the same effect as that of the first embodiment, and it is possible to test whether or not adjacent terminals are short-circuited.

Although the enable signal of the output buffer is controlled by the scan cell in the second embodiment, it may be controlled by the test mode signal.

Further, in this second embodiment, three each on the output terminal 27b and the input terminal 27c scan is canceled is provided, for status setting scan example 10 ₅ and a state observer for The scan cells, for example, 10 ₆ may be integrated and reduced to two.

In the second embodiment, the outer lead of the TAB tape 50 is cut using the fuse for the short-circuit wiring 56, but the short-circuit wiring 56 is mechanically cut by using a normal metal wiring. May be.

In the connection test of the integrated circuit devices of the first and second embodiments described above, it is not necessary to prepare the socket 61 for multi-pins, but every time the integrated circuit chip 1 on the TAB tape 50 is tested. In addition, there is a problem that the socket 61 must be contacted with or separated from the test terminal 54 each time. The third embodiment of the present invention solves this problem, and the configuration of an integrated circuit device according to the third embodiment is shown in FIG. In FIG. 4, a plurality of integrated circuit chips 1 ₁ , 1 ₂ , 1 ₃ are actually mounted on a TAB tape 50. Each integrated circuit chip 1 _i (i = 1, 2,
3) on the surface of the power supply terminal pads 21a _i , 21b _i
, Ground terminal pads 22a _i , 22b _i , scan-in terminal pad 23 _i , and scan-out terminal pad 24
_i , test clock terminal pad 24 _i , test mode terminal pad 25 _i , and input / output terminal pad (not shown)
And a boundary scan circuit is provided therein as in the first and second embodiments.

The integrated circuit chip 1 ₁ of the scan-in terminal pads 23 ₁ scan-in terminal 3 on the TAB tape 50
0 are connected via a wire 31 _1, integrated scan-out terminal pads 24 ₁ through the wiring 31 ₂ circuit chip 1 ₂
Of the scan-in terminal pad 23a ₂ .
Integrated circuit scans the chip 1 ₂ out terminal pads 24 ₂
Is connected to the scan-in terminal pads 23 ₃ of the integrated circuit chip 1 ₃ through a wiring 31 _3, the integrated circuit the scan-out terminal pad 24 ₃ of the chip 1 ₃ scan-out terminal on the TAB tape 50 via the wiring 31 ₄ It is connected to the pad 32. Therefore, scan-in terminal pad 3
One scan path is formed from 0 to the scan-out terminal pad 32.

The power supply terminal pad 21a ₁ is connected to the power supply terminal pad 33a on the TAB tape via the wiring 34 ₁ , and the power supply terminal pad 21b ₁ is connected to the power supply terminal pad 21a ₂ via the wiring 34 ₂ . In addition, the power supply terminal pad 21b ₂ is connected to the power supply terminal pad 21 through the wiring 34 _3.
a ₃ and the power supply terminal pad 21b ₃ is connected to the wiring 34 ₄
Is connected to the power supply terminal pad 33b on the TAB tape 50 via.

The ground terminal pad 22a ₁ is connected to the ground terminal pad 35a on the TAB tape 50 via the wiring 36 ₁ , and the ground terminal pad 22b ₁ is connected to the ground terminal pad 22a ₂ via the wiring 36 ₂ . . The ground terminal pad 22b ₂ is connected to the ground terminal pad 22a via the wiring 36 _3.
Connected with ₃ . Ground terminal pad 22b ₃ is wiring 3
It is connected to the ground terminal 35b of the TAB tape 50 via a 6 _4.

Further, the test clock terminal pads 24 ₁ ,
24 ₂ and 24 ₃ are connected to the test clock terminal pad 37 on the TAB tape 50 via one wiring 38, and the test mode terminal pads 25 ₁ , 25 ₂ , 25 ₃ are connected to the TAB via one wiring 40. It is connected to the test mode terminal pad 39 on the tape 50.

In FIG. 4, the power supply voltage and the ground power are supplied by wirings 34 ₁ , 34 ₂ , 34 ₃ , 34 ₄ connecting the power supply terminals of the integrated circuit chips 1 ₁ , 1 ₂ , 1 ₃ and the chips. It is performed through 1 _1, 1 _2, 1 ₃ of the wiring. This is the test clock wiring 38, the test mode wiring 3
9 and scan path wiring 31 ₁ , 31 ₂ , 3
This is because the wirings for power supply and ground do not intersect with 1 ₃ and 31 ₄ .

Although not shown, the input / output terminals of the integrated circuit chip 1 are short-circuited via leads (not shown) on the TAB tape 50 as in the case of the first or second embodiment. Is connected to the wiring (not shown). The wiring for short circuit is not a single wiring but a plurality of wirings because it does not intersect with the wirings for power supply, ground, test clock, test mode, and scan path. If two-layer wiring can be formed on the TAB, the number of short-circuit wirings can be one.

Next, a case of testing the integrated circuit device of the third embodiment will be described. Test clock terminal 37,
The signals supplied or observed through the test mode terminal 39, the scan-in terminal 30, and the scan-out terminal 32 are
For example, IEEE boundary scan standard 114
9.1-1990 (IEEE Std 1149.1-1990, “IEEE Stad
ndard Test Access Port and Boundary-Scan Architect
ure ", May 21, 1990).

In FIG. 4, in order to perform a test, first, a test clock signal is applied to the test clock terminal 37, and a test mode signal is applied to the test mode terminal 39. 11
49.1 instructions such as EXTEST and INTEST are set, and for chips not tested,
Set the BYPASS command. As a result, the scan paths of the chips other than the test target can be bypassed, and only the chip to be tested can be tested with the short scan path. After the original test instruction (EXTEST, INTEST) is set only in the chip to be tested, the test is performed by the test method described in the first embodiment, whereby the inner lead of the TAB tape 50 and the integrated circuit chip 1 _i (i = 1, 2, 3) can be tested.

According to this embodiment, the signal is applied to the integrated circuit chip by applying the signal to the test terminal of the TAB tape 50, and the chip on the TAB tape 50 is selected by setting the test instruction. By doing so, it is not necessary to contact or separate the socket from the test terminal each time each chip on the TAB tape is measured. In addition, since the chips are electrically selected, the chips can be selected at high speed and the test time can be reduced.

Further, it goes without saying that the third embodiment also has the same effect as the first or second embodiment.

In the third embodiment, for power supply,
Although the wiring inside the integrated circuit chip 1 is used for the wiring for grounding, the wiring inside the integrated circuit chip 1 may be used for the test clock and the test mode.

[0054]

As described above, according to the present invention, even if the number of pins is increased, it is not necessary to prepare a socket for a large number of pins, and the test can be performed inexpensively and easily.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of an integrated circuit device according to the present invention.

FIG. 2 is a plan view of the integrated circuit device according to the first embodiment.

FIG. 3 is a block diagram showing a configuration of a second embodiment of an integrated circuit device according to the present invention.

FIG. 4 is a block diagram showing the configuration of a third embodiment of the integrated circuit device according to the present invention.

FIG. 5 is a schematic diagram illustrating a conventional method for testing an integrated circuit device.

FIG. 6 is a circuit diagram showing a specific configuration of scan cells.

[Explanation of symbols]

1 integrated circuit chip 10 _i (i = 1, ... 9) boundary scan cell 11 _i (i = 1, 2, 3) enable signal 12a, 12b bidirectional buffer 14 _i (i = 1, 2) output buffer 16 _i ( i = 1, 2) Input buffer 21 Power supply terminal pad 22, 35a, 35b Ground terminal pad 23, 30 Scan-in terminal pad 24, 32 Scan-out terminal pad 25 Test clock terminal pad 26 Test mode terminal pad 27 I / O terminal pad 27a Bidirectional terminal pad 27b _i (i = 1, 2) Output terminal pad 27c _i (i = 1, 2) Input terminal pad 31 _i (i = 1, ... 4) Wiring 33a, 33b Power supply terminal pad 34 _i (i = 1, ... 4) Power supply wiring 36 _i (i = 1, ... 4) Ground wiring 37 Test clock terminal pad 38 Test black Wiring 39 Test mode terminal pad 40 Test mode wiring 50 TAB tape 52 Lead 54 Pad 61 Socket 62 Probe terminal 67 Connection line 70 Tester

Claims (7)

[Claims] 1. A boundary scan circuit in which a plurality of boundary scan cells are cascaded, a scan-in terminal pad for setting data in the boundary scan circuit, and a scan-out terminal for taking out an output of the boundary scan circuit. A pad, an input terminal pad for inputting data, an output terminal pad for outputting data, and an input terminal pad provided corresponding to the input terminal pad, and the data from the input terminal pad is passed through the boundary scan cell. And an input buffer for sending the data internally to the output terminal pad, and whether data sent from the inside via the boundary scan cell is sent to the output terminal pad based on an operation control signal. Or output buffer controlled to be in high impedance state The integrated circuit device, characterized in that comprises a. 2. The integrated circuit device according to claim 1, wherein an output-dedicated terminal pad that does not serve as an input terminal pad among the output terminal pads has an output provided corresponding to the output-dedicated terminal pad. An input buffer is provided for sending the output of the output buffer to the boundary scan cell in order to observe the output of the buffer, and the input-only terminal pad that is not also used as the output terminal pad among the input terminal pads has this input. An output buffer is provided for sending data from the boundary scan cell to the input buffer based on an operation control signal in order to set data to be input to the input buffer provided corresponding to the dedicated terminal pad. An integrated circuit device characterized by the above. 3. When the integrated circuit device according to claim 1 is mounted on a TAB tape, each outer lead on the TAB tape of the input terminal pad and the output terminal pad is connected by a short-circuit wiring. An integrated circuit device characterized by: 4. The integrated circuit device according to claim 3, wherein the step of setting data in the boundary scan cell, and the operation control signal for only the output buffer corresponding to one output terminal pad of the output terminal pads. Sending the data set to the corresponding boundary scan cell to the input terminal pad and the input buffer via the short-circuiting wiring, the data being set to the boundary scan cell corresponding to the input buffer. A test method comprising: a step of observing by canceling. 5. When the integrated circuit according to claim 2 is mounted on a TAB tape, the outer leads on the TAB tape of the input terminal pad and the output terminal pad are connected to each other by short-circuit wiring. Characterized integrated circuit device. 6. A step of disconnecting outer leads of the input terminal pad and the output terminal pad from the short-circuit wiring after performing the test method of claim 4 using the integrated circuit device of claim 5. A step of setting data in the boundary scan circuit so that data of boundary scan cells corresponding to output buffers of adjacent terminal pads of the input terminal pad and the output terminal pad are different; Based on, the data of the corresponding boundary scan cell is sent to the boundary scan cell corresponding to the input buffer via the input buffer corresponding to the output buffer,
A test method comprising the step of observing with the boundary scan cell, and. 7. When a plurality of integrated circuit devices according to claim 1 or 2 are mounted on a TAB tape, the boundary scan circuits of each integrated circuit device are serially connected on the TAB tape and each integrated circuit device is integrated. An integrated circuit device, wherein an input terminal pad and an output terminal pad of the circuit device are connected to a short-circuit wiring for each integrated circuit device.