JPH0232271A - Test circuit for soldering defect inspection of multi-pin lsi - Google Patents

Abstract

PURPOSE:To enable inspection with two test patterns without knowing the circuit operation of a multi-pin LSI by sending out the output signals of OR and AND circuits through two output terminals for testing. CONSTITUTION:Input terminals 2-5 are connected to input buffers 2a-5a, whose outputs are connected to a signal processing block 6 which performs digital signal processing and also connected to AND circuits 14 and 17 and OR circuits 13 and 16 directly or through NOT circuits 15 and 18. then the output of the block 6 and the output of the circuit 14 which is obtained directly or inverted by the NOT circuit 19 are inputted to two-input selectors 20-23. The circuits 14 and 17 and circuits 13 and 16 are connected to output terminals 14a and 17a, and 13a and 16a for testing. Then the outputs of the block 6 and circuit 14 are selected by all the selectors 20-23 by the selector input terminal 2 according to normal operation and test operation and output signals are obtained from the terminals 13a and 14a and output terminals 7-10.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a test circuit for inspecting soldering defects in multi-pin LSIs.

Conventional technology In recent years, LSI technology has progressed and LSI packages have become smaller and smaller.
The number of pins is increasing. An example of a conventional multi-pin LSI will be described below with reference to the drawings.

FIG. 3 shows a conventional multi-pin LSI circuit. In FIG. 3, 1 is a multi-pin LSI. 2 is the first
is connected to a signal processing block 6 that performs various digital signal processing via a first input buffer 2a. The second input terminal 3, the third input terminal 4, and the fourth input terminal 5 also pass through the second input buffer 3a, the third input buffer 4a, and the fourth input buffer 5m, respectively, to the signal processing block 6. Connected to the input terminal. Signal processing block 6
The respective output terminals of to the output terminal 8, from the third output flip-flop 9b to the third output terminal 9 via the third output buffer 9a, from the fourth output flip-flop 10b to the fourth output terminal via the fourth output buffer 10g. 10, respectively. Further, the third output terminal 9 and the fourth output terminal 1o are each connected to the input terminal 9C110G of the memory 11, and each output terminal 9d, 10d of the memory 11 for the input terminal 9C110G is connected to the third output terminal 9C110G of the multi-pin LS11.
is connected to an input terminal 4 and a fourth input terminal 5.

The operation of the multi-bin LSI configured as described above will be described below.

First, input signals from the first input terminal 2 and the second input terminal 3 are input to the signal processing block 6 via the first input buffer 2!1 and the second input buffer 3m, respectively. After various digital signal processing is performed in the signal processing block 6, the output signal is sent from the first output flip-flop 7b to the first output terminal 7 via the first output buffer 7a.
From the second output flip-flop 8b to the second output terminal 8 via the second output buffer 8a; from the third output flip-flop 9b to the third output terminal 9 via the third output buffer 9a; are output from the output flip-flop 10b to the fourth output terminal 10 via the fourth output buffer 10m. Further, the respective output signals from the third output terminal 9 and the fourth output terminal 1o are inputted to the memory 11, and are transferred to the third input terminal 4 and the fourth input terminal of the multi-pin LS 11 after a certain delay time. 5 is input. Each input signal passes through a third input buffer 4a and a fourth input buffer 5a, and is input to a signal processing block 6, where it is used for various signal processing.

Problems to be Solved by the Invention However, in the above-described configuration, inspection for soldering defects when a multi-pin LSI and memory are mounted on a printed circuit board must be performed by visual inspection, signal input/output response, or the like. With recent advances in LSI technology, packages have become smaller and have more terminals, but there are limits to package size and number of terminals when visually inspected.
The problem is that a huge number of test patterns must be created after understanding the circuit operation of the memory.

Therefore, in view of the above-mentioned problems, the present invention is capable of testing soldering defects when a multi-pin LSI and a memo are mounted on a printed circuit board without knowing the circuit operation of the multi-pin LSI and using two test patterns. The present invention provides a test circuit for inspecting soldering defects in multi-pin LSIs, which can be inspected by observing input/output responses of signals.

Means for Solving the Problems In order to solve the above problems, the test circuit for inspecting soldering defects in multi-pin LSI according to the present invention includes an OF2 circuit connected to the output terminal of each input buffer connected to each input terminal. and A
An ND circuit, a plurality of two-input selectors that receive the output signal of the OR circuit or the AND circuit, and the output signal of the signal processing block, each output flip-flop connected to the output terminal of the plurality of two-input selectors, and two-input selectors. It is provided with a selection input terminal for selecting the output of the selector, a first test output terminal and a second test output terminal that output the output signal of the OR circuit and the output signal of the AND circuit, respectively.

For production The effect of this technical means is as follows.

That is, when the multi-pin LSI performs normal operation, all two-input selectors may select the output of the signal processing block using the selection input terminal. Further, when performing a soldering defect inspection test, all two-input selectors are caused to select the output of the OR circuit or the AND circuit using the selection input terminal. From this point on, when a test pattern is input to the input terminal, output signals are obtained from the first test output terminal, second test output terminal, and each output terminal of the multi-pin LSI. Can inspect soldering defects on input/output terminals. In addition, the test pattern is such that the output signal of the OR circuit or AND circuit input to the 2-input selector becomes the logical value "'O" and C'I I+, and the inputs of all input terminals are given the logical value tl□ ”
Two patterns that are 1" and 1" are sufficient.

Embodiment Hereinafter, a test circuit for inspecting soldering defects in a multi-pin LSI according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows a multi-pin LSI circuit incorporating a test circuit for inspecting soldering defects in one embodiment of the present invention.

In FIG. 1, 1 is a multi-pin LSI. The first input terminal 2, the second input terminal 3, the third input terminal 4, and the fourth input terminal 5 are connected to the power supply 12 via resistors 2b, 3b, 4b, and 5b, respectively, and at the same time, the first input buffer 2
m, second input buffer 3m, third input buffer 4-
1 Connected to each input terminal of the fourth input buffer 5a. 1st
The output of the input buffer 2 is input to the signal processing block 6, as well as the first OR circuit 13 and the first AND circuit 1.
Enter 4. The outputs of the three second input buffers are input to the signal processing block 6, and are passed through the first (7) NOT circuit 15 to the first OR circuit 13 and the first AND circuit 1.
Enter 4. The output of the third input buffer 4m is input to the signal processing block 6, and the second OR circuit 16,
The signal is input to the second AND circuit 17. The output of the fourth input buffer 5a is input to the signal processing block 6, and simultaneously passes through the second NOT circuit 18 to the second OR circuit 16, the second
input to the AND circuit 17. First OR circuit 13, first AND circuit 14, second OR circuit 16, second AN
The outputs of the D circuits 17 are respectively connected to the first test output terminals 13m.
, the second test output terminal 41, the third test output terminal 16a, and the fourth test output terminal 17m.

The first selector 20 selects the output 20m of the signal processing block 6 and the output of the first AND circuit 14, and outputs the first output via the first output flip-flop 7b and the first output buffer 7. Apply to terminal 7. Second selector 21
is the output 21m of the signal processing block 6 and the first AN
The output of the D circuit 14 is inverted by the third NOT circuit 19, and is selected and applied to the second output terminal 8 via the second output flip-flop 8b and the second output buffer 81.

The third selector 22 selects a certain output 22a of the signal processing block 6 and the output of the first AND circuit 14, and outputs the selected output to the third output terminal via the third output flip-flop 9b and the third output buffer 9a. Give to 9. Fourth selector 23
is the output 23m of the signal processing block 6 and the third NO.
The output of the T circuit 19 is selected and applied to the fourth output terminal 10 via the fourth output flip-flop 10b and the fourth output buffer 10m. Further, the third output terminal 9 and the fourth output terminal 1o are connected to the input terminal of the memory 11, and the output terminals are connected to the third input terminal 4 and the fourth input terminal 5, respectively. The select inputs of the four selectors 20 to 23 are collectively applied from a select input terminal 24.

The operation of the multi-pin LSI circuit incorporating the soldering defect inspection test circuit configured as described above will be described below.

First, a case where a multi-pin LSI performs normal operation will be described. In this case, the logic value +
By inputting “TO”, the four selectors 20.2
1.22.23 to each output terminal 2 of the signal processing block 6
0a121a, 22m.

23m signal is output, each output flip-flop 7b
, 8b, 9hi, 10b and each output buffer 7i, 8m,
9m and 10a to each output terminal 7.8.9.10.

Next, a case will be described in which a test for inspecting soldering defects is performed. In this case, the select input 24 has the logical value "1".
After inputting , perform the following two tests.

Test 1: Input the logic value "'1" to the first input terminal 2 and the logic value +TO" to the second input terminal 3.

Test 2: Logical value +1011 on first input terminal 2, second
The logical value "1" is input to the input terminal 3 of the .

In test 1, the two inputs of the first OR circuit 13 and the first AND circuit 14 both have a logical value of +1111, and the output from the first test output terminal 13m and the second test output terminal 14m is The logical value "1 n" is output. Also, since the logical value 1'1" is input to the select input terminal 24, the first selector 20 and the third selector 22
outputs the output of the first AND circuit 14 (logical value "1"), and the second selector 21 and fourth selector 23 output the output of the first AND circuit 14 to the third NOT circuit 1.
9 (logical value ++O+1) is output.

As a result, the output terminals 7.8, 9.10 output logic values "1", 0"l'+111, 110", respectively. After that, each is input to the input terminal 4.5. Therefore, the logic value "1" °0 is input to the input terminal 4.5.
” is input, the second OR circuit 16, the second AND circuit 1
Both of the two inputs of 7 have a logic value of "1", and the third test output terminal 16a and the fourth test output terminal 17a both output a logic value of "1".As a result, as shown in FIG. As shown in the figure, when the logical value "1" is input to the first input terminal 2 and the logical value ++ On is input to the second input terminal 3, the first output terminal 7, the second output terminal 8, and each test output terminal 13
Logical value +1”O” from a, 14m, 16a, 17g respectively
, °1"1" 11111 ++ 111 are obtained.

Next, in test 2, the first OR circuit 13 and the first AN
Both of the two inputs of the D circuit 14 have the logical value "O", and the first test output terminal 13s and the second test output terminal 14a both output the logical value +1 Q 11. Furthermore, since the logical value "1" is input to the select input terminal 24, the first selector 20 and the third selector 22 output the output of the first AND circuit 14 (the logical value ITo
The second selector 21 and the fourth selector 23 output the output of the first AND circuit 14 to the third NO
The T circuit 19 outputs the inverted value (logical value J++).

As a result, the output terminals 7, 8, 9, and 10 each output a logic value of +10'''1''LO''1''.

The output signals of the output terminals 9.1o are given a delay time by the memory 11, and then input to the input terminals 4.5.

Therefore, the input terminals 4.5 have respective logical values +T□I+1.
, 1'' is input, and the two inputs of the second OR circuit 16 and the second AND circuit 17 both have a logical value of ``0'', and the third test output terminal 16a and the fourth test output terminal 17
m outputs the logical value "0".In the end, as shown in FIG. 2, the logical value ++01 is output to the first input terminal 2.
1. When the logical value 14111 is input to the second input terminal 3, the logical value "O" is output from the first output terminal 7, the second output terminal 8, and each test output terminal 13m, 14a, 16m, and 17m. ++ I M IJ Q IT ++ Q
“PaO” ++011 is obtained.

In addition, each resistor 2b, 3b, 4b, 5b is connected to each input terminal 2.
．． 3.4.5 input logic values to each input buffer 2, 3
a, 4-15a, and each input terminal 2.3.
When 4.5 is a 7% impedance, the values are set such that a logical value of "1" is given to each input buffer 2, 3m, 4, and 5a.

At least all input terminals other than the power supply, ground, clock input terminal, and vacant terminals are connected to the power supply 12 by resistors.
Connect to.

If tests 1 and 2 are performed, the signals of all input/output terminals become logical values 0 and 1 once each, so that all soldering defects can be detected. For example, if there is a soldering defect in the first input terminal 2 or the second input terminal 3, the test output terminal 1
An abnormality appears in the 3m and 14m signals, and the first output terminal 7
Or, if there is a soldering defect in the second output terminal 8, an abnormality will appear in the signal of the output terminal 7.8, and the third output terminal 9,
If there is a soldering defect in the fourth output terminal 10, memory input/output terminal/control signal, etc., third input terminal 4, fourth input terminal 5, test output terminals 16m, 17m
An abnormality appears in the signal. Furthermore, each input buffer 2a
, 3 heat, 4 a, 5 hatake output to each OR circuit 13.16, A
When inputting to the ND circuit 14.17, NOT
If you invert and input using circuit 15.18, the input logical values of the test pattern will differ between adjacent input terminals, so
It can also detect solder contact with the terminal next to the input terminal.

Also, each selector 20.21.22.23 has a first AN
C) When inputting the output of the circuit 14, the first AND circuit 1
NOT circuit 1 is connected to every other selector that connects the output of 4 to the adjacent output terminal on the multi-bin LSII package.
If the test pattern is inverted and inputted using 9, the output logic value of the test pattern will be different between adjacent output terminals, so it is possible to detect solder contact with the terminal next to the output terminal.

As described above, according to this embodiment, each input terminal 2.3.4
．． 5 is connected to the power supply 12 via resistors 2b, 3b, 4b, and 5b, and the output of the first input buffer 2a is input to the signal processing block 6, and also to the first OR circuit 13 and the first AND circuit 14. input, inputs the output of the second input buffer 31 to the signal processing block 6, and inputs the output of the second input buffer 31 to the first NO.
The first OR circuit 13 and the first AND via the T circuit 15
The output of the third input buffer 4a is input to the signal processing block 6, and the second OR circuit 1
6. The output of the fourth input buffer 5a is input to the second AND circuit 17, and the output of the fourth input buffer 5a is input to the signal processing block 6. 17, the first OR circuit 13, the first AND circuit 14, the second OR circuit 16, the second AN
The outputs of the D circuits 17 are respectively connected to the first test output terminals 13m.
, connected to the second test output terminal 14a, the third test output terminal 16a, and the fourth test output terminal 17a,
Output 2 with signal processing block 6 in first selector 2o
0a and the output of the first AND circuit 14, the second selector 211 selects the output 21a of the signal processing block 6.
and the output of the first AND circuit 14 to the third NOT circuit 19
, the third selector 22 selects the output 22g of the signal processing block 6 and the output of the first AND circuit 14, and the fourth selector 23 selects the output 23a of the signal processing block 6. and the first ANC) circuit 14
The third NOT circuit 19 selects the inverted output of , and the select inputs of the four selectors 20 to 23 are collectively applied to the C select input terminal 24, thereby creating two test patterns, test 1 and test 2. Multi-pin LS
11 and all input/output terminals of the memory 11 can be inspected for soldering defects.

Effects of the Invention As described above, according to the present invention, the OR circuit and the AN connected to the output terminal of each input buffer connected to each input terminal
A D circuit, a plurality of two-input selectors receiving the output signal of the OR circuit or the AND circuit and the output signal of the signal processing block as inputs, and each output flip-flop connected to the output terminal of the plurality of two-input selectors. and a selection input terminal for selecting the output of the two-input selector, and a first test output terminal and a second test output terminal for outputting the output of the OR circuit and the output of the AND circuit, respectively. By looking at the input/output responses of the signals according to the two test patterns, it is possible to inspect all the input/output terminals for soldering defects.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a multi-bin LSI incorporating a test circuit for inspecting soldering defects in a multi-pin LSI according to an embodiment of the present invention, FIG. 2 is a logic diagram showing input/output logic in each LSI operation, and FIG. FIG. 3 is a circuit diagram showing the circuit configuration of a conventional multi-pin LSI. DESCRIPTION OF SYMBOLS 1...Multi-pin LSI, 2...First input terminal, 2a...First input buffer, 2b,
314b. 5b...Resistor, 3...Second input terminal, 3a...Second input terminal, 4...
・Third input terminal, 4m...Third input buffer, 5...Fourth input terminal, 5a...
Fourth input buffer, 6...signal processing block, 7...first output terminal, 7a...first output buffer, 7b... First output flip-flop, 8...Second output terminal, 8m...
...Second output buffer, 8b...Second output flip-flop, 9...Third output terminal, 9m...Third output buffer, 9b...
...Third output flip-flop, 9c, 10e...
...Memory input terminal, 9d, 10d...Memory output terminal, 10...Fourth output terminal, 1
0a...Fourth output buffer, 10b...
...Fourth output flip-flop, 11...Memory, 12...Power supply, 13...First OR circuit, 13a...First Test output terminal, 14...First AND circuit, 14a...
...Second test output terminal, 15...First N07 circuit, 16...Second OR circuit, 16m
...Third test output terminal, 17...
・Second AND circuit, 17g...Fourth test output terminal, 18...Second N07 circuit, 19
...Third N07 circuit, 20...First
selectors 20a, 21a, 22a, 23a...
...Output of the signal processing block, 21...2nd
selector, 22...Third selector, 23.
...Fourth selector, 24...Select'
input terminal.

Claims (5)

[Claims] (1) a plurality of input terminals, a plurality of input buffers connected to the plurality of input terminals, and a signal processing block that performs digital signal processing connected to the output terminal of each input buffer;
OR circuit and AN connected to the output end of each input buffer
D circuit, a plurality of 2-input selectors that receive the output signal of the OR circuit or the AND circuit and the output signal of the signal processing block as inputs, and a plurality of output flip-flops connected to the output terminals of the plurality of 2-input selectors. , a plurality of output buffers connected to the output end of each output flip-flop, a plurality of output terminals connected to the output end of each output buffer, and an input terminal for a select signal that selects the output of the two-input selector. and a first test output terminal and a second test output terminal that respectively output the output signals of the OR circuit and the AND circuit. (2) Soldering of the multi-pin LSI according to claim 1, in which all input terminals other than at least the power supply, ground, clock input terminal, and vacant terminal among the plurality of input terminals are connected to the power supply via a resistor. Test circuit for detecting defects. (3) At least one of the output terminals of the multi-pin LSI is input to the memory, the output terminal of the memory is connected to the input terminal of the multi-pin LSI, and the output terminal of the input buffer is connected to the input terminal connected to the memory. The OR circuit and the AND circuit connected to the output terminal of the input buffer connected to the input terminal not connected to the memory and the A
The multi-pin LS according to claim 1, wherein the ND circuit is separate, and the first test output terminal and the second test output terminal are also separate for each OR circuit and each AND circuit.
I test circuit for inspecting soldering defects. (4) A test for inspecting soldering defects in a multi-pin LSI according to claim 1, in which the OR circuit and the AND circuit input at least one of their inputs by inverting the signal from the input terminal. circuit. (5) A patent claim in which a plurality of two-input selectors that receive the output of an OR circuit or an AND circuit and the output of a signal processing block input the inverted output of at least one of the OR circuits or AND circuits. A test circuit for inspecting soldering defects in a multi-pin LSI as described in scope 1.