JPS6039186B2 - semiconductor element - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a structure of a semiconductor device mounted with a logic element to realize a logic function.

Semiconductor devices refer to both those with ICs mounted on a substrate and those with gates mounted thereon (such as IC chips). FIG. 1 shows the logic structure of a board on which a conventional logic element is mounted.

The prior art is concerned only with realizing logical functions. In FIG. 1, reference numerals 101 and 103 are input terminals to which logic values are applied from the outside, logic A performs a logic operation, and the result is delivered to logic B.

Logic B receives it, performs similar logical operations, and outputs the results to output terminals 201 and 202. When testing the functions of logic A and logic B, test data prepared in advance is given to the input terminals 101 and 102, and the resulting values at the output terminals 201 and 202 are compared with the expected values prepared in advance. and determine whether it is good or bad.

Since one piece of test data is not enough to test all logic functions, the above steps are repeated by sequentially applying a plurality of pieces of test data to the input terminal. The conventional example described above has the following problem first.

In Figure 1, when logic A and logic B become complex, it is not possible to create test data that tests all functions simply by supplying test data from the input terminal and comparing the actual value and expected value at the output terminal. It's getting difficult. In other words, the test data for detecting a "0" stuck-at type fixed fault at a certain point in logic A is an input terminal that satisfies both the conditions for making that point "1" and the conditions for guiding the logical value at that point to the output terminal. However, when logic A and logic B become complicated, it becomes difficult to obtain the logic value of the input terminal that satisfies this. In order to alleviate this problem, as shown in Figure 2, a method has been adopted in which the output of logic A is also output to the output terminal and the number of points for comparison with the expected value is increased, but this method has the problem of increasing the number of output terminals. be. Next, in the logical structure shown in Figure 1, when testing, the tester has a part that stores test data, a part that controls giving test data one by one, and a part that compares the value of the output terminal with the expected value. Separately required.

Therefore, a complicated tester is required for inspection. An object of the present invention is to facilitate the creation of test data by increasing the points at which actual operation and expected values are compared when test data is given to a logic circuit to be tested.

Another purpose is to enable inspection with a simple tester. It is possible to store test data on the same board as the logic element mounting board that has logic functions, and to place a logic circuit on the same board that compares the actual operation with the expected value when test data is given. This is the main point of the invention.

FIG. 3 shows an embodiment of the present invention.

In FIG. 3, the control circuit 3 is a control circuit for writing and reading test data into and from the memory element 4.

101 and 102 are used both for inputting normal logic functions and for inputting test data.

A pulse 103 for counting the address of the memory element is input. Reference numeral 1104 is a signal line for controlling reading and writing of the memory element.

105 controls normal logic operations and inspection operations.

- This is a signal to be used. The memory element 4 stores test data. The control circuit 5 controls switching between the input terminals 101 and 102 and the storage element as data to be applied to the logic A, and transfers the expected value stored in the storage element to the next comparison circuit 6. It is important to prepare for comparison. The comparison circuit 6 compares the logical values of arbitrary points of the circuit under test, in this example, P, Q, 201, 202, with the expected value passed from the control circuit 5, and outputs the coincidence or mismatch to the output terminal 203. It is. In normal logic operation, signals enter from 101 and 102, pass through control circuit 5, and are passed to logic A.

After that, logical operations are performed using logic A and logic B, and the results are output to 201 and 202. However, the input terminal 105 must be a signal indicating normal logic operation. This signal causes the control circuit 3 and comparison circuit 6 to become inoperable. The control circuit 5 outputs 101 and 102 instead of the output of the storage element 4.
Select and output the logical value. Next, the operation for inspection will be explained.

Input data or expected values for testing are input into 101 and 102, and 105 is a control signal for testing operation;
Give a write signal to 04.

Therefore, when a signal for counting addresses is applied to 103, test input data or expected values are written into the memory element. By sequentially repeating this, test input data and expected values are stored in the storage element in advance. When actually inspecting, a read signal is input to 104, a control signal for inspection operation is input to 105, and a signal for counting addresses is input to 103.

As a result, test input data or expected values are read from the memory element 4 and passed to the control circuit 5. The control circuit 5 prepares the data so that it can be passed to the logic A if it is test input data, and to the comparison circuit 6 if it is an expected value, and supplies it to the logic A and the comparison circuit in units of one test sequence. The comparison circuit 6 compares the expected value and the logical value of the actual operation for each point and calculates
If they do not match, a 203 pin mismatch signal is output.
Note that in the above explanation, for simplicity, the outputs are P, Q,
Only two pins, 201 and 202, are numbered, but generally there are more pins, and the total number of pins is the second.
This number is smaller than the example shown in the figure.

Also, although the logical block can be divided into two in the embodiment,
Even if the board has logic that can be divided into more than this, the output of any logic block can be tested in the same way. According to the present invention as described above, it is possible to compare the expected value and the actual logic value at any point, so it becomes easier to create test data for logic functions, and this can be achieved with a small number of pins.

Furthermore, since test data and comparison circuits are built-in, tests can be performed using simple control signals.

[Brief explanation of drawings]

Figures 1 and 2 are diagrams showing the logical structure of the prior art, and Figure 3 shows the logical structure of the prior art.
The figure shows an embodiment of the present invention. Tortoise; Logic A, 101-105; Input terminal, 2; Logic B,
201 to 203: output terminal, 3: control circuit, 4: memory element, 5: control circuit, 6: comparison circuit. Na figure 2 figure 3 figure

Claims (1)

[Claims] 1. A logic circuit including a plurality of logic elements, means for storing test data and providing it to the logic circuit, and means for comparing the output with an expected value are mounted on the same substrate, and the output is A semiconductor device comprising an output from at least one intermediate point of a logic circuit.