CN85108326A - The very lagre scale integrated circuit (VLSIC) that self-testing capability is arranged - Google Patents

Abstract

A kind of self-test very lagre scale integrated circuit (VLSIC) comprises the functional block of finishing very lagre scale integrated circuit (VLSIC) device basic function.Has the enclose pattern generator so that under the control of test controller, produce predetermined figure.The test controller response is carried out the presumptive test program by interface circuit from the external signal that the external control bus receives.The output of functional block is imported into identification circuit its output is compared with predetermined testing standard.If test controller is measured the output of identification circuit and failed to carry out effective ratio, then produce fault-signal at the test program end between processed resolution chart data and predetermined testing standard.

Description

The very lagre scale integrated circuit (VLSIC) that self-testing capability is arranged

The present invention is usually relevant with the fault test of the interior dress of integrated circuit in a system, and is more particularly relevant with the self-test characteristics of very lagre scale integrated circuit (VLSIC) on chip-scale and circuit board level.

Because the increase of Technology Need, the closeness of integrated circuit and the variation of function increase day by day.The speed of these integrated circuit deal with data also constantly increases in addition.These devices are commonly referred to as very lagre scale integrated circuit (VLSIC) (VLSI).In order to realize the very lagre scale integrated circuit (VLSIC) device reliably, device and packaged chip that new technology is made semiconductor chip scale have been developed.Because very lagre scale integrated circuit (VLSIC) also must link to each other with peripheral circuit, thereby some delivery outlets must be arranged, control mouth etc. are so have some intrinsic shortcomings to the density and the speed of this growth.Because a VLSI (very large scale integrated circuit) chip can be finished a large amount of functions, compares with the function number that device is finished, interface linking number or integrated circuit pinnumber are less relatively.The result searches the fault of built-in function and built-in function is carried out failure analysis feel difficulty because of being difficult for contact, because the use that interface connects must optimization, and they generally depend on the functional mode rather than the test mode of device.

In case utilize very lagre scale integrated circuit (VLSIC) to make a system, it is very important keeping some forms to the built-in test of the chip of very lagre scale integrated circuit (VLSIC) and the system of packing into thereof.This test can be finished on many grades, and as chip-scale, circuit board level and system-level, wherein chip-scale is a lowermost level.The purpose of built-in test is to determine before finishing desired function whether this system can satisfy the requirement of operating instruction regulation, the form that lost efficacy may be the fault that interconnected between connector and different elements, between each VLSI (very large scale integrated circuit) chip fault is arranged on the circuit board, perhaps even between the pin of VLSI (very large scale integrated circuit) chip and circuit board itself fault is arranged.In chip-scale, losing efficacy has two kinds of forms, and promptly the funtion part at chip has fault or in the funtion part of chip and the interface circuit between the integrated circuit pin fault arranged.Integrated circuit (IC) chip lost efficacy has significant percentage to be because output interface circuit has fault.At circuit board level, lost efficacy or because in that to interconnect contacting of interconnection graph on bad or integrated circuit pin and the plate on the printed circuit board (PCB) cranky.The form of system-level malfunction normally is connected with fault between control bus and the signal bus.

Aspect system testing, the processor of the utilization central authorities of system of prior art or produce the similar ancillary equipment that various resolution charts are input to each device in the system.The function of each device is also controlled so that each device can both independent test, and the different circuit of perhaps controlling on the various boards interact in a predefined manner, and the output prearranged signal.The output signal of this any test pattern is compared with the result of expectation, and whether test result is maked decision in acceptable working range.If this result is not within acceptable scope, then this system is decided to be inefficacy, and essential or repairing is perhaps changed.

For system-level, on circuit board level or the chip-scale system is carried out built-in test, preferably different brackets can both respond single fast signal separately and carry out self-test.This self-test need be different with the normal function circuit the built-in test circuit.These test circuits produce test signal, handle output signal, and control general test itself.The existing system of the built-in test of discrete component that provides need establish dedicated pin on integrated circuit, so that allow to touch the funtion part of integrated circuit.This may need a large amount of dedicated pin, is a shortcoming therefore.It is that people are undesirable that integrated circuit pin is exclusively used in test, just it should be minimized as possible.

Because above shortcoming is arranged, exist a kind of needs for the self-test very lagre scale integrated circuit (VLSIC), promptly in test mode, do not need to use a large amount of application-specific integrated circuit (ASIC) pins to link to each other with very lagre scale integrated circuit (VLSIC).

Open and request patent protection the present invention includes self testing circuit in order to the test function circuit block at this.Self testing circuit comprises the pattern generator circuit, and it produces resolution chart according to the test program of storing and is input to functional circuit.Then the output of functional circuit being input to comparison circuit compares treated resolution chart signal with the presumptive test standard.If between dateout of handling and presumptive test standard, do not make effective ratio, then produce a fault-signal at the test program end.So far, after receiving triggering signal from external source, promptly begin to produce resolution chart by the interface gateway.This interface gateway also provides a path, by this path fault-signal is sent to external device (ED).

In another embodiment of the present invention, test program is stored in the stored position on the integrated circuit, and control circuit is visited this resolution chart with predefined procedure.The input of functional circuit blocks is linked in the output of resolution chart storage circuit, and can be by the control circuit addressing.Comparator receives the resolution chart data by the processing of functional circuit blocks output, and this is compared with the presumptive test standard that is produced by control circuit.Control circuit is also determined the function of functional circuit blocks according to the test program of storing.

In order more completely to understand the present invention and advantage thereof, do following explanation now in conjunction with the accompanying drawings with for referencial use, comprise in the accompanying drawing:

Fig. 1 is shown in the functional circuit on the self-test VLSI (very large scale integrated circuit) chip and the block schematic diagram of relevant test circuit;

The calcspar of the expansion of the VLSI (very large scale integrated circuit) chip of Fig. 2 pictorial image 1;

The block schematic diagram of the functional circuit of Fig. 3 pictorial image 2;

Fig. 4 diagram is with the network of the very lagre scale integrated circuit (VLSIC) device of ring connection connection;

Fig. 5 diagram tests out the calcspar of ingress interface;

Fig. 6 illustrates the oscillogram of bit protocol;

Fig. 7 diagram tests out the schematic diagram of ingress interface circuit;

Fig. 8 illustrates the block schematic diagram of selected marker circuit;

The block schematic diagram of Fig. 9 direction as shown detection circuit; And

Figure 10 illustrates the interface circuit of VLSI (very large scale integrated circuit) chip and the workflow diagram of self-test feature.

Now referring to Fig. 1, the block schematic diagram of the very lagre scale integrated circuit (VLSIC) mainly formed by functional circuit blocks (10) of diagram wherein.Functional circuit blocks (10) can be finished such as arithmetic and logic unit (ALU), multiplier, the function of arbitrary pattern such as adder.In most preferred embodiment, functional circuit blocks (10) is for handling the digital circuit of numerical data.Yet, should understand that functional circuit blocks (10) can be a simulation circuit.

Functional circuit blocks (10) goes up at input bus (12) and receives the input data and go up dateout at output bus (14).Input bus (12) and output bus (14) are the representative of one group of circuit, and this bus links to each other with the pin of integrated circuit encapsulation by input buffer (13) and output buffer (15).Buffer (13) and (15) are tristate buffers, and it is controlled, so as functional circuit blocks (10) and integrated circuit pin to be disconnected also thereby with the disconnection that is connected of ancillary equipment.

As mentioned above, functional circuit blocks (10) has functional mode, also has test mode in addition.When test mode, produce test signal according to preset program, and analyze the result who handles these test signals with functional circuit (10).Test signal produces in pattern generator (16), and this generator is linked the input of functional circuit blocks (10) by bus (18).Identification circuit (20) is linked the test signal of the output of functional circuit blocks (10) with the reception processing by bus (21), and they and presumptive test standard are compared.The test signal that is produced by pattern generator (16) under test mode and the work of functional circuit blocks (10) are all controlled by test controller (22), this controller links to each other with pattern generator (test Pattern generator) (16) or read-only memory by bus (24), link to each other with function circuit piece (10) by control bus, and link to each other with identification circuit by bus (28), so that the testing standard data are provided.

The work of test controller (22) is operation one presumptive test program (this program is stored in the very lagre scale integrated circuit (VLSIC) device inside), with function that determines functional circuit blocks (10) and the test signal that is input to this place.Test controller also determines to be input to the presumptive test standard of comparator or identification circuit (20).An example of functional circuit and test program thereof is and door that wherein test program is made up of truth table.Logic state on the input is by pattern generator (16) change.And output is compared with expected results (or logic state " 0 " or logic state " 1 ").These expected resultss are produced by test controller (22).Identification circuit comprises two input comparators.

There is an interface circuit (30) to do connection between test controller (22) and the control bus (32).This interface circuit provides a special-purpose gateway to control bus (32), comes the work of controlled function piece (10) under test/maintenance mode by it, and this will illustrate below.Control bus (32) is delivered to the very lagre scale integrated circuit (VLSIC) device to control signal, and test result delivered to outside point from the very lagre scale integrated circuit (VLSIC) device, and comprise two holding wire S1 and S2, error message line AT, and clock line CK, its working condition will illustrate below.

When work, functional block (10) is worked under functional mode usually, and this mode allows device to go up received signal at input bus (12), goes up output signal at output bus (14), and works in system.These buses (12) and (14) link to each other with the application-specific integrated circuit (ASIC) pin by buffer (13) and (15) respectively, and this pin and integrated circuit packing form whole.Under test/maintenance mode, signal is added to interface circuit (30) by interface control bus (32), so that the beginning test program.This testing sequence realizes with test controller (22).Test controller is controller buffer (13) and (15) at first, prevent that functional circuit (10) links to each other with external device (ED), produce signal by bus (24) then, make pattern generator (16) produce figure.Functional circuit blocks (10) (a kind of functional block of multitask) is controlled by control bus (26) by test controller (22) in addition, to finish given function.Output will change along with the pattern of used functional circuit blocks (10), and required test number also changes along with the change of pattern simultaneously.

When testing, carry out the test program of storing and testing sequence is done down set by step by test controller (22).Produce the test input for each test in this order, and the function of functional circuit blocks (10) is in selected function.This output is compared with the expected results that is produced by test controller (22).For each step in testing sequence, can with the effective ratio of each test in this order or test result stored.Yet, because self-test feature of the present invention is row/not all right test, thus only need to monitor the existence of invalid test result, because just can judge that with this point this device is defective device.

By the pattern generator of providing for oneself that utilizes and the functional circuit that will test links mutually, controller and identification circuit, and it is integrated in single-chip or the integrated circuit, just can no longer needs to use all external control signals.Mode in view of the above only need provide initial signal to test controller, and the presumptive test program that makes the relevant very lagre scale integrated circuit (VLSIC) of beginning just.So no matter the density of the function finished of functional circuit blocks (10) and quantity how, begin test program and therefrom to obtain exporting the line that only needs minimum quantity just passable.This permission is carried out fault test in chip-scale.Chip-scale is the minimum grade in the hierarchical organization of any system.Because can not place under repair on semiconductor chip, so must be changed, thereby self-test feature of the present invention allows each the very lagre scale integrated circuit (VLSIC) device in the external system controller Request System to carry out self-test, and the relevant information back that breaks down in this system is arrived system controller.Only it may be noted that in the somewhere of this system has fault, and not it may be noted that trouble location.This will determine in " maintenance " mode as described below.

Now referring to Fig. 2.This figure is the expansion calcspar of the self testing circuit of Fig. 1, and among each figure, same parts are marked with identical number.As mentioned above, functional circuit blocks (10) can be the functional circuit of any pattern.For the purpose of illustrating, utilize the arithmetic and logic unit (being called vector operation logical block (VALU)) that has many other functions that one embodiment of the present of invention are described.Vector operation logical block label in the drawings is 40, and its three I/O ports are denoted as " A ", " B " reaches " C ".The A gateway is connected with one group of bidirectional lines driver (42), and the B gateway is connected with one group of bidirectional lines driver (44), and the C gateway is input to a gleam of driver (46), so that enter data into vector operation logic position (40).Driver (42), (44) and (46) represent input buffer (13) and output buffer (15), and by test controller (22) control, so that allow data to transfer to relevant gateway, or shift into from it.The output " injection " of pattern generator (16) is to the input buffer of the input buffer of buffer (42) and buffer (44) and be injected in the buffer (46).

Vector operation logical block (40) has two groups of output lines (48) and (50).Output line (48) is input to multiplexer (Multiplexer) (52), and output register (54) is linked in the output of this transducer, so that store dateout.Output line (50) is input to multiplexer (54), and output register (58) is linked in its output, so that store data therein.Output register (54) outputs to the A gateway by the output of a driver in the line drive (42) with data, and output register (58) will be failed according to outputing to the B gateway by the output of the driver in the line drive (44).

The function operational order of vector operation logical block (40) is stored in the microcoding read-only memory (60), and this memory is by the outer address addressing that is stored in address register/counter (62).When circuit was worked with functional mode, outer address allowed to select the specific function of vector operation logical block (40).The output of microcoding read-only memory (60) is input to an input of multiplexer (64), and pipeline register (66) is linked in its output.The output of pipeline register (66) provides micro-coded instruction, the difference in functionality of this instruction control circuit.In when operation, the microcoding read-only memory is by the particular address addressing, and, be included in data word on this address location and determine content in the micro-coded instruction of the output of pipeline register (66).Different door and reference voltage are set then, to finish appropriate functional in vector operation logical block circuit (40).

As described above in reference to Figure 1, carry out easily for making test mode, test controller (22) output control signal is controlled from the output of microcoding read-only memory data.Output count signal (CNT) just can make this point accomplish easily to address register/counter.This count signal stepping is by a series of instructions, and the micro-coded instruction by pipeline register (66) output is determined in this instruction.The output of microcoding read-only memory (60) also is input to pattern generator (16), and this generator is a read-only memory.Data by microcoding read-only memory (60) output are addresses.The address that is input to pattern generator (16) is by multiplexer (68) control, and an one input is linked the output of microcoding read-only memory (60), and its another input is then linked the output of counter (70).Counter (70) is controlled by test controller (22), so that pack initial value therein into, and through this clock speed stepping of value to be scheduled to.This value is input to pattern generator (16), so that predetermined resolution chart is provided, or the sequence of resolution chart.In addition, the output of calculator (70) also is input to an input of multiplexer (64) to provide a numerical value as the output from pipeline register (66), and this register can pass through or be counted in order.By the predetermined value of in counter (70), packing into test system system device (22), need in microcoding read-only memory (60) independent code of each function storage of order, just can finish a series of functions by the step.So counter (70) is used more effectively the space on the chip.

Except that in a predefined manner instruction code being lined up order, also the diagnostic program that separates can be stored in the microcoding read-only memory (60), program step is carried out in order one by one.Each program step is the address of a micro-coded instruction.Yet the test mode of this kind pattern needs a large amount of memory spaces for the functional circuit of complexity.

In another embodiment of the invention, register (66) is replaced by test controller (22), so that independent generation micro-coded instruction.In this embodiment, the storage of instruction and program separates with the funtion part of circuit.From practical viewpoint, self test mode is the combination of said method.

When test mode, output valve is taken out from output register (54), is input to identification circuit or comparator (20).Identification circuit can be any type of circuit, this circuit with output valve with compare by the determined expected result of presumptive test standard.A kind of form of this circuit can be a kind of simple comparator circuit.One input of comparator circuit is linked output valve, and another input is then linked test controller (22).Test controller (22) output comparand is to identification circuit (20) and directly compare then.As obtain true comparative result, then this is tested and is successfully test.Yet, will point out that for the output that the faulty circuit comparator is arranged chip has fault.This rub-out signal is input to test controller (22), is input to interface circuit (30) then, with its output.The use of this rub-out signal will illustrate below.

In most preferred embodiment, identification circuit (20) uses conventional data compression technique that data are compressed in time or on the space.Be predetermined result or " hardwired " (" hard wired ") result all identical with the expected results that packed data output compares to all tests.By suitable selection input data, output can be controlled to be the same with the expected result that presets.The used data compression technique of the present invention is " signature analysis ", and an example wherein is verification and circuit.The signature analysis technology had once been done more intactly to discuss in " analysis of parallel sign difference and assimilation " literary composition.This article author is that T. West Germany moral is breathed out (T.Sirdhar), what (D.S.HO) of D.S., and P.T. Bao Weir (P.T.Powell), S.M. spread spy (S.M.Thette), are published in nineteen eighty-two international testing meeting minutes 656-661 page or leaf.

Referring now to Fig. 3.Fig. 3 is the expansion block schematic diagram of the part functional circuit of vector operation logical block (40).Some functions that vector operation logical block (40) is finished are arithmetic and logic unit (ALU), the function of multiplier part and adder/subtracter part.Each part individually links to each other with its input and output and has all files (file) and register to interrelate with it.The multiplier part is by multiplier memory (multiplier file) (71), and multiplier (72) and displacement (shift)/selector (74) are formed.Add/subtract part by adder/subtracter circuit (76), A-input register (78) and B-input register (80) are made, and its output is handled by displacement/selector (82).Arithmetic and logic unit is made up of arithmetic and logic unit memory (84) and arithmetic and logic unit circuit (86).

Gateway A, B and C are made up of 16 bit data bus, and A gateway and B gateway can be selected as input port or delivery outlet, and the C mouth only is elected to be input bus.A, B, three gateways of C are elected to be by multiplexer (88) and (90) respectively and are the input to the A and the B input of multiplier memory (71).Multiplexer (88) from the A gateway, the output of arithmetic and logic unit (86) and the output that adds/subtract part internal shift/selection circuit (82) selects input.Multiplexer (90) is being selected between B and the C gateway and between the output of the displacement/selection circuit (74) in the output of arithmetic and logic unit (86) and multiplier part.The input that receives from multiplexer (88) and (90) is handled by multiplier memory (71).Multiplier (72) is worked immediately and is finished whole multiplication with the result who handles in the displacement/selection circuit (74).The available many different algorithms that multiply each other on digital value, one of them is Persian algorithm (Booth ' salgorithm).

The input of output multiplexer (52) is linked the output of arithmetic and logic unit (86) and the output of displacement/selection circuit (82) by circuit (48).The input of multiplexer (56) is linked the output of arithmetic and logic unit (86) and the output of displacement/selection circuit (82) by circuit (50).When work, data are encased in the multiplier memory, use multiplier (72) and displacement/selection circuit (74) to carry out multiplying then.An output of displacement/selection circuit is input to multiplexer (91) usefulness that elects, and is input to the A-register (78) that adds/subtract part.The input of multiplexer (90) is linked in another output of displacement/selection circuit (74) backward.In addition, the output of multiplier memory (71) is input to multiplexer (91) and multiplexer (93) via multiplier (72) and displacement/selection circuit (74) institute fixed line, and B-register (80) is then linked in the output of multiplexer (93).

The multiplexer (91) that is adding/subtracting in the part has four inputs, and they link an input of displacement/selection circuit (74), an output of multiplier memory (71), the output of A input port and arithmetic and logic unit (86).Multi-channel converter (93) has three inputs, and an input is linked the output of displacement/selection circuit (74), and an input is linked an output of multiplier memory (71), also has an input to link the output that adds/subtract circuit (76).When work, add/subtract circuit (76) and receive two input signals from A-register (78) and B-register (80), its input value is selected by multiplexer (91) and (93) respectively.Add/subtract the output of circuit (76) or to being fed back into multiplexer (93) so that in B-register (80), select, and stored thereafter, perhaps, handle by displacement/selection circuit (82).As its output.

The output of displacement/selection circuit (82) is input to an input of multiplexer (92) and multiplexer (94).The input of arithmetic and logic unit file (84) is linked in the output of multiplexer (92) and (94).The remaining input terminal of multiplexer (92) is then linked the A input port, the output of C input port and arithmetic and logic unit (86).The remaining input terminal of multiplexer (94) is then linked the B input port, the output of the displacement/selection circuit (74) of multiplier part and the output of arithmetic and logic unit (86).When work, arithmetic and logic unit (86) is by the micro-coded instruction control that comes from register (66), so that carry out selection logical operation about data, these data are selected as output by multiplexer (92) and (94), and are handled through arithmetic and logic unit file (84).Arithmetic and logic unit file (84) comprises interior register, and its response micro-coded instruction is stored and selected data, so that output to arithmetic and logic unit (86) selectively.These data are handled by arithmetic and logic unit (86) then, and therefrom output.

When test vector arithmetic and logic unit (40), remove outside the computing of all inner function circuits, also can test other all positions.For example, if the work of check multiplier memory or various register storages, then visit pattern generator or read-only memory (16) and be stored in pre-stored values in desired register or the data file memory with output, the interior functional block of control only is sent to data the output of arithmetic and logic unit (86) by this place then, so that be input to identification circuit or comparator (20), determine whether to receive desired result.Can control pattern generator or read-only memory and export the resolution chart of any pattern, and the logic function of all circuit such as adder/subtracter (76) and arithmetic and logic unit (86), available predetermined way is by different files and register is controlled so that deal with data.Mistake in any device all can provide the result different with expected result, thereby points out that fault is arranged in device.

As mentioned above, in another form of test, in microcoding read-only memory (60), store a diagnostic program.This program is only made the usefulness of self-test.This diagnostic program is a testing sequence, and it is finished set by step with vector operation logical block (40), finishing all functions, and in identification circuit or comparator (20) result of output relatively.Because this is the test of being scheduled to, so Test Design can be become all results of output, perhaps can be designed to always export same result, as exports the position of a string logic state for " 0 ".This is a kind of method of simplification, and wherein identification circuit or comparator are always compared the result with data word, and this data word all has logical zero for its all data bit.By utilizing diagnostic program, can control the concrete test that to finish more closely.Yet carrying out aspect the required instruction number of whole test, this can prove a shortcoming.Thereby the common other technologies that more effectively to utilize memory space on the chip of preferably utilizing.Certainly, this is the thing of relevant design alternative.

Now referring to Fig. 4, Fig. 4 is the block schematic diagram of the network of very lagre scale integrated circuit (VLSIC), and interconnecting of when being circular layout interface port output is described.The very lagre scale integrated circuit (VLSIC) device represents that with numbering (96), (98), (100) and (102) they are called as " subordinate device ".Each subordinate device (96-102) can be finished different functions, and these functions are to be mutually related.Yet each circuit also can be finished incoherent fully independently function mutually.Represent with signal bus (103) in other parts of circuit and the functional interconnection between all the other parts of this system.When functional mode, the transfer of data between the device (96-102) is only carried out on signal bus (103), and this bus can be the layout of any interconnection.When test mode, the funtion part of subordinate device and signal bus (103) are isolated, thereby the subordinate device can not interact.

As mentioned above, the interface circuit (30) of each subordinate device (96-102) comprises four circuits: two holding wire S1 and S2, a clock incoming line CK and transmit the attention output AT of error message.Holding wire S1 and S2 are the bidirectional linked list transmission line, and this line can receive or send serial data.Interface circuit allows subordinate device (96-102) to be linked to be loop configuration, receives data or to its dateout from the holding wire of holding wire S1 and S2.These data are serial form, thereby only need single line.In addition, the interface circuit in each subordinate device (96-102) can determine whether receiving or sending data on circuit S1 or the S2, thereby can enter data into arbitrary holding wire gateway.As will illustrating below, this has two advantages, and promptly data can transmit on either direction around ring, and whether holding wire S1 and S2 be oppositely unimportant.

As mentioned above, the network of Fig. 4 is linked to be loop configuration, with the end of subordinate device (96) at ring, and with the other end of subordinate device (102) at ring.The S1 pin of interface connector (104) is linked in the S1 gateway of subordinate device (96) by line (106).The S2 gateway of subordinate device (98) is linked in the S1 gateway of subordinate device (98) by interconnection line (108).In a similar manner, the S2 gateway that subordinate device (98) is linked by interconnection line (110) in the S1 gateway of subordinate device (100), and the S2 gateway of linking subordinate device (100) by interconnection line (112), the S1 gateway of subordinate device (102).The S2 pin of interface connector (104) is linked in the S2 gateway of subordinate device (102) by interconnection line (114).Common node (116) is all linked in the AT gateway of each subordinate device (96-102), and links the AT pin of interface connector (104) by interconnection line separately.Common node (118) is all linked by interconnection line separately in the CK gateway of each device (96-102), and links the CK pin of interface connector (104) again.For making network work, four pins of interface connector (104) are linked test/safeguard controller (120).Controller (120) can be to be used for the outer processor of test component respectively, maybe can be the integral part of controlling the system of subordinate device (96-102) self-test feature and maintenance features according to the present invention.

The interface gateway of each subordinate device (96-102) (as used in Fig. 4 network) allows to finish many different computings on very lagre scale integrated circuit (VLSIC).As mentioned above, a kind of mode is a self-test feature, and wherein all subordinate devices all place self test mode to have fault still normal to determine whether arbitrary device.As the arbitrary device in the network fault is arranged, then go up output one signal indicator spare and lost efficacy at AT node (116).Because all devices all are that a network is common, a component failure will cause the inefficacy of whole network.Yet second mode or diagnostic mode allow each the subordinate device (96-102) in the network is carried out single test, thereby can make decision to the concrete parts that must change.

The test of subordinate device determines whether the functional circuit blocks on certain device is work when self test mode.Yet this is the interface of test between the different components on integral unit that provides such as the circuit board not.For the ease of carrying out the test of this kind pattern, the diagnostic program in the microcoding read-only memory designs to such an extent that can be used in the signal that other devices in the given network export and finish predetermined test.For example, if do not record component failure then signal that pattern generator on the certain device or read-only memory come will produce, and by relevant functional circuit signal is handled, and be sent to the output pin of this device, so that receive and handle by another device.Certainly, this need interact between different diagnostic programs, and forms second level test.Advanced diagnostic program is to customize for a certain core assembly sheet in the network.Automatically signal excitation can be used by testing/safeguard controller (120) in transition or it from the second level test that carries out the transition to interactive testing between the different components in network in the test of the first order of self-test on the chip.As lean out inefficacy, then this thing can be tied (116) at AT and go up indication, thereby shows that fault occurs in the interface between the different components in the network rather than occurs in chip itself.By finishing this more senior test, can measure other failure mode.

Remove outside the self-test, each subordinate device also have by controller (120) selectively addressing ability and receive the ability of data from control bus (32).The form of these data can be the instruction of functional circuit computing, program information or the real data that is input to functional circuit and handles.Chosen subordinate device also can be along control bus (32) loopback one response signal to controller (120), and this will illustrate below.

Further referring to Fig. 4.The transfer of data of each the subordinate device annular structural network makes from arbitrary end of network to network is very convenient, and each the subordinate device in the network can receive data, or absorption data, or forwards the data to the next subordinate device in the ring.The data of this forwarding can be revised (will illustrate below) or directly pass through.Owing to use, select the subordinate device with the function of its relative position on ring according to loop configuration of the present invention.For example, as send data on the pin S1 of interface connector (104), then device (100) will be the 3rd device on the ring.Yet as feed signals on the S2 pin of interface connector (104), then device (98) will account for the 3rd position, so need both know the position of subordinate device on ring, know the direction of signal transmission on ring again, so that determine the subordinate device that a certain subordinate device is " selected ".In case select, just indicate in the device of selecting is built-in that any data that after this are placed on the bus will only be absorbed by this device.When another device is selected, this mark is resetted.

Instruction is all waited in beginning, all devices under " free time " state.Come the individual selection information encoded signals that has then on the bus.Each receives the device of this information must at first determine which data accepted among signal gateway S1 or the S2.In case the data of receiving then check these data determine whether device the ring on suitable coding site on.If not, then revise this signal, and be forwarded to the next position on the ring.This kind modification as will illustrating below, is a kind of counting form, wherein revises signal at the device on the primary importance and makes coded number subtract 1 till counting equals zero.For example, if coding site is the coding site of the 3rd device on given side signal transmission makes progress ring, then the encoded radio of signal is 2, revises signal to numerical value 1 by the device on primary importance, and revises signal to value of zero by the device on the second place.Will be at the 3rd locational device with null value as selecting code, and this device is provided with interior selected marker.This device just can receive the data of the relevant computing of the instruction of receiving with slave controller (120) then.

The loop configuration of network allows controller (120) to communicate by letter with the known device on the ring from either direction.This point is very important, because interconnection line breaks one, can not hinder and the communicating by letter of this device.Only need to know that this device gets final product with respect to the position of arbitrary end of ring.In this way, when having only interconnection line to disconnect, the interface circuit of the arbitrary device of perhaps another kind of situation is not worked, and thereby when stoping the transmission of data between the S1 and S2 gateway wherein, can test arbitrary device.

Now referring to Fig. 5.Be shown with the block schematic diagram of the interface circuit (30) on the subordinate device of each very lagre scale integrated circuit (VLSIC) among the figure.As mentioned above, interface circuit (30) is communicated by letter with the loops structure by control bus (32).Holding wire S1 and S2 send serial data, CK signal transmission clock signal, and the internal clock signal of this clock signal and subordinate device is irrelevant.The common operating frequency of this clock signal is more much lower than the frequency of the internal clock signal of subordinate device, so that adapt to long operation between the different components of network.Because the internal clock signal of device can be in the frequency work between 10 to 100 megahertzes, make transfer of data at the holding wire on S1 and the S2 on this frequency synchronously, infinite problem can appear.Thereby use clock signal separately, transmission is asynchronous with respect to the internal clock signal.

S1 and S2 holding wire are imported into data wire and select circuit (121), and which root is sending data among this circuit specified data line S1 or the S2.Data only receive from one of them line, but can be along appointing single line to beam back.In a kind of mode that is called as " passing on " mode, data receive on a holding wire, send on another root holding wire in two holding wires, and when " answer " mode, data are returned along the single line that receives.Data wire select circuit [121] allow on holding wire with wherein be connected and throughput direction irrespectively transmits signal.

In case holding wire S1 or S2 that data wire selects circuit [121] to select data to send thereon are about to data and are sent to chip selection control [122] by transmit data line [124].Data are selected control circuit [122] to send back data wire by data conveyer line [126] from chip and are selected circuit [121].Data wire selects circuit [121] to select control circuit [122] to control by control line [128] by chip, so which root is a reception line wherein among definite line S1 or the S2, and having data to transmit on any single line, this will see that data are forwarded or send back to controller [120] and decide.

The data that choose circuit chip [122] inspection is received, explain information wherein, handle these data then, the data of receiving can comprise three kinds of information, i.e. " selection " information, " overall self-test " (" Global Self-Test ") information and " selecting device at last " (" Last Selected Device ") information.As information is " selection " information, checks that then the phase ortho position is relevant with receiving device with the selection information that determines whether to encode, and as irrelevant, then revise data and is forwarded to next contiguous subordinate device by loop configuration.As encode and select the Information Selection receiving device, selected marker then is set, and absorption information.When information is " overall self-test " information, then begin self test mode, and transmit this information.As information is " selecting device at last " information, then checks the selection marker of receiving device, as putting, then absorbs these data; Otherwise data are forwarded to next contiguous subordinate device by loop configuration.

Chip selects control circuit [122] to link to each other with synchronous circuit [130], this synchronous circuit provide the difference of the remainder of interface circuit [30] and chip import with export between be connected.Synchronous circuit [130] provides many outputs, is controlled at chip and selects binding between the remainder of control circuit [122] and chip, and instruction also is provided and transmits data between loop configuration and subordinate device.

In order data to be sent to the subordinate device and, need to provide the sign that is called " data go into to occur " (" DATA IN PRESENT ") and " data appearance " signal from wherein sending out." data go into occur " signal indication chip is selected, and has been ready to receive data, and " data appearance " signal, and then designation data is comprised among the interior register in the subordinate device, so that export on S1 or S2 holding wire." data are gone into " end is used for receiving the data of selecting control circuit [122] from chip, and " data go out " end is used for sending data to chip from the interior register of subordinate device and selects control circuit [122], so that be sent on S1 or the S2 line.Also provide other additional signals.Wherein " beginning self-test " signal indication (after excitation) self-test feature will begin; Error message is provided by " mistake " signal, the AT line of this signal enabling loop configuration.Also provide " internal clock " signal, synchronous reference signal is offered synchronous circuit [130].

Now referring to Fig. 6.Fig. 6 is the waveform that the bit protocol of the serial data on holding wire S1 and the S2 is used.Waveform [132] is represented clock signal C K, and this signal sends to each the subordinate device on the loop network.The frequency of CK signal can be about 1 megahertz, and the internal clock frequency of subordinate device can be between 10 to 100 megahertzes, and perhaps even higher, the used form of serial transmission is called " dibit " transfer of data.This kind transmission form utilizes the group of two binary logic positions to define four kinds of states.These four kinds of states are " free time " (" Idle "), " selection ", and " 1 " reaches " zero "." free time " two attitudes are by two adjoining logical one position definition, " selection " two attitudes are by two adjacent logical zero position definition, " 1 " two attitudes are defined by a logical zero and the logical one followed later, and " zero " two attitudes are defined by a logical one position and the logical zero position of following later.

Waveform [134] is represented the type sequence of two hytes, and in order to obtain reference signal, " idle two attitudes are generally the sequence of a logical one position, and will determine frame of reference when the transition to the logical zero position takes place.This occurs in when " selection " two hytes or the generation of " 1 " two hytes, and the edge transition of serial data occurs in the back along last of CK signal, and the sampling of the logic state of serial data stream waveform [134] is then synchronous with the forward position of CK waveform [132].This is represented by the sampling pulse in waveform [136].In waveform [134], first three sampling is corresponding to three logical one positions of representative " free time " two attitudes.When waveform [134] when level is done transition, provides reference point so that constitute two hytes to logic " low " with " free time " attitude.As mentioned above, this occurs in when " selection " two hytes or the generation of " 1 " two hytes.In waveform [134], in preceding two logical bit of " free time " two attitude back all on the logical zero level, with definition " selection " two hytes.Next two logical bit are on logical zero and logical one level, with definition " 1 " two hytes.Next sequential bits is the logical one level, and its back follows the logical zero level with definition " zero " two hytes.

Information produces by testing/safeguard controller [120].On any given time, have only an information to occur.If an informational needs meets with a response from the subordinate device of selecting, then test/safeguard controller [120] must be before giving another information wait-for-response.As mentioned above, test/safeguard controller [120] and can send three types information.They are that " selection ", " overall self-test " reach " selecting device at last " (LSD) information." selection " information comprises address information and device special order.LSD information includes only the device special order, and nearest LSD device is the implicit address of this instruction." overall self-test " notifies all subordinate devices to enter self test mode.

" selection " information with the back heelstrike " selection " two hytes of location section begin, be the special message segment of device that comprises special order then.This address comprises n-1 " zero " two hytes, follows " 1 " two hytes thereafter.This address is used for n subordinate device in the loop configuration.As described below, each the subordinate device in the loop configuration comes the modified address section by removing " zero " two hytes.The selection information that is modified is forwarded to subordinate device next adjacent in the loop configuration then.At the end of the information of selection, a series of " free time ", two hytes were pointed out the end of information.

It is that " 1 " two hytes then are the special message segments of device that LSD information begins, and ends up with " free time " two hytes then.As described below, LSD information is only absorbed by device work or that select, and this device had received selection information in the past.After selection information was received, selected device was put selected marker.Unless put selection marker, otherwise the subordinate device just is forwarded to LSD information next contiguous subordinate device in the ring, till running into the device of putting selection marker.This selects the device absorption data, and does not transmit data.

Overall situation self-test information is made up of continuous " selection " two hytes, and finishes with a series of " free time " two hytes.After receiving continuous two hytes, produce a signal in response, and self-test is begun.Then " overall self-test " information is forwarded to subordinate device next adjacent in the loop configuration, thereby all devices in the loop configuration all receive " overall self-test " information.

For selector, n-1 " zero " two hytes and " 1 " two hytes are followed in " selection " two hyte back of transmission, and wherein n is the position of selecting device on the ring.Each subordinate device responds to " selection " two hytes followed by the state of " selection " two hytes by checking.If first liang of hyte is " zero " two hytes, then with signal forwarding.Yet, be " 1 " two hytes if directly follow two hytes of " selection " two hytes, the subordinate device identifies it and controls for selecting, and puts selection marker for this subordinate device.When directly and then two hytes of " selection " two hytes are " zero ", then interface circuit (30) is at first revised this signal before sending it to next adjacent chips, and the mode of this kind modification is to remove " zero " two hytes in a string " zero " two hytes.For example, if selection mode back and then two " zero " two hytes and " 1 " two hytes, then to discern it be non-selection code to the subordinate device, and this sign indicating number is spread out of.Yet, this signal will be modified and make " selection " two hyte back with " zero " two hytes, be " 1 " two hytes then, it is non-selection sequence that next subordinate device is discerned this selection sequence, and remove remaining " zero " two hytes to code revision after, this sequence is passed to next contiguous device, and like this, " 1 " two hytes are just directly followed in " selection " two hyte back.Next contiguous chip, promptly the 3rd chip in the ring identifies it for selecting signal.Thereby the 3rd subordinate device is selected with two " zero " two hytes and " 1 " two hytes representative in " selection " two hyte back in ring.The quantity of 0 two hytes can be regulated between " selection " two hytes and " 1 " two hytes, and this depends on the quantity of the subordinate device that must cross before the subordinate device that arrival desires.

After given subordinate device identifies " selection " two hytes, below just with a information with the beginning of " 1 " two hytes.In case a device is selected, then it rests on the state of selecting, till it detects selection sequence to another device.The device of selecting can be accepted many information of being separated by " free time " two hytes.Usually, " 1 " two hyte back of beginning and then illustrate the instruction of needed action, and data can be followed in its back then.Each subordinate device is formulated instruction and data segment structure according to predetermined pattern.When " free time " when state exists, always the response data that will read on ring is sent back to, and this response data is always to select the side of sequence signal to return in the opposite direction with sending.

Now referring to Fig. 7.It among Fig. 7 the block schematic diagram of the interface circuit of Fig. 5.Every single line is linked the input of buffer (138) separately and (140) respectively in the S1 of control bus (32) and the S2 holding wire.The D-input of trigger (142) is linked in the output of buffer (138), and links the A input of orientation detection circuit (144).The D input of trigger (146) is linked in the output of buffer (140), also link the B-input of orientation detection circuit, the input end of clock of trigger (142) and (146) and the clock of orientation detection circuit input all passing through non-inverting buffer (148) are linked from the next CK signal of sets of lines (32), and the output of this buffer is designated as " external clock " (EXT CK).

The Q-of trigger (142) is input to an input that is designated as " 1 " of multiplexer (150).The Q-output of trigger (146) then is input to another input that is designated as " 0 " of multiplexer (150).The Q-output of orientation detection circuit (144) is linked in the control input of multiplexer (150).Orientation detection circuit (144) determines which single line has entering signal among holding wire S1 or the S2, and after making decision, control multiplexer (150) is selected the Q-output of relevant in trigger (142) and (a 146) trigger.

The output of multiplexer (150) is input to the D-input of trigger (152), and an input that is designated as " 2 " of five input multiplexers (154) is then linked in the Q-output of trigger (152).EXT CK is linked in the clock input of trigger (152).Four remaining input terminals of multiplexer (154) are designated as " 0 ", " 1 ", " 3 " reach " 4 ".Zero-input terminal is linked the logical zero reference level.One-input terminal is linked the logical one reference level." 3 " input is linked the output of negative circuit (156), and " 4 " input is linked node (158), and node (158) is linked the input of inverter (156).

The MUX output of interface control circuit (160) is linked in the control input end of multiplexer (154).Interface control circuit (160) determines which will be from wherein output in the multiplexer input.As described below, the data of being exported by trigger (152) can directly maybe can replace with " 1 " two hytes or " zero " two hytes by multiplexer (154).In addition, can utilize multiplexer (154) to be chosen in its " 3 " and reach dateout on " 4 " input.

The D-input of trigger (162) is linked in the output of multiplexer (154), and the Q output of trigger (162) is then linked the input of negative circuit (164) and (166).The S1 holding wire is linked in the output of negative circuit (164), the S2 holding wire is linked in the output of negative circuit (166), inverter (164) and (166) are all triple gate, the output that two input multiplexers [168] and two input multiplexers [170] are linked in this control input respectively, inverter [164] reach [166] or holding wire S1 and S2 are presented high impedance or drive this line with logic low or logic high signal.

Each all has an input and an input that is designated as " 0 " that is designated as " 1 " two input multiplexers [168] and [170].The Q output of trigger [172] and " 0 " input of multiplexer [170] are all linked in " 1 " input of multiplexer [170] and " 0 " input of multiplexer [168].The Q-output of trigger [174] is linked in " 1 " input of multiplexer [168].The Q-output of orientation detection circuit [144] is linked in its control input.

The output of interface control circuit [160] is linked in the D-input of trigger [172], and this output is designated as RLY, and corresponding to passing on function.The D-input of trigger [174] is linked and is designated as RPY, and corresponding output of answering function.The work of trigger [172] and [174] is which single line receives from what multiplexer [154] came and selects data among control signal wire S1 or the S2.For example, can in the S1 input, receive data,, and on holding wire S2, export directly by multiplexer [154].Otherwise, can on holding wire S2, receive data, and on holding wire S1, export.Trigger [162], the inversion signal of EXT CK is linked in the clock input of each trigger in [172] and [174], and it is handled by inverter [176].

Interface control circuit [160] is checked the logic state of the data bit in the input of trigger [152] and output.The DIN input of corresponding input data bit is linked in the input of trigger [152], and the output of trigger [152] is linked and is designated as " B2 " and corresponding to the deputy input of data.Nationality helps the delay time one-period of EXT CK clock signal of data, and interface control circuit can be seen two logic states of data flow simultaneously.In this way, it can determine whether " selection " dibit group occurs.If " selection " two hytes are determined by two continuous logics " 0 " occurring, multiplexer [154] transmission data that then no thoroughfare.Interface control circuit (160) is checked next continuous logic position so that determine its logic state then.If logic state has been pointed out " 1 " dibit group and occurred, then be enhanced logic high corresponding to the SELS output of selecting (Select Set) signal is set.This output is imported into " set " (" Set ") input of selection marker circuit (178).The output of this circuit is input to the SEL input of interface control circuit (160), and thereafter, interface control circuit (160) is always to indicate about whether it be the device that is selected on the ring and no matter data are to be input to device on the S1 holding wire or on the S2 holding wire.

If the data immediately following selection mode are " zero " two attitudes, interface control circuit (160) identifies selects sequence to use for another chip, and it finishes two functions.At first, it produces the SELR signal and outputs to selection marker circuit (178) with the indication reset function, and the state that changes the SEL signal is so that provide the indication in this future that subordinate device is not selected.The second, revise data flow, the form of this kind modification is to leave out " zero " two hytes and replace " selection " two hytes.This kind replacement realizes by producing two continuous logic zero data positions with multiplexer (154)." selection " two hytes of this new generation send by trigger (162) then, and two hytes of the remainder in the sequence are and then selected in the back.The result deletes " zero " two hytes from select sequence.

When revising the selection sequence, it is outputing on the holding wire of receiving data on the relative holding wire.This is to transmit kinetic energy, and it forwards the data to the next subordinate device in the ring.Forwarding capability uses the RLY output that comes from interface control circuit (160) to realize, this output is selected by a suitable multiplexer in multiplexer (168) and (170), so that start driver (164) or (166) of corresponding relative signal line S1 or S2, and with this holding wire as its output signal line.

Remove on holding wire S1 or S2 by testing/safeguard outside " selection " order or " selection " information that controller (120) sent, this controller (120) also can send " overall self-test information " to reach " selecting device at last " (" LSD ") information." overall self-test information " is a special information, and the whole devices of its commander on ring are finished built-in self-test, as previously discussed.LSD information includes only the device special order and nearest " LSD " is implicit address.Can also can start self-test by carry information though test/safeguard controller [120], the subordinate device can only send response message.The form of these response messages is to start the AT line with misdirection information, and sends response message back to along loop configuration, and this will illustrate below.

LSD information begins with " 1 " two hytes, and then comprises the special message segment of device of data then.The end of information is the end of " free time " attitude with the indication information data.When information is placed on the bus, all devices of interspersing are all put selection marker circuit [178] in the device front of selecting and in ring, transmit output RLY so that the device that is not selected will start, transmit data to next adjacent subordinate device by the device that is not selected.This will proceed to the device that is selected and receive till the data, and the device that is selected is a device of being put selection marker by circuit [178].

" overall self-test information " is made up of continuous " selection " two hytes, and with the ending of the signal of pre-charge, this signal is one " free time ", two hytes or a series of logical one level, the response message of coming from the subordinate device be a kind of logically follow before the information of " selection " or LSD information.Removing the destination is to test/safeguard outside the controller [120], and response message is identical on form with LSD information.When working in this way, start the answer output RPY of interface control circuit [160], so as to export a signal to multiplexer [170) zero-input terminal and the one-input terminal of multiplexer [168].It is very important that the response that makes the subordinate device is returned along the same path that receives data, because might have the subordinate device of higher position to break down on ring.The subordinate device that is selected receives this fact of data and means that communication path is intact, and the out of order possibility of orientation detection circuit on the middle subordinate device is very little, thereby allows to get back to controller [120] by middle subordinate device transmitted in both directions.

The AT line can be worked in the mode of two wrong identification.First kind of mode is that the AT line remains on logic low, if when having one to lose efficacy in the top device, just is pulled to logic high.The second way and be that preferable mode is when self-test is initial is moved the AT line to logic high, and each subordinate device can both maintain logic high with the AT line.After the self-test of given subordinate device is finished, AT line " release ", when having only one or more subordinate devices not discharge the AT line, the AT line just can remain on logic high.In this way, test controller [120] only needs supervision AT line to finish self-test to determine when, and whether finishes self-test.Remain on high level as the AT line, then point out wrong.Although show the concrete device of this mistake and do not know that system is inoperable, must be repaired.When maintenance mode, each subordinate device can be by independent addressing, and controls it and finish self-test, so just can determine out of order device.

For all the other positions with chip interrelate, need adjunct circuit to make self-test initial, communicating data is to this place, from this outgoi8ng data and reception error message.In order to make these operations synchronously, must produce a gating signal STRB.Gating signal is produced by clock signal EXTCK, and this clock signal is input to three triggers [180], and [182] and [184], all triggers are all synchronous by the internal clock (being designated as INT CK) of chip.The D-input of trigger [182] is linked in the Q-output of trigger [180], and the D-input of trigger [184] is linked in the Q-of trigger [182] output.The input with door [186] is all linked in the Q-output of the Q-of trigger [182] output and trigger [184], make this with the output of door on produce gating (STRB) signal.Because INT CK signal frequency is high more a lot of than the frequency of EXT CK signal, the Q-output of trigger [182] will remain on the logic high long enough time, so that with the anti-phase Q-output of this level of clock synchronization up to trigger [184].At this moment, gating (STRB) signal enters logic high, and the time that remains on this level is a clock cycle of INT CK signal, becomes logic low then.This in fact provide one with the synchronous pulse in clock signal edge of INT CK signal.

In case draw synchronous gating signal from slower EXT CK signal, can finish other functions such as output and input data.During the input data these data are gone up input at " data are gone into " line DIN, during dateout, on the DOUT output line, export.The output of multiplexer [150] is linked in the DIN input, so that receive the input data from it.The D-input of trigger [188] is linked in DOUT output, and node [158] is linked in its Q-output, and it is synchronous to make clock signal by EXT CK signal.

The dateout that interface control circuit [160] control is selected dateout and is sent back to controller [120] as answer.This operation signal occurs with the data input, and (it is synchronous that signal (" DOP ") appears in " DIP " and data.The DOP signal is the output signal of coming from all the other positions of chip, and it is transported to trigger [190] and [192] of series connection.The DIP signal is produced by interface control circuit [160], and by making its remainder with chip synchronous with door [194], should link the DIP output of interface control circuit [160] with an input of door, should import with another of door and then link gating signal.As mentioned above, have only when device to be selected and data strobe signal is done the time spent, DIP and DOP signal just all are " really " (" true ").

For the operation of self-test feature synchronously, produce a ST signal corresponding to the enabling signal of self-test feature by interface control circuit.This signal is input to the input with door [196], and its another input is then linked gating signal.When receiving " overall self-test " information, this signal is brought up to logic high.For error message, the AT signal is exported by chip, and is input to the input that presets of two triggers [198] of connecting and [200], and the both is by EXT CK signal Synchronization.The gate control end of inverter gate [202] is linked in the Q-output of the output trigger of trigger [198] and [200].The logical one level is linked in the input of inverter gate [202], and the AT holding wire of circuit [32] is linked in its output.The logical zero level is linked in the D-input of the input trigger of trigger [198] and [200].When work, the AT line is used for reporting in many ways the dendrometry effect of testing oneself.At first when test, the AT signal is work, is successful as test, and then this signal is released; Promptly all are changed to operating conditions from the AT output signal that the subordinate device comes when testing, reach chip generation-AT signal when EOT, this signal passes on by trigger (198) and (200), so that the operating conditions on the AT holding wire in the release output line (32).Perhaps another situation be only when test is failed the AT signal just can be activated.If in used mode, component failure causes failed device to keep the AT line in operating state, then tests/safeguard controller (120) but the device of poll on loop configuration, and a device in forcing device discharges the AT signal.This permission is tested/is safeguarded controller (120) and determines which subordinate device lost efficacy in the loop configuration.

Now referring to Fig. 8, wherein figure is shown with the block schematic diagram of selection marker circuit (178).The selection of selection marker circuit (178) input is linked or an input of door (204), and the output with door (206) is then linked in its another input.With the Q-output that selection marker circuit (178) is linked in an input of door (206), its another input is linked the input that resets by inverter (208).Or the output of door (204) links the D-input of trigger (210), and the Q-output of selection marker circuit (178) is linked in its Q-output.Trigger (210) is by the EXTCK signal Synchronization.In when work, the SELS signal on " set " input of selection marker circuit (178) by trigger (210) regularly, and the SELS signal on it resets input is only patrolled on its Q-exports when seizing high level when previous state, just changes its state.

Now referring to Fig. 9, the block schematic diagram of direction as shown detection circuit (144) wherein.The A-of circuit (144) input is input to a input with (212) by inverter (214).The B-input of circuit (144) is input to an input of NAND gate (216) by inverter (218).The C-that links circuit (144) with another input of door (212) and NAND gate (216) imports.Link with the output of door (212) or an input of door (220), the output with door (222) is linked in its another input.Or the D-input of trigger [224] is linked in the output of door [220].Import the output of linking NAND gate [216] with one of door [222], the Q output of trigger [224] is then linked in its another input.The Q-output of trigger [224] is corresponding to the Q-output of orientation detection circuit [144].Trigger [224] is by EXT CK signal Synchronization.Except that " allowing operation " (" Enable ") signal, the signal in the A-input of orientation detection circuit [144] makes data pass through trigger [224] when work.Perhaps another situation is when producing " allowing operation " signal, and the output that the data input in the B-input is produced is anti-phase by NAND gate [216], and this oppisite phase data output signal drives an input with door [222].When only the output in the Q-output of trigger [224] occurs, just produce output with door [222].

Now, wherein illustrate the work flow diagram of interface circuit [30] and the interface control circuit [160] in interface circuit [30] referring to Figure 10.Whether order is initial from beginning square [226], and then to decision square [228], occur with specified data.As mentioned above, holding wire S1 and S2 remain on high logic level, till data are sent out.Detect logic low and show that transfer of data is initial.If lean out logic low, then program is along " Y " path flows.If do not lean out logic low, then program flows to decision square [230] along " N " route.Decision square [230] is determined as whether " signal appears in data " is high level (DOP), if high level shows that storage has data in chip, chip is sent these data back to by former information request.

If the DOP signal is not a high level, then program is got back to the input of decision square [228] along " N " route, as the DOP signal is high level, then program along " Y " route flow to functional block [231] wherein " 1 " dibit group be sent back to test controller, point out that response message is initial.In this mode, with output driver [164] and [166] set, to select the received signal line of holding wire S1 and S2.Program flows to function square [232] then, along the same route that receives data data is sent back to and tests/safeguard controller (120).Program enters decision square (234) then, determines whether that the DOP signal is still high level.As long as still within device, then the DOP signal will maintain high logic level to data.When transfer of data was finished, the DOP signal became low level, so program flow back into " sending data " function square (232) along " N " route, till all data all were sent out, it got back to the input of decision square (228) at that time.

Occur at decision square (228) as data, then program flows to the input of function square (236) along " Y " route, with second of two hytes in the output that receives trigger (152).Program flows to and determines that square (238) is " 1 " dibit group with two hytes that determine whether to receive then.If two hytes are " 1 " two hytes, then this shows has information to occur.In this mode, flow process flows to decision square (240) along " Y " route, to determine whether to put selection marker.If put selection marker, this shows that device is selected, and the program of reaching flows to function square (242) along its " Y " route, with absorption data.Program flow goes back then, occurs to have determined whether more data.Be not set as selection marker, then program flows to function square (244) from decision square (240) along " N " route, so that data are transferred to next subordinate device in the loop configuration.Program is got back to the input of decision square (228) then, to have determined whether that more multidata occurs.

If determining second in decision square (238) is logical zero, i.e. " selections " two hytes, program enters function square (246) along " N " route, with inspection two hytes thereafter.If two hytes are " selection " two hytes thereafter, show that then self-test is initial, program flows to function square (250) along " Y " route, the beginning self-test.After self-test was initial, program flow to function square (252), and " selection " two hytes of transmitting thereafter arrive the interior next subordinate device of ring.Show that the initial information of self-test is " overall self-test " information, it comprises a string " selection " two hytes.Because as mentioned above, after its identification, leave out first " selection ", two hytes, so the initial and forwarding capability of the indication self-test of " selection " two hytes thereafter, this function is forwarded to adjacent subordinate device for " selection " two hytes with remainder.In sequence, only need the quantity of " selection " two hytes enough to get final product above the quantity of when all the subordinate devices are handled, being left out.Program flow is got back to the input of decision square (228), the data of products for further then.

If two hytes thereafter are not " selection " two hytes, then program flows to the input of decision square (254) along " N " route from decision square (248), so that determine whether this two hyte is " 1 " two hytes.If it is " 1 " two hytes, then this shows that device is selected, so program flows to function square (256) along " Y " route, makes selection marker set, flows to function square (258) then, absorbs data thereafter.After absorption data, program flow is got back to the input of decision square (228), waits for new data.

If position thereafter is not " 1 " two hytes, program flows to the input of decision square (260) from decision square (254) along its " N " route, to determine whether two hytes thereafter are " zero " two hytes.As thereafter two hytes is not " zero " two hytes, this indication " free time " state then, and program flow is got back to the input of decision square (228).If yet this two hyte is " zero " two hytes, program flows to function square (262), and sign is resetted, and points out that one selects sequence because " zero " two hytes are followed " selection " two hytes, and wherein present chip is not the chip of selecting.Thereby, selection marker is resetted, program flows to function square (264) then.In function square (264), nationality helps check the position immediately following " selection " two hytes, determines that this position is meant the logical one of " zero " two hytes, also is meant the logical zero of " 1 " two hytes, revises data then as mentioned above.Because " zero " two hytes are immediately following " selection " two hytes, it is changed to " selection " two hytes, then the data flow that is modified is forwarded to subordinate device next adjacent in the ring, as pointed by function square (266).After transmitting these amended data, program is got back to the input of decision square (228), products for further data or selection sequence.

In a word, this place provides the very lagre scale integrated circuit (VLSIC) device of full self-test, and this device is combined in pattern generator and identification circuit and functional circuit blocks in one integral device.Control circuit also is provided, and the work of this control circuit control pattern generator is input to functional circuit blocks with predetermined pattern, to obtain predetermined response to, is input to identification circuit.Identification circuit is compared dateout with predetermined result.If the data of being exported by functional circuit response input test figure fail to provide with the result who expects really compare, determine that then device has fault, and export a signal at the special use end and indicate.One end points that separates is exclusively used in control signal, beginning self-test function, thereby two pins of minimum needs make the self-test of integral device initial, and this test result transmitted get back to external devices.

Remove outside the self-test feature, also link to each other, come the work of controlled function circuit block, to test its discrete component with safeguarding device outward with the test controller that functional circuit blocks is combined into one.Data can receive from outer device, and finish specific function with functional circuit blocks, and dateout is to outer device.

Each has the integral device of self-test feature can connect into loop configuration, and wherein each device all has input port and delivery outlet.Data are input to one of them gateway, and with the delivery outlet of other gateways as the input port of linking adjacent devices, thereby formed loop configuration.The data route is the form of series connection transmission.When data are input to certain device, with data time-delays so that can check two phase ortho positions, and according to wherein the information of being included in these data or be forwarded to next adjacent devices, or transmit again after revising.This revises and allows to select certain device by the position on the loop configuration.If this device is not selected, then select number progressively to successively decrease preceding code, till counting equals zero, indicate the device of selecting.

Although described most preferred embodiment in detail, should be understood that and can make many variations according to spirit of the present invention, replacement and modification, these variations, replacement and modification all drop on by within the defined invention scope of following claim.

Claims (21)

1, a kind of self testing circuit comprises:

One from the external system receiving inputted signal and according to being linked to be the functional circuit blocks that whole predetermined function is handled the input signal of receiving with this functional circuit blocks, and above-mentioned processed input signal outputs to the said external system from the above-mentioned functions circuit block;

Produce the graphics device that the resolution chart signal is input to the above-mentioned functions circuit block;

Recognition device, this device receives the output processing signals of above-mentioned functions circuit block, output signal and presumptive test standard are compared, and when between the output signal of above-mentioned functions circuit block and above-mentioned presumptive test standard, do effective ratio than the time, export effective comparison signal;

Control the control device that above-mentioned graphics device response receives outer self-test initial signal and produces above-mentioned resolution chart signal according to the presumptive test program;

Above-mentioned functions circuit, graphics device, recognition device and control device are (Self-contained) integral unit of providing for oneself;

Above-mentioned control device detects the output of above-mentioned recognition device, and if when not detecting effective comparison signal for all above-mentioned resolution chart signals that produced according to above-mentioned presumptive test figure by above-mentioned resolution chart device then export a fault-signal;

Above-mentioned integral unit linked to each other with external system state the interface arrangement of fault-signal to this place from concurrent the serving of the above-mentioned self-test initial signal of this reception, above-mentioned interface arrangement is exclusively used in the self-test of above-mentioned functions circuit.

2, self testing circuit as claimed in claim 1, wherein above-mentioned interface arrangement is with respect to above-mentioned integral unit asynchronous working.

3, self testing circuit as claimed in claim 2, wherein above-mentioned interface arrangement receives the serial data of coming from above-mentioned external system and above-mentioned control device control above-mentioned functions circuit block and receives above-mentioned external system data from above-mentioned interface arrangement and handle, and above-mentioned control device is got back to above-mentioned external system by the output of above-mentioned interface arrangement control data with serial form.

4, self testing circuit as claimed in claim 1, wherein the above-mentioned predetermined function of above-mentioned functions circuit block comprises a plurality of functional performances.

5, self testing circuit as claimed in claim 4, wherein above-mentioned controller is finished a function of being desired in its a plurality of functions in order to control above-mentioned functions circuit block according to above-mentioned presumptive test program.

6, self testing circuit as claimed in claim 1, the generation of wherein above-mentioned self-test initial signal make above-mentioned control device above-mentioned presumptive test program the duration start a corresponding attention, the generation of above-mentioned fault-signal is kept above-mentioned attention in working order so that determine fault with the appearance of in working order attention.

7, self testing circuit as claimed in claim 1, wherein above-mentioned control device produce the resolution chart signal of the corresponding above-mentioned generation of above-mentioned testing standard.

8, self testing circuit as claimed in claim 1, wherein the above-mentioned functions circuit block is that the digital above-mentioned test signal that reaches comprises numerical data, above-mentioned graphics device comprises the storing apparatus that is used for storing a plurality of digital data words and available above-mentioned control device addressing, and the addressing of above-mentioned storing apparatus transfers out to be selected numerical data and be input to the above-mentioned functions piece to handle.

9, self testing circuit as claimed in claim 1, wherein above-mentioned control device comprises:

Storage is with the memory of the above-mentioned predetermined test program of diagnostic program form appearance;

Carry out the final controlling element of above-mentioned diagnostic program with predesigned order; And

Survey the output of above-mentioned identification circuit and determine whether to receive the sniffer of effective comparison signal at above-mentioned diagnostic program end;

If the end of above-mentioned diagnostic program is not received effective comparison signal and is just produced above-mentioned fault-signal.

10, self testing circuit as claimed in claim 1, wherein above-mentioned recognition device utilize data compression technique with data compression and with the more above-mentioned compressed data of above-mentioned predetermined testing standard.

11, self testing circuit as claimed in claim 1 also comprises the above-mentioned functions circuit block and receiving inputted signal is isolated so that the device that functional interface and external system are isolated.

12, a self-testing integrated circuit comprises:

The semiconductor encapsulation is in order to be placed on integrated circuit the inside and to have a plurality of signal pins to be used for linking to each other with external system;

One functional circuit blocks, having input and output is used for receiving from the next data of above-mentioned external system, according to the above-mentioned functions circuit block intrinsic predetermined function handle above-mentioned reception data as the data output of handling, the input of above-mentioned functions circuit block and output are connected with above-mentioned external system by the above-mentioned signal pins of function system work special use;

One pattern generator is input to the above-mentioned functions circuit block in order to produce a plurality of resolution chart data;

Control device is in order to the feature operation of control above-mentioned functions controll block and control above-mentioned pattern generator and produce and select the resolution chart data and handle above-mentioned selection resolution chart data by the above-mentioned functions circuit block and export as it;

Above-mentioned resolution chart data selected by above-mentioned control device and according to the feature operation of presumptive test program control above-mentioned functions controll block, above-mentioned presumptive test program is initial after receiving the self-test initial signal from above-mentioned external system;

If recognition device is in order to the output that receives above-mentioned functions controll block and will export and compare with the expected result of being scheduled to and make effective ratio by above-mentioned recognition device then export effective comparison signal;

The signal that spacer assembly comes from above-mentioned control device in order to response is isolated above-mentioned functions circuit block and above-mentioned external system, and above-mentioned control device is controlled above-mentioned spacer assembly and isolate the above-mentioned functions circuit block when self-test;

Above-mentioned control device is surveyed the output of above-mentioned recognition device and after above-mentioned presumptive test program has been moved, if carry out effective ratio by recognition device according to above-mentioned selection graph data then export an acknowledge(ment) signal; And

Interface arrangement is in order to connecting between above-mentioned control device and outer test controller by the dedicated pin in the above-mentioned signal pins, and above-mentioned outer test controller generation is above-mentioned from initial signal and receive above-mentioned acknowledge(ment) signal.

13, as the self testing circuit of claim 12, wherein comprise at least two pins with the above-mentioned dedicated pin that above-mentioned interface circuit links, pin receives above-mentioned self-test initial signal and a pin sends above-mentioned acknowledge(ment) signal to above-mentioned outer controller.

14, as the self testing circuit of claim 12, wherein the predetermined function of above-mentioned functions circuit block comprises the function of a plurality of cross-correlation, and above-mentioned control device is controlled the combination that all above-mentioned mutual function associated are finished an above-mentioned mutual function associated or above-mentioned mutually relevant function selectively.

15, as the self testing circuit of claim 12, wherein above-mentioned pattern generator comprise store a plurality of test data words and can by above-mentioned control device selectively addressing memory thereby the selection word in the above-mentioned test data word can be input to the above-mentioned functions circuit block and carry out its processing.

16, as the self testing circuit of claim 10, wherein above-mentioned control device comprises:

Store the memory of above-mentioned presumptive test program;

Carry out the final controlling element of above-mentioned presumptive test program output function code, this code is controlled the function of above-mentioned functions circuit block and is controlled above-mentioned pattern generator and export the input of the selection data conduct of above-mentioned resolution chart data to the above-mentioned functions circuit block, and

According to the output of the above-mentioned identification circuit of above-mentioned presumptive test program instrumentation to determine between dateout and above-mentioned presumptive test standard, whether having effective comparison.

17, as the self testing circuit of claim 12, wherein above-mentioned preassigned is produced according to above-mentioned presumptive test program by above-mentioned control device.

18, as the self testing circuit of claim 12, wherein above-mentioned recognition device utilizes data compression technique to compress the data of being exported by the above-mentioned functions circuit block when it is tested, to compare with above-mentioned presumptive test standard.

19, as the self testing circuit of claim 12, the status signal that wherein above-mentioned control device startup one is transmitted by above-mentioned interface arrangement when self-test and the startup of above-mentioned acknowledge(ment) signal are not restarted above-mentioned status signal thereby are provided relevant test ongoing indication.

20, a kind of self-test method of testing the funtion part of the integrated circuit of working in system comprises:

Remove the funtion part of integrated circuit and connecting of this system;

According to predetermined test program generation resolution chart, the funtion part that is input to integrated circuit is handled according to predetermined function;

After resolution chart being handled, the output of functional circuit is compared with the presumptive test standard by functional circuit;

Survey relatively output, if can not make effective ratio between dateout of handling and presumptive test standard after test program has carried out, then produce fault-signal, this output signal outputs to the external devices relevant with integrated circuit;

The execution relatively of the generation of resolution chart and dateout and presumptive test standard forms an integral body with integrated circuit, and it is initial then to be to respond the external signal that the source received outside the integrated circuit and initial.

21, as the method for claim 20, further comprise the function of determining the funtion part of integrated circuit according to test program.

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