JPS61175835A - Information processing system - Google Patents

Abstract

PURPOSE:To decide whether the generation of an illegal channel address has been caused by software or hardware, by constituting a titled system so that a CPU uses an identification number which has been informed from a support processor. CONSTITUTION:A channel address (GA number) from each gate array GA26 is supplied to a support processor 27, inputted in series to a shift register 28, and stores in a RAM29. In accordance with a request of a CPU21, it is informed to the CPU21 through a system bus 24. Stored data of the RAM29 shows the GA number peculiar to each GA26 in the system so as to correspond to a bit, and also, as for the GA26 placed in channels 23-1-23-n, the GA number coincides with the channel address. Accordingly, the CPU21 can recognize the channel address existing in the system by data which has been informed from a processor 27, and when transferring an input and an output between auxiliary storage devices 25-1-25-n, whether the channel address sent out to the channels 23-1-23-n is illegal or not can be checked.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an information processing system having error information collection and error processing functions.

[Technical background of the invention and its problems] As shown in FIG.
, and channels 13-1 to 13-n are connected to system bus 1.
In information processing systems interconnected by C.
Between the P U 11 and the main storage device 12, the CPU 11. !
: Between the auxiliary storage devices 15-1 to 15-n (connected to channels 13-1 to 13-n), and the main storage device 1
If an error occurs during data transfer between the storage device 2 and the auxiliary storage devices 15-1 to 15-0, or during that process, error information is collected. However, in traditional systems,
Since the error information is returned by the hardware where the error occurred, the reliability of the error information is extremely high! There was a problem.

Further, in the above system, when data is written from the CP LJ 11 to the auxiliary storage units fl 15-1 to 15-n, etc., the channels JLt 13-1 to 13-n and the auxiliary storage units [15-1 to Even if an error occurs with 1s-n, the CPU 11 is not notified of the error. Moreover, if you try to collect all the error information including this type of error in each channel 13-1 to 13-n, each channel 1
Since the hardware configuration of 3-1 to 13-n is large-scale, it is difficult to realize.

Now, in the system of FIG. 3, for example, in the process of data transfer between the CPU 11 and the auxiliary storage devices 15-1 to 15-n, a channel address that does not exist in the system is
When signals are sent from U 11 to channels 13-1 to 13-n, channels 13-1 to 13-n do not operate and do not respond. In this case, a timeout is detected in the CPU Ll 11, and error information corresponding to the CPU Ll 11 remains.

However, in conventional systems, illegal channel addresses are either caused by programming errors (i.e. software errors) or hardware defects (
It was difficult to determine whether the problem was caused by a malfunction.

[Object of the Invention] The present invention has been made in view of the above circumstances, and its purpose is to provide an information processing system that can collect accurate and abundant error information.

Another object of the present invention is to provide an information processing system that can correctly determine whether an illegal channel address is caused by a program error or a hardware defect even if an illegal channel address is transferred to a channel. It is in.

[M\l of the Invention] According to the present invention, an information processing system is provided in which various components such as a CPU 1 main storage device and a plurality of channels are interconnected by a system bus.

The above system is provided with a serial bus including a function line, an interrupt signal line, and a serial data bus for serial transfer. Information gathering/processing circuitry is provided. This error information collection/processing circuit is connected to the serial bus. Further, the serial bus is provided with a support processor that controls the error information collection/processing circuit and performs serial data transfer with the circuit via the serial bus. The error information collection/processing circuit also includes an identification number setting switch that sets an identification number for the circuit, and that sets an identification number that matches the channel address when the corresponding component is the above channel. Connected.

The error information collection/processing circuit includes an error information register that stores error information of a corresponding component, and a flip-flop that is set in response to a request from the corresponding component and outputs an interrupt signal to an interrupt signal line. A shift register that inputs and outputs serial data to and from the serial data bus, a decoder that decodes the identification number set by the identification number setting switch and outputs a decoded signal specific to the identification number, and a support processor that connects the function line. An identification number register that stores the identification number transferred via the serial data bus when the is set to address mode, and a flip-flop that is set when the content of this identification number register is the first identification number. means to set the decoding result of the decoder in a shift register and serially transfer the set contents to a supporting processor via a serial data bus; A means for setting the decoding result of a decoder in a shift register regardless of the current state and serially transmitting the set contents to a supporting processor via a serial data bus, and a means for setting the contents of an identification number register and an identification number set by an identification number setting switch. A comparator that detects a match by comparing the , a means for serially transferring the set contents to the support processor via the serial data bus, and when a match is detected by the comparator, the contents are transferred from the support processor if the function line is set to shift-in-function by the support processor. It is equipped with a means for serially inputting data on a serial data bus to a shift register and performing error processing using the input data, and error collection can be performed independently of system operation under the control of a support processor. The structure is as follows.

Furthermore, when a channel address search is necessary, the support processor sets the function line to address mode and sends the second signal to the serial data bus.
serially outputs the identification number of the serial data bus, then sets the function line to shift-out mode, serially inputs the data on the serial data bus, and notifies the CPU of the input contents as necessary. ing. C.P.L.
The data notified to I is an identification number from each error information collection/processing circuit, and if the circuit is provided in a channel, it matches the channel address. Therefore, by using the identification number notified from the support processor, the CPU can determine whether the illegal channel address is caused by software or hardware.

[Embodiments of the invention] An embodiment of the present invention is shown in FIG. 1(a) below.

This will be explained with reference to (b), (c) and FIG.

FIG. 1 (a) shows the system configuration of an information processing system according to an embodiment of the present invention. In the figure, 21 is a CP
U and 22 are main storage devices, and 23-1 to 23-n are channels. CPLI 21, main memory 22, and channels 23-1 to 23-n are interconnected by system bus 24. Auxiliary storage devices 25-1 to 25-n are connected to channels 23-1 to 23-n. The channel addresses (device addresses) of channels 23-1 to 23-n are 1 to n. Note that in this embodiment, n is 12, that is, C in hexadecimal representation.

26 is CPU 21. Main storage device 22. channel 2
A gate array (hereinafter referred to as GA), 27, which is provided in each system component such as 3-1 to 23-n, and serves as an error information collection/processing circuit that collects error information and performs error processing for the corresponding device. is GA26,
26..., and the same GA26, 26...
A support processor that performs serial data transfer between The support processor 27 includes a shift register 28 for serial data transfer, and a storage unit such as RA.
It has M29. RAM 29 is used, for example, to store channel addresses present in the system. Support processor 21 and GA26.26...
are interconnected by a serial bus 30 for serial data transfer.

The serial bus 30 is controlled by the support processor 27, and as shown in FIG. 1(b), includes a 1-bit serial data bus 31, 32, each GA 26, 26, .
It has an interrupt signal line 33 for transmitting an interrupt request from GA26, 26 to the support processor 27, a clock signal line 34 for transmitting a clock signal for operation, and a function line 35. This function line 35 is used to specify the operation mode of the GA 26, 26, . . . Each of the GAs 26, 26, . . . has a shift register 41 for serial data transfer with the support processor 27. Serial data output from the serial input terminal of each shift register 41 is led to the serial input terminal of the shift register 28 in the support processor 27 via the serial data bus 31, and is led to the serial output terminal of the shift register 28 in the support processor 27. Serial data output from the G A 26 is guided to a shift register 41 in each G A 26 via a serial data bus 32 .

FIG. 1(C) shows the configuration of the GA 26. In the same figure,
42 is the 4-bit GA identification number of GA 26.
This is a decoder that decodes a number and activates a decode signal unique to the corresponding GA number among 16 types of decode signals. The GA number is set by a GA number setting switch 60, which will be described later. 44 indicates various interrupts (error interrupts, test request interrupts, etc.) transmitted via terminal 45 from the system component in which G A 26 is placed.
Interrupt flip-flops (set by request)
(hereinafter referred to as interrupt F/F group), 46 is an interrupt F/F
For example, an OR gate (hereinafter referred to as OR) of an oven collector calculates the logical sum of the outputs of the group 44. The active output signal of OR 46 is sent to interrupt signal line 33 at terminal 47 as an interrupt signal.

48 is a 32-bit error information register that stores status information such as error information derived from the system component in which G A 26 is placed through the terminal 45; 49 is the lower 16 bits of the contents of the error information register 48; Alternatively, it is a multiplexer that selects either one of the outputs of the decoder 42. The selected output of multiplexer 49 is supplied to the lower 16 bit field of shift register 41. The upper 16 bits field of the shift register 41 is supplied with the upper 16 bits of the contents of the error information register 48. The serial output terminal of the shift register 41 is connected to the serial data bus 31 via an open collector output driver (not shown) and a terminal 50, and the serial input terminal is connected to the serial data bus 3 via a terminal 51.
Connected to 2.

52 is a 32-bit data register that stores the contents of the shift register 41. The contents stored in the data register 52 are supplied via the terminal 53 to the system component in which the corresponding GA 26 is placed. 54 is shift register 4
An address register 55 stores the lower 4 bits of the contents of 1 (specifically, the GA number), and a comparator 55 compares the contents of the address register 54 with the GA number and detects a match. Each output of address register 54 and comparator 55 is connected to control circuit 56. Control circuit 56 is connected to clock signal line 34 and function line 35 via terminal 57. The control circuit 56 is
The clock signal from the clock signal line 34, the operating mode specified by the function line 35, the contents of the address register 54, and the comparison result of the comparator 55 (
Each part within the G A 26 is controlled according to the match detection result).

A GA number setting switch 60 for setting a 4-bit GA number, which is an identification number of the GA 26, is connected to the terminal 58 of the GA 26. The GA number set by the GA number setting switch 60 is supplied to the decoder 42 and comparator 55 in the GA 26 via the terminal 58. In addition,
In this embodiment, the GA numbers assigned to the GAs 26 placed in the channels 23-1 to 23-n match the channel addresses. In addition, GA number “0” and “F
” is prohibited.

Next, the operation of the above configuration will be explained. Channel 23 now
-1, an error is detected and an error interrupt request is generated. This error interrupt request is
It is supplied to the interrupt F/F group 44 via the terminal 45 of 26,
As a result, the corresponding F/F (flip-flop) in the same F/F group 44 is set. Interrupt F/F group 4 in group 4
When one of the F/Fs is set, the output signal of OR46 becomes active. That is, an interrupt signal is output from OR4B. The interrupt signal output from the OR 46 is sent via a terminal 47 onto the interrupt signal line 33 (of the serial bus 30) and is transmitted via the same signal line 33 to the support processor 27. Furthermore, when any F/F in the four interrupt F/F groups is set as described above, the decoder 42 becomes enabled, and a specific decode signal (corresponding to pit 1 in this embodiment) is sent from the decoder 42. A valid decode result is output with only the decode signal (decode signal) active. If an interrupt occurs in GA26 with GA number B (hexadecimal representation), that GA2
The decoder 42 in bit 6 outputs a decode result in which only the decode signal corresponding to bit 11 is active.

When the support processor 27 receives an interrupt signal via the interrupt signal line 33, the support processor 27 selects the interrupt source (interrupt source GA).
), the function line 35 is set to address mode, and the 4-pit address data "0000" (this is called address O) is transferred to the serial data bus 32 (by shifting the shift register 28).
output in series.

The control circuit 56 within each QA 26 is connected to the serial bus 30.
When the function line 35 is set to the address mode, the data on the serial data bus 32 is assumed to be address data (GA number), and the same data is serially input to the shift register 41. And the control circuit 56
The address data input to the shift register 41 is stored in the address register 54.

The contents stored in the address register 54 are supplied to the control circuit 56. The control circuit 56 identifies whether the contents of the address register 54 are address 0, address F (“1111”), or something else. When the contents of the address register 54 are address 0 as in this embodiment, the control circuit 56 switches the multiplexer 49 to the O side. As a result, the output data of the decoder 42 is selectively output from the multiplexer 49 to the lower 16 bit field of the shift register 41. The control circuit 56 then causes the shift register 41 to perform parallel input operation. This allows multiplexer 49
The output data of the decoder 42 selectively outputted from the decoder 42 is stored in the lower 16 bit field of the shift register 41. Therefore, the GA provided in channel 23-1
In the lower 16-bit field (bits 16 to 31) of shift register 41 in bit 26, only pit 17 is set.

The support processor 27 sets the function line 35 to the address mode as described above and sets the function line 35 to address 0.
is transferred to each GA 26, then the function line 35 is switched to the shift-out function. Each G
The control circuit 56 in A 26 is connected to the function line 3.
When the shift-out function mode is specified by 5, the shift register 41 is shifted out by 32 bits in response to the clock signal from the clock signal line 34, and the contents of the 32 bits are serially output from the serial output terminal.

The serial output data from the shift register 41 in each G A 26 is sent to the serial data bus 31 at the oven collector. Serial data on the serial data bus 31 is supplied to the support processor 27 and serially input to the shift register 28 within the support processor 27 . Therefore, if an interrupt is issued from each GA 26 with GA number 8.8 at the same time as an interrupt from GA 26 with GA number 1, the content of the data taken into the support processor 27, that is, the shift The contents of register 28 are
Bit 1 corresponding to GA number 1.8.8 as shown in the figure
7.24.27 is set. The support processor 27 operates at pits 17 and 24 of the shift register 28.
．． By setting 27, GA number 1.8
．． 8 (hexadecimal representation) recognizes that interrupts have been issued simultaneously from each G A 26. That is, in this example,
When interrupts are issued from multiple GAs at the same time, i! The source of all interrupts can also be recognized. Therefore, in this example, all G
For A, it is possible to provide interrupt processing services to Alley. That is, according to this embodiment, the degree of freedom in interrupt processing is significantly improved compared to conventional systems in which acceptance of interrupt requests is determined based on physical priority, such as systems that apply a daisy chain method.

The support processor 27 inputs the data indicating the interrupt source GA according to the above-described procedure, and when it recognizes the interrupt source GA, sets the function line 35 to the address mode again, and sets the GA indicating the recognized interrupt source GA.
number (in case of simultaneous interrupts, the GA number of one of them), e.g. GA 26 placed on channel 23-7
The GA number 1 indicating GA number 1 is serially outputted to the serial data bus 32.

The control circuit 56 within each G A 26 connects to the serial bus 30
When the function line 35 is set to the address mode, assuming that the data on the serial data bus 32 is address data (GA number) as described above, the same data is transferred from the shift register 41 to the address register 54.
be stored in The contents stored in address register 54 are supplied to control circuit 56 and comparator 55.

The GA number set by the GA number setting switch 60 is also supplied to the comparator 55 via the terminal 58 . The comparator 55 selects the GA set by the GA number setting switch 60.
The number and the contents of the address register 54 are compared to detect a match. In this embodiment, the content of address register 54 is 1, so only comparator 55 in GA 26 located in channel 23-1 detects a match.

The control circuit 56 determines that the contents of the address register 54 are 01F.
or otherwise. The control circuit 56 operates according to the comparison result of the comparator 55 when the contents of the address register 54 are other than O1F as in this embodiment. If a match is detected in the comparator 55 in the GA 26 placed in channel 23-1, that is, the GA placed in channel 23-1
26 is selected and designated by the support processor 27, only the II ta11 circuit 56 in that GA 26 performs the status transfer preparation described below. That is, the control circuit 56 in the GA 26 placed in the channel 23-1 controls the status register (not shown) of the channel 23-1.
Status information such as error information supplied from the terminal 45 is stored in the error information register 48. Further, the IIJI11 circuit 56 switches the multiplexer 49 to the 1 side. As a result, the lower 16 bits of the contents of the error information register 48 are selected from the multiplexer 49,
It is supplied to the lower 16 bit field of the shift register 41. Further, the upper 16 bits of the contents of the error information register 48 are supplied as they are to the upper 16 bit field of the shift register 41. and #J I11
The circuit 56 causes the shift register 41 to perform parallel input operation. As a result, the contents (status information) of the error information register 48 are stored in the shift register 41.

After the support processor 27 sets the function line 35 to the address mode and sends the GA number to the serial data bus 32 as described above, it then switches the function line 35 to the shift-out function.

Control circuit 56 in GA 26 where GA number matching is detected
When the shift-out function mode is designated by the function line 35, the shift register 4
1 is shifted out by 32 bits, and the contents of the 32 bits, ie, status information, are serially output from the serial output terminal. At this time, the control circuit 56 resets the interrupt F/F group 44 and turns off the interrupt signal.

Serial output data from shift register 41 in G A 26 is transferred to support processor 27 via serial data bus 31 and serially input to shift register 28 in support processor 27 . Support processor 2
Reference numeral 7 displays an error on, for example, a CRT display device (not shown) based on the status information that is the transfer data from the interrupt source GA.

Furthermore, if necessary, the support processor 27 generates data for error processing for the relevant system component (in this example, channel 23-1) based on the status information from the interrupt source GA, and uses the data. An operation is performed to transfer the data to the GA 26 in the same component (channel 23-1). In this case, the support processor 27 first sets the function line 35 to address mode and sends a GA number to the serial data bus 32, thereby selecting and specifying, for example, the GA 26 placed in the channel 23-1. Next, the support processor 27 sets the function line 35 to the shift-in function mode and sends error processing data to the serial data bus 32.

When the shift-in function is designated by the function line 35, the control circuit 56 in each GA2B
Data transferred via the serial data bus 32 is serially input to the shift register 41. And of the IvJWJ times WI56 in each G A 26, the support processor 27
The control circuit in the GA 26 selected and designated by transfers the data serially input to the shift register 41 to the data register 52, and supplies the same data (that is, error processing data) to the contents of the channel 23-1 via the terminal 53. By doing this, error processing of the same channel 23-1 (channel 23-1)
-1, the auxiliary storage device 25-1, etc.). Note that the above-described error handling procedure does not necessarily have to be performed on the interrupt source, but may be performed on any system component. Furthermore, it is also possible to perform not only error processing but also, for example, testing.

Next, channel address search by the support processor 27 will be explained. When the support processor 27 needs to search for a channel address, for example, when the system power is turned on, the support processor 27 sets the function line 35 to address mode and sends the address F to the serial data bus 3.
Serial output to 2. When the function line 35 of the serial bus 30 is set to the address mode, the control circuit 56 in each GA 26 assumes that the data on the serial data bus 32 is address data (GA number) as described above. The same data is stored in the address register 54 via the shift register 41. When the content of the address register 54 is F as in this embodiment, the control circuit 56 sets the decoder 42 to the enabled state, switches the multiplexer 49 to the O side, and then causes the shift register 41 to perform parallel input operation. As a result, the valid decoding result of the decoder 42 is stored in the lower 16 bit field of the shift register 41. therefore,
For example, in the shift register 41 of the GA 26 in channels 23-1 to 23-n, only one specific bit corresponding to the channel address is set.

The support processor 27 sets the function line 35 to the address mode as described above and reads the address F.
is sent to the serial data bus 32, then the function line 35 is switched to the shift-out function. When the shift-out function mode is specified by the function line 35, the control circuit 56 in each GA 26 shifts out the shift register 41 by 32 bits, and transfers the contents of the 32 bits from the serial output terminal to the serial data bus 31. output in series.

Serial data indicating the GA number (channel address) from each GA 26 is wired-ORed on the serial data bus 31, supplied to the support processor 27, and serially input to the shift register 28 in the support processor 27. The support processor 27 stores the data serially input to the shift register 28 in the RAM 29. The support processor 27 stores the data stored in the RAM 29 in C
In response to a request from the P U 21, the CPU 21 is notified via the system bus 24. The data stored in RAM29 is
The GA number unique to each GA 26 in the system is shown in bit correspondence, and the channels 23-1 to 23-n are
For GA 26 located in GA 26, the GA number matches the channel address. Therefore, the CPU 21 can recognize the channel addresses existing in the system based on the data notified from the support processor 27.
It is possible to check whether the channel addresses sent to the channels 23-1 to 23-n are illegal during input/output transfer between the auxiliary storage devices 25-1 to 25-n, and to prevent illegal channel addresses from being sent. It can be done. Therefore, if this check does not detect an illegal channel address and the above-mentioned timeout is detected, more specifically, if an illegal channel address exists in the error information of the channel, the CPU 21 It can be determined that an illegal channel address was generated due to a hardware defect. The same applies to channel addresses generated by the support processor 27.

In the above embodiment, the error information collection/processing circuit is
Although the explanation has been made assuming that the gate array is composed of A (gate array), the present invention is not limited to this.

[Effects of the Invention] As described in detail above, according to the present invention, the following effects can be achieved.

■ The error information collection/processing circuit installed in the system component is controlled only by the supporting processor via a serial bus independent of the system, and operates completely asynchronously and independently of the corresponding system component, so it is accurate. In addition, a wealth of error information can be collected, and MTTR (mean time to repair) can be shortened.

- Since the error information collection/processing circuit is independent, there is no risk of system timeout even if the circuit fails, and MTBF (Mean Time Between Failures) can be improved.

■ Since the error information collection/processing circuit is independent from the system, testing of corresponding system components such as channels can be performed even while online (during field operation).

- Even if an illegal channel address is transferred to a channel, it can be correctly determined whether it is caused by a programming error or a hardware defect.

[Brief explanation of drawings]

FIG. 1(a) is a block diagram of an information processing system according to an embodiment of the present invention, and FIG. 1(b) is a support processor and a GA (gate gate) as an error information collection/processing circuit applied in the above system. FIG. 1(c) is a block diagram of the GA (gate array), and FIG. 2 is an example of the input data of the support processor when an interrupt occurs. The figure shown in FIG. 3 is a diagram showing a conventional information processing system. 21・CPU, 22... Main storage device, 23-1
~23-n-...channel, 24...system bus,
26... Gate array (GA), 27... Support processor, 28.41... Shift register, 29.
...RAM, 30...Serial bus, 31, 32...
・Serial data bus, 35...function line,
42... Decoder, 44... Interrupt F/F group, 48
...Error information register, 54...Address register (1 separate number register), 55...Comparator, 56...
・Control circuit. Applicant's agent Patent attorney Takehiko Suzue Figure 1-2 Figure 3

Claims (1)

[Claims] In an information processing system in which various components such as a CPU, a main memory device, and a plurality of channels are interconnected by a system bus, a serial bus including a function line, an interrupt signal line, and a serial data bus for serial transfer is provided. an error information collection/processing circuit that is connected to the serial bus and that collects error information and processes errors for the corresponding component; an identification number setting switch that sets an identification number that matches the channel address when the corresponding component is the channel address; a support processor that controls the error information collection/processing circuit and performs serial data transfer with the circuit; the error information collection/processing circuit stores error information of the corresponding component; Serial data input/output is performed between the error information register, a flip-flop that is set in response to a request from the corresponding component and outputs an interrupt signal to the interrupt signal line, and the serial data bus of the serial bus. A shift register, a decoder that decodes the identification number set by the identification number setting switch and outputs a decoded signal specific to the identification number, and a support processor when the function line is set to address mode. , an identification number register that stores an identification number transferred via the serial data bus; and when the content of this identification number register is the first identification number, if the flip-flop is set, the decoding result of the decoder; means for setting the set in the shift register and serially transferring the set contents to the support processor via the serial data bus, and when the contents of the identification number register are a second identification number,
means for setting the decoding result of the decoder in the shift register regardless of the state of the flip-flop and serially transmitting the set contents to the support processor via the serial data bus; and the contents of the identification number register and the identification number register. A comparator that detects a match by comparing the identification number set with the number setting switch, and when a match is detected by this comparator, if the function line is set to the shift out function by the support processor. , means for setting the contents of the error information register in the shift register and serially transferring the set contents to the support processor via the serial data bus; and when a match is detected by the comparator, the support processor If the function line is set to a shift-in function, means for serially inputting data on the serial data bus transferred from the support processor to the shift register and performing error processing using the input data. In preparation, when a channel address search is necessary, the support processor sets the function line to address mode, serially outputs the second identification number to the serial data bus, and then shifts out the function line. 1. An information processing system characterized in that the information processing system is configured to input data on the serial data bus in series by setting a mode, and to notify the input content to the CPU as necessary.