JP2645021B2 - Bus abnormality inspection system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a bus abnormality inspection system that can be used for a computer system or the like.

(Prior Art) In a conventional computer system or the like, a bus abnormality is inspected by increasing the capacity of the bus so as to have redundancy, and transmitting the data as redundant data by a predetermined method on the data sending side via the bus. The data is sent and the receiving side checks the data by using a predetermined method based on the redundant data.

According to such a configuration, there is a disadvantage that the bus configuration is increased in size and complicated because the bus capacity is increased to provide redundancy. In addition, it is necessary to add a configuration relating to data redundancy to each of the data sending side and the data receiving side, and there is a disadvantage that the configuration of this portion becomes large and complicated.

(Problems to be Solved by the Invention) As described above, in the conventional bus abnormality inspection system, data is provided with redundancy, and accordingly, a bus, a data receiving side, and a data transmitting side are provided. Each of them has a drawback that the configuration becomes large and complicated.

The present invention has been made in view of the drawbacks of such a conventional bus abnormality inspection system, and has an object to eliminate the need to increase the size and complexity of the bus configuration, and to further improve the data reception side.
An object of the present invention is to provide a bus abnormality inspection system that can simplify the configuration of a data transmission side.

[Configuration of the Invention] (Means for Solving the Problems) In the present invention, a control unit for controlling a system and a plurality of I / Os
An O / I interface is connected to the I / O interface via an address bus and a data bus. In the bus error inspection system, the I / O interface corresponds to a predetermined address different for each I / O interface via the address bus. To the I / O interface, and the I / O interface responds to the data returned via the data bus with each I / O
An error check means for checking whether or not there is a match with predetermined data specific to each O interface, and in the case of a mismatch, detecting that there is an error in the address bus and the data bus, is provided. In response to a predetermined address being given from the abnormality inspection means via the address bus, another I / O interface
A bus abnormality inspection system including data transmission means for returning specific data different from the / O interface through the data bus is provided.

(Operation) According to the above configuration, when each I / O interface is accessed from the control unit via a different address bus, the check as to whether or not predetermined data is returned to the data bus is repeated. Further, it is possible to appropriately detect and detect an abnormality in the I / O interface. That is, by detecting the presence or absence of a response by sending different address data, it is possible to determine whether any of the address data has been transmitted via the address bus, and to determine whether the return result is appropriately different predetermined data. Thus, the normality of the data bus can be detected, and further, the abnormality of the I / O interface can be detected, for example, because the inspection for the other I / O interface is normal and the inspection for the predetermined I / O interface is abnormal.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a configuration diagram of one embodiment of the present invention. In the figure, 1 denotes a control unit for controlling the system, ₄₁ to ₃ shows the I / O interface is a device. The control unit 1 and the I / O interface ₄₁ to _3, and is connected via an address bus 2, the data bus 3. I / O interface 4 ₁ to 4 ₃
The data transmitting unit 40 ₁ to 40 ₃ are provided, respectively, alpha + 1 to the address bus 2, beta + 1, the gamma + 1 is given, a data input-output address alpha, beta, gamma and to the data bus 3 It is configured to send out. The control unit 1 is provided with an abnormality inspection means 10 by a program, and the abnormality inspection means 10
+1, β + 1, and γ + 1, the data bus 3
Are compared with α, β, and γ, respectively, to detect whether they match or mismatch. The result of this detection is
The display may be shown by turning on a display (not shown) or printed out (from a printer (not shown)).

Specifically, the abnormality inspection means 10 operates according to the flowchart shown in FIG.

First, a start, the check target and I / O interface 4 ₁ (101). Then, outputs alpha + 1 to the address bus 2, the data bus 3 from the data transmission means 40 ₁
Reads the data input / output address output to
2). Here, it is determined whether the read address matches α (103), and if they do not match, a bus error process (104) is performed. The bus error processing is, for example, lighting of the above-mentioned display. Here in the case of disagreement, the address bus 2 is abnormal and the address alpha I / + 1 as a data bus 3 which could not have be properly instruction alpha is abnormal data input-output address could not transfer properly O interface 4 ₁ bus It can be considered that one or more of three types of abnormalities in which the connection circuit is abnormal and correct data cannot be received have occurred.

Next, the abnormality inspection means 10 detects whether or not all the I / O interfaces have been subjected to the bus abnormality inspection (105). If all the I / O interfaces have not been inspected yet, the next I / O interface is targeted (106), Returning to step 102, the inspection is repeated.
Thus, I / O interface 4 _2, 4 ₃ are inspected.
When all the I / O interfaces are inspected, the operation is stopped. For example, as a result of the above inspection, I / O
Is abnormal when the interface 4 _1, assuming that a normal time of the I / O interface 4 _2, 4 _3, interface 4
_It can be seen that there is a high possibility that the bus connection circuit ₁ is abnormal.

As described above, in this embodiment, different addresses α + 1, β + 1, and γ + 1 are transmitted for each I / O interface, so that it is possible to detect which address is difficult to pass through the address bus 2. That is, if α + 1, β + 1, and γ + 1 are addresses (predetermined address data including all 0 to all 1) that can distinguish whether “1” or “0” passes through each bit of the address bus, I / O If there is no return from the interface, it can be detected that this address data does not pass (that is, the address data with a certain bit set to “1” or “0”) does not pass. Similarly, since different data α, β, and γ are returned for each I / O interface, it is possible to detect which data is difficult to pass through the data bus 3. Further, since data is returned by subtracting 1 from the address (α + 1, β + 1, γ + 1), it can be very easily inspected that the I / O interface is responding appropriately and sending back data. Above, by sending data one bit different from the address data sent to the address bus 2, it is possible to distinguish whether "1" or "0" passes through each bit of the data bus.

In this embodiment, the data input / output address is read, but this is not always necessary.
Instead of giving a certain address to take out predetermined data, a device may be designated by a certain address and a command may be given via a data bus to take out specific data.

[Effects of the Invention] As described above, according to the present invention, by sending different addresses, it is possible to detect whether any of the addresses can be transmitted via the address bus based on the presence or absence of a response from the I / O interface. Also, a normal or abnormal data bus can be detected based on whether or not the return result is appropriately different predetermined data. Further, when a test on a predetermined I / O interface is abnormal, a test on another I / O interface is performed. It is possible to detect an abnormality in the I / O interface depending on the situation such as normal operation.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG.
It is a flowchart for demonstrating operation | movement of the system of the figure. DESCRIPTION OF SYMBOLS 1 ... Control part, 2 ... Address bus 3 ... Data bus 4 ₁ to 4 ₃ ... I / O interface 10 ... Abnormality inspection means 40 ₁ to 40 ₃ ... Data transmission means

Claims (2)

(57) [Claims] A control unit for controlling a system and a plurality of I / Os
In a bus abnormality inspection system of a system in which an interface is connected via an address bus and a data bus, the control unit includes an I / O corresponding to a predetermined address different for each I / O interface via the address bus. To the I / O interface, and the I / O interface responds to the data returned via the data bus with each I / O
The O / I interface is provided with abnormality inspection means for inspecting the coincidence / mismatch with predetermined data specific to the O interface, and in the case of inconsistency, detecting that the address bus and the data bus are abnormal. In response to the predetermined address being provided from the abnormality inspection means via the address bus, specific specific data different from other I / O interfaces is returned to the I / O interface via the data bus. A bus abnormality inspection system, comprising: 2. The bus abnormality inspection system according to claim 1, wherein said data transmission means transmits data obtained by subtracting 1 from an address transmitted from the address bus to the data bus.