JPH02146643A - Memory device - Google Patents

Abstract

PURPOSE:To prevent the transfer of wrong data by monitoring the delay timing signal from the 1st and 2nd bank control parts and outputting an error signal caused by the bank conflict to an external device when both delay timing signals are received in the same timing. CONSTITUTION:The 1st and 2nd delay timing signals of the 1st and 2nd bank control parts 16 and 17 are monitored by a monitor part 18. Then the part 18 outputs a signal to an external device 14 via a common control part 15 to show an error due to the conflict caused between the 1st and 2nd banks 11 and 12 when both delay timing signals are received in the same timing. Thus it is possible to detect an error due to the conflict to the action of one of both banks 11 and 12 that is caused by the malfunction of the other bank. Furthermore the error due to such conflict can be reported to the device 14.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a storage device having a storage section including a plurality of banks and a control section that controls the storage section.

[Background Art] With the recent increase in speed of processors, the demand for faster storage devices has also increased. However, progress in increasing the speed of storage elements in storage devices is slower than that of processors, and high-speed storage devices that match the high speed of processors have not been obtained.

Therefore, a storage device having a storage section including a plurality of banks and a control section that controls the storage section is used as one storage device, and high-speed data transfer is achieved by interleaving operation or the like.

In such a storage device having a storage section including a plurality of banks, a means for detecting a failure is required. Conventionally, as a failure detection means for such a storage device, a check means is provided by checking the data and address (No. 5) manually entered into each bank, and by checking the parity of data output from each bank.

[Problems to be Solved by the Invention] However, with such a check means, even if one bank malfunctions and an operation conflict with another bank occurs, if there is no error in the data, etc., such conflict will be resolved. occurrence cannot be detected. Therefore, the storage device is unable to report the occurrence of a conflict to an external device such as a processor, and ends up transferring erroneous data to the external device.

An object of the present invention is to provide a storage device that has a storage section including a plurality of banks and is capable of detecting the occurrence of conflict in bank operations.

[Means for Solving the Problems] According to the present invention, a storage unit including first and second banks is connected to an external device, and in response to a predetermined signal from the external device, the timings of the storage unit and the second bank are mutually controlled. a common control section that outputs shifted first and second basic timing signals; the common control section and the first basic timing signal;
and first and second bank control units connected between the first and second banks, respectively, and the first and second bank control units are connected to the first and second basic banks. processing the first and second basic timing signals into first and second delayed timing signals, respectively, by giving the same delay time to the timing signals; and The signal is processed into first and second bank control signals, respectively, and the first and second bank control signals are provided to the first and second banks, respectively; In the storage device, the second bank control signal is for controlling the first and second banks, and the second bank control signal is connected to the first and second bank control units, and is connected to the first and second bank control units. monitor the delay timing signal of
a monitor that outputs a signal representing an error due to conflict between the first and second banks to the external device via the common control unit when the delayed timing signals are received at the same timing; A storage device characterized in that it has a section is obtained.

[Example] Next, an example of the present invention will be described with reference to the drawings.

Referring to FIG. 1, a storage device 10 according to an embodiment of the present invention is connected to a storage unit 13 including first and second banks 11 and 12 and a processor 14 as an external device, and is connected to a processor 14 as an external device. A common control section 15 that outputs first and second basic timing signals whose timings are shifted from each other in response to a predetermined signal, and between the common control section 15 and the first and second banks 11 and 12, respectively. Connected first and second bank control units 16 and 1
7.

The first and second bank control units 16 and 17 provide the first and second basic timing signals with the same delay time, thereby converting the first and second basic timing signals into the first and second basic timing signals. and processing the first and second delayed timing signals into first and second bank control signals, respectively, to control the first and second bank control signals. signals to the first and second banks 11 and 1
Give each to 2. For example, a shift register is used to process each of said first and said second basic timing signals into said first and said second delayed timing signals, wherein said first and said second delayed timing signals are The signal is transmitted to the first and second bank control sections 16 and 1.
These signals are used as X-Juku timing signals for the operations of No. 7. The first and second bank control signals are for controlling the first and second banks [1 and 12].

The common control unit 15 and the first and second bank control units 16 and ]7 will be described in detail below.

The common control unit 15 receives request signals, commands, etc. from the processor 4 as the predetermined signals, and outputs the first and second basic timing signals. Further, the common control unit 15 controls the transfer of data and address signals from the processor] 4 to the first and second bank control units 16 and 17, and controls the transfer of data and address signals from the first and second bank control units 16 and 17. Controls the transfer of data to the processor 14.

The first bank control unit] 6 processes the first basic timing signal into the first delayed timing signal, and based on this first delayed timing signal, sends it to the first bank] 1. Timing signals such as a write enable signal and various control signals necessary for the first bank 11 are transferred to the first bank 1 as a link control signal, and data received from the common control unit 15 is transmitted. An operation of writing data to the address of the first bank 11 indicated by the address signal received from the common control unit 15, and an operation of reading data received from the common control unit 15 from the address of the first bank 11 indicated by the address signal. I do.

Similarly, the second bank control unit] 7 processes the second basic timing signal into the second delayed timing signal, and sends the second delayed timing signal to the second bank 12 based on the second delayed timing signal. Timing signals such as a write enable signal to be output and various control signals necessary for the second bank 12 are given to the second bank 12 as the second bank control signal, and data is written to the second bank 12. Also, data is read from the second link 12.

A monitoring unit 18 is connected to the first and second bank control units] 6 and 17. [Monitor] 8 monitors the first and second delayed timing signals, and when the first and second delayed timing signals are received at the same timing, the first and second banks 11 and 12 A signal representing an error due to the conflict is generated, and this signal is output to the processor 14 via the common control unit 15.

Here, the storage section includes not only the first and second banks, but also
A case where a third bank is further included will be described. In this case, the common control section outputs first, second, and third basic timing signals whose timings are shifted from each other in response to a predetermined signal from the processor. This third basic timing signal is processed into a third delayed timing signal in a third bank control section provided corresponding to the third bank. Therefore, the monitoring unit overlooks the third delayed timing signal in addition to the first and second delayed timing signals, and monitors the first, second, and third delayed timing signals. When at least two of them are received at the same timing, a signal indicating an error due to bank conflict is output.

[Effects of the Invention] As described above, in the present invention, the first and second delay timing signals in the first and second bank control sections are monitored, and the first and second delay timing signals are controlled. We installed a monitoring unit that outputs No. 1g, which indicates an error due to conflict between the first and second banks, to an external device via the common control unit when received at the same timing.
It is possible to detect an error caused by an operation conflict with the other bank of the first and second banks due to a malfunction of one of the banks, and to report an error caused by the occurrence of such conflict to the external device. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a storage device according to an embodiment of the present invention.

Claims (1)

[Scope of Claims] 1. A storage unit including first and second banks, and first and second banks connected to an external device and whose timings are shifted from each other in response to a predetermined signal from the external device. a common control section that outputs a basic timing signal, and first and second bank control sections connected between the common control section and the first and second banks, respectively; and the second bank control unit is configured to control the first and second bank control units.
the first and second basic timing signals are processed into first and second delayed timing signals by giving the same delay time to the basic timing signals of the first and second delayed timing signals, respectively; The delayed timing signal is processed into first and second bank control signals, respectively, and the first and second bank control signals are provided to the first and second banks, respectively; and a storage device in which the second bank control signal is for controlling the first and second banks, wherein the second bank control signal is connected to the first and second bank control units, and is connected to the first and second bank control units. monitoring a second delayed timing signal;
monitoring that outputs a signal representing an error due to conflict between the first and second banks to the external device via the common control unit when the first and second delayed timing signals are received at the same timing; A storage device characterized by having a section.