JPS5917465B2 - Check device - Google Patents

Description

Detailed Description of the Invention The present invention provides an input/output device that connects the CPU, memory device, and input/output device in a control device that includes a central processing unit (hereinafter abbreviated as CPU), a memory device, and an input/output device. The purpose of this is to detect a failure in the output data bus (common connection line) and prevent the control device from malfunctioning due to a failure in the input/output data bus.

In addition, when the control device malfunctions, it is possible to clarify whether or not it is related to the input/output data bus of the CPU, thereby reducing the time required to analyze the cause of the control device malfunction. It is something that you have. Conventionally, in a so-called stored program type control device, the CP
In addition to the memory device, many input/output devices are connected to U via an input/output data bus. In this case, a software-based processing method is often used as a fault diagnosis method for the above-mentioned control device, but this method requires a large amount of memory and control time to completely detect the fault, and it cannot be done in real time. When attempting to process this, there was a drawback that the control ability of the control device was reduced. In addition, with the above method, even if it is determined that there is a failure somewhere in the control device as a whole, it is not possible to determine whether it is specifically a memory device, an input/output device, or an input/output bus. There are many. FIG. 1 shows a basic block diagram of a stored program type control device.

To explain FIG. 1, 1 is a CPU, 2 is a memory device, 31, 32-3n are input devices, 41, 42-4n are output devices, 5 is a CPU input data bus, 6 is a CPU output data bus, T is a bidirectional bus of the CPU, 8 is a memory address line, 91 is an output data line of the memory device 2, 92
~9n are input data lines from external devices, 101, 102
~10n is the selection signal line of the input devices 31, 32~3n, 1
11 is an input data line of the memory device 2; 112 to 11n are output data lines from the output devices 42 to 4n to external equipment;
21, 122-12n are selection signal lines of the output devices 41, 42-4n. Conventionally, errors in the memory device 2 have been detected using a detection method such as a parity check by adding 1 or 2 check bits to the data signal. There is no suitable detection method for the output data bus 6 and the output data bus 6, and the software method described above has been relied upon.

In this case, there were problems such as an increase in memory devices, a decrease in control ability, and a large amount of time required to analyze defective parts.

The present invention solves these conventional problems, and uses an input/output buffer and a comparator to detect defects in the input/output data bus reliably with a relatively simple configuration and with a fast response. The present invention provides a check device.

The check device of the present invention will be explained in detail below with reference to FIG.

FIG. 2 shows an embodiment of this invention. In Figure 2,
1, 2, 31-3n, 41-4n, 5-8, 91-9n
, 101-10n, 111-11n, 121-12n,
is the same as that explained in FIG. 13 is a buffer device for the input data bus 5 and the CPU1.

Since a large number of input devices are generally connected to the input data bus 5, this is provided for signal amplification and shaping, and is not necessarily necessary. Reference numeral 14 is a buffer device for the CPU 1 and the output data bus 6, which is necessary for signal amplification and shaping.

15 is a comparator, which connects input data bus 5 and output data bus 6.
It is connected to the circuit and detects a match between the two, and is composed of, for example, an exclusive OR circuit.

Next, the operation of this invention will be explained.

In FIG. 2, data from memory device 2 and external equipment is transmitted to input data bus 5 via input devices 31 to 3n.

At this time, the input device selection signal (CP
Departs from U. The data of only one input device selected by 101 to 10n (generated) is transmitted. This data signal is transmitted to the CPU1 via the input data buffer 13, and is also transmitted to the output data bus 6 via the output data buffer 14. ．． However, since the output device selection signal is not generated at this time, it is not transmitted to the external output device and the memory device 2. The signals on the input data bus 5 are simultaneously input to the comparator 15. On the other hand, input data is input to the comparator 15 via the output data bus 6, and the input data signal from the input data bus 5 and the output data bus 6 In this method, both input data signals from the 1st and 10th generation are compared to detect a match between the two. If either the input data bus or the output data bus is faulty, comparator 15 generates an input/output bus fault alarm signal. This check is performed each time the input device inputs data, and can be performed in real time without affecting the control time of the CPU. As is clear from the above description, by providing the check device of the present invention, in a so-called stored program type control device, by detecting a malfunction of the input/output data bus, the control device It is possible to prevent erroneous control.

In addition, the components can be relatively easily constructed using integrated circuits (ICs), the overall construction is simple, the detection operation is fast, the detection can be performed reliably in real time, and there are many practical advantages.

[Brief explanation of drawings]

Fig. 1 is a basic block diagram of a conventional stored program type control device, and Fig. 2 is a block diagram showing an embodiment of the present invention. 41, 42 to 4n are output devices, 5 is an input data bus of the CPU, 6 is an output data bus of the CPU, 7 is a bidirectional bus, 8 is a memory address line, 91 is an output data line of the memory device 2, 92~9n are input data lines from external equipment, 101, 102~10n
is the selection signal line of the input device, 111 is the input data line of the memory device 2, 112 to 11n is the output data line from the output device to the external device, 121, 122 to 12n is the selection signal line of the output device, and 13 is the input data line. Data bus buffer 14 is an output data bus buffer, 15 is a comparator, and 16 is a timing signal line from CPU1.

Claims (1)

[Claims] 1. In a check device for a control device in which a plurality of input devices are connected to a central processing unit via an input spring and a plurality of output devices are connected to a central processing unit via an output bus, data on the input bus and data on the output bus are compared. a comparator that transfers data on the input bus to the output bus; the central processing unit selects a specific input device to access data; A checking device characterized in that it determines whether the input bus and the output bus are out of order.