JPH08305637A - Storage - Google Patents

Abstract

PURPOSE: To detect and correct the errors of instructions and data which are stored in a main storage by providing a circuit and a signal line to make every storage recognize whether it is equal to an exclusive storage or an auxiliary storage to an MPU and also to make the storage notify other storages or a tact that it is equal to an MPU exclusive storage and then by deciding the priority of every storage. CONSTITUTION: When a main storage 8 is read at the side of an MPU bus, a read/write signal 19 is inputted together with a strobe signal 20 and an address. At the same time, the data equivalent to the address are outputted from a storage part 1 and an ECC(error correction circuit) circuit 4 performs the detection of errors of data. If no error is detected, the data valid signal 21 that is outputted to the MPU bus via a data buffer 9 is asserted. If a bit error is detected, the corrected data are outputted to the MPU bus. The circuit 4 performs only the detection of an error if this error contains two bits or more, and the priority is transferred to another storage of a lower order in a cycle mode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device having a function of detecting and correcting an error in an instruction or data stored in a main memory.

[0002]

2. Description of the Related Art In a main memory of a data processor, a command or data at the time of writing and a command or data at the time of reading are included in the command or data in the main memory due to the influence of external noise such as radiation. , Different errors or errors caused by the physical destruction of the storage element itself may occur. The former is called a soft error and the latter is called a hard error. In addition, a memory error includes a soft error and a hard error.

Generally, as a method of preventing a malfunction of a data processing device due to this memory error, when a redundant bit is provided in the main memory and data is written in the main memory,
A parity method that stores a parity bit in this redundant bit, detects the error by using the parity bit when reading an instruction or data, and reports the occurrence of a 1-bit error in the main memory to the MPU. An ECC method that detects an error when reading a 1-bit memory error, automatically corrects the corresponding bit and reads it, and only detects an error when 2 bits occur simultaneously, and reports the error occurrence to the MPU.
The storage devices are arranged in parallel, and the same instructions or data are stored in advance in the main memories arranged in parallel.
There is a method of switching to another storage device when an error occurs in one storage device.

[0004]

However, in the above method, the parity method generates the parity bit in accordance with the write operation to the main memory of the MPU and stores it in the redundant bit, and at the time of the read operation, the instruction is executed. Or, it reads the parity bit at the same time as the data, judges the occurrence of a memory error, has a simple circuit configuration, and has the advantage that it does not regulate the operating speed of the processor, but it has a 1-bit (abnormal inversion of odd number of bits) error Occurrence can be detected and runaway of MPU can be avoided by software configuration, but in order to continue normal operation as a data processing device after an error occurs, the current instruction is interrupted and F / D or H / D etc. Reload the instruction or data from the boot device of
The device needs to be restarted. Further, if even bits of two or more bits are inverted at the same time, detection itself is impossible, and an instruction or data containing an error may enter the MPU as it is, and as a result, MPU runaway may occur. Therefore, it is difficult to secure high reliability in a storage device using only the parity method. ECC
According to the method, even if a 1-bit memory error occurs when an instruction or data is read from the main memory by the MPU, the error bit is specified at the time of reading and the error-corrected data is read and stored. Since it is possible to modify the corresponding bit of the device, it is possible to ensure high reliability as compared with the parity method. However, even in the ECC method, when an inversion of an even number of bits occurs at 2 bits or more at the same time, a memory error occurrence can be detected, but this cannot be corrected. In addition, simultaneous error of 2 bits or more is detected and reported to MPU.
There is also a method to make the MPU execute the exception handling program, but if the exception handling program itself has a simultaneous error of 2 bits or more, or if quantitatively meaningful data has a simultaneous error of 2 bits or more, the data The normal operation of the processor cannot be guaranteed.

In a system in which storage devices are arranged in parallel and an error occurs in one of the storage devices, switching is made to the other storage device, even if a simultaneous error of 2 bits or more occurs,
The data sent to the MPU is normal, but the storage device that once generated the error still contains the error,
Even if this error can be corrected by software, the original processing of the MPU had to be interrupted in order to correct it. An object of the present invention is to prevent a malfunction of a data processing device even when a memory error of 2 bits or more simultaneously occurs in a main memory of the data processing device, and
It is to realize correction of an error in a storage device without interrupting the processing of the data processing device and the MPU.

[0006]

In order to solve the above object, the present invention is configured as follows.

A plurality of storage devices are used to store instructions and data required for the operation of the device.

A circuit for recognizing whether each of the plurality of storage devices is an exclusive storage device or an auxiliary storage device of the MPU and notifying other storage devices that they are the exclusive storage device of the MPU. It has a signal line and determines the priority of each storage device. The MPU normally uses the above-mentioned exclusive storage to perform data processing. Further, the storage device monitors the conversion of the read instruction or data into a state different from the write instruction or data in synchronization with the read and write cycles of the MPU bus in the storage device, and performs conversion. ECC for correcting 1-bit error of instruction and data in main memory
And a circuit for delegating the right of the exclusive storage device to another storage device when an instruction and data conversion of 2 bits or more that cannot be self-corrected by the ECC circuit occur. Even in the case of the auxiliary storage device, when an error occurs in another high-priority private storage device during the read cycle of the MPU and the right of the private storage device is transferred, it corresponds to the address of the MPU bus. , And has a circuit for outputting instructions and data during a read cycle of the MPU bus.

When the auxiliary storage device is not accessed by the MPU or the like, an internal counter artificially generates an address only inside the storage device, monitors data conversion at any time, and increments the counter. It has a circuit that operates an ECC circuit that corrects a 1-bit error by repeating the monitoring operation. Further, in this case, if a conversion of instructions and data of 2 bits or more, which cannot be corrected by the ECC circuit, occurs. , The circuit has a circuit to determine whether the conversion is caused by the physical destruction of the memory element itself or the conversion of the electric transient memory content due to external noise, etc. In the case of conversion, the auxiliary storage device acquires the right to use the MPU bus, directly reads out the instructions and data from the storage device in another parallel relationship, and Storage device, two or more bits of instruction and data conversion has a circuit for correcting replaced with instructions and data locations that occurred.

[0010]

The plurality of storage devices individually recognize whether they are the exclusive storage device or the auxiliary storage device of the MPU, and the storage device itself recognizes the MPU.
It has a circuit and a signal line for notifying the other storage device that it is the exclusive storage device, and determines the priority order as an individual storage device. This signal line informs other main memory that it is a dedicated storage device in the active state, and while it is a dedicated storage device, an instruction of 2 bits or more which cannot be repaired by the ECC circuit in the storage device and When data conversion occurs, this signal is made negative to transfer the right of the exclusive storage device to the storage device having a lower priority. As a result, during the read cycle of the MPU, if an abnormality occurs in the storage device at the higher priority position, the other storage device to which the priority has been transferred becomes M
The instruction and data corresponding to the address output by the PU are output. When the instruction or data read in synchronization with the read and write cycles of the MPU is converted into 1 bit, the error is repaired by the internal ECC circuit, so the priority does not move.

Further, even when each storage device is an auxiliary storage device which is not a read access target by the MPU, it is possible to generate a pseudo address only inside the storage device by an internal counter inside the storage device. By reading the data inside and operating the ECC circuit, the conversion of the instruction and the data is monitored, and if there is a 1-bit error, the ECC circuit corrects it. Further, at this time, when the conversion of the instruction and the data of 2 bits or more, which cannot be corrected by the ECC circuit, occurs, the conversion is caused by the physical destruction of the memory element itself, or by the external noise. If the temporary storage contents are converted, the auxiliary storage device acquires the right to use the MPU bus, and an instruction is issued from another storage device in parallel relation. And read the data directly, and replace and correct it with the instruction and data at the location of the conversion of the instruction and data of 2 bits or more in the own storage device.

[0012]

EXAMPLES The present invention will be described in detail below with reference to examples.

1 and 2 are block diagrams of a storage device according to an embodiment of the present invention. In this embodiment, as shown in FIG.
A plurality of storage devices 8 shown in FIG. 1 are arranged in parallel on the MPU bus. The signals of the data bus 9 and the address bus 12 and 17 to 24 of each storage device 8 are connected to the MPU bus or directly between the storage devices 8. In Figure 1,
When the main memory device 8 is read from the MPU bus side, the read / write signal 19, the strobe signal 20, and the address are input, the data corresponding to the address is output from the memory unit 1, and the ECC circuit 4 detects a data error. And then
If no error is detected, it is output to the MPU bus via the data buffer 9 and the data valid signal 21 is asserted. When an error is detected and the error is a 1-bit error that can be corrected by the ECC circuit 4, corrected data is output to the MPU bus. When the error is an error of 2 bits or more that cannot be corrected by the ECC circuit 4. Is E
Only the detection is performed by the CC circuit 4, and the data valid signal 2
1 is not asserted and the priority transfer signal output 18 is activated to transfer the priority right to the lower storage device during the cycle.

If the priority delegation signal input 17 is in a negative state (when there is a storage device having a higher priority), the address is latched in the address buffer 3 and is not transmitted to the storage unit 1, but as described above. When the priority delegation signal input 17 becomes active, the latched address is transmitted to the storage unit 1, data is output from the storage unit 1, the data valid signal 21 is asserted, and the read cycle is ended. As a result, even if an error of 2 bits or more occurs in the storage device having the priority, the data viewed from the MPU is normal. Further, the address counter 5 is mounted inside the memory device 8, and when the priority delegation signal input 17 is in the negative state, the increment address is input from the address counter 5 to the memory unit 1 and the data is output to the ECC circuit 4. By doing so, the error in the data in the storage device 1 is monitored. If an error occurs during this monitoring operation and the error is a 1-bit error that can be corrected by the ECC circuit 4, the corrected data is rewritten to the read address. If the generated error is an error of 2 bits or more that cannot be corrected by the ECC circuit 4, the comparator 7 having the test data generation function writes the test data at the address where the error occurred and the comparator 7 reads it again. It is compared with the test data, and if it matches the test data, it is separated as a soft error, and if it does not match, it is separated as a hard error, and it is notified to the controller 6 by the comparator control signal 14. As a result, the cause of the error of 2 bits or more is the soft error. In this case, the controller 6 sends the bus right request signal 13 to MP.
When the bus is output to the U bus and the use of the bus is permitted by the bus permission signal 15, the address in which the error has occurred is output from the address buffer 3 to the MPU bus and has another priority right now. The error is repaired by reading the data corresponding to the address where the error has occurred from the storage device and rewriting to the address where the error occurred.

Further, if the storage device having the priority right is E
Immediately after the CC circuit 4 generates an uncorrectable error of 2 bits or more and transfers the priority to another main memory, the error isolation and correction are similarly performed.

When the generated error of 2 bits or more is judged to be a hard error, the controller 6 uses the hard error signal 25 to warn the MPU.

Further, the main memory 8 suspends the internal monitoring operation and is latched by the address latch 3 when there is a write access from the MPU or the master on the MPU bus regardless of the presence or absence of the priority. Data stored in the data latch 3 using the address
The suspended monitoring operation, which is written to, is reunited as soon as the write access from the master on the MPU bus is completed. By the operation, the contents of all the storage devices arranged in parallel on the MPU bus can be kept the same.

[0018]

According to the present invention, in a data processing device having an MPU and a storage device, even if a memory error of 2 bits or more occurs in the storage device at the same time, the generated 2 bits are generated without stopping the operation of the MPU. The above memory error can be corrected.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a connection diagram of the storage device of FIG.

3 is a flowchart of the storage device of FIG. 1 when the storage device is a dedicated storage device.

FIG. 4 is a flowchart of the storage device of FIG. 1 in the auxiliary storage device.

[Explanation of symbols]

1 ... storage unit, 2 ... data latch, 3 ... address latch,
4 ... ECC circuit, 5 ... Address counter, 6 ... Controller, 7 ... Comparator, 8 ... Main memory device, 9 ... Data bus, 10, 11 ... Internal data bus, 12 ... Address bus, 13 ... Internal address bus, 14 ... Comparator control signal, 15 ... ECC control signal, 16 ... Storage unit control signal,
17 ... Priority delegation signal input, 18 ... Priority delegation signal output, 1
9 ... Read / write signal, 20 ... Strobe signal, 21
... data confirmation signal, 22 ... bus right request signal, 23 ... bus right permission signal input, 24 ... bus right permission signal output.

Claims (1)

[Claims] 1. A plurality of storage devices are arranged in parallel in the same address space of an MPU, one of the storage devices is used as a dedicated storage device normally used exclusively by the MPU, and the other is used as the dedicated storage device. In a data processing device used as an auxiliary storage device when an abnormality occurs, each storage device itself recognizes whether it is the dedicated storage device or the auxiliary storage device of the MPU, and also the MPU itself. Circuit for notifying other storage devices that it is the above-mentioned exclusive storage device, and a circuit for detecting and correcting an error in an instruction or data during a read cycle on the MPU bus side, and for the MPU bus side. Regardless of the read cycle, the contents of each memory device have a circuit for constantly monitoring the conversion to a state different from the instruction and data at the time of writing, and when the conversion is detected, the In the case of conversion that cannot be corrected by the circuit itself, the conversion is caused by the physical destruction of the memory element itself, or by an electrical noise caused by external noise or the like. It has a circuit that distinguishes whether it is due to the temporary conversion of memory contents, and if it is due to the temporary conversion of memory contents,
The MPU has a circuit for correcting an error by reading an error-free instruction or data from another storage device arranged in parallel at the same address and writing the read instruction or data in the storage device in which the conversion has occurred. When the bus side writes to the storage device, it has a circuit for writing instructions and data regardless of whether it is the dedicated storage device or the auxiliary storage device, and the contents of other storage devices and their own storage device. A storage device characterized in that