JPS6136641B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a process control system equipped with a backup controller, and particularly to a process control system that can guarantee the validity of a backup database no matter how abnormal the main digital controller becomes. It is.

The main digital controller stores the database in a backup database at regular intervals to prepare for failure of the main digital controller.

Conventionally, the main digital controller directly stores the database in a backup database storage location.

However, a controller with a large database requires a large storage space for the backup database, which increases the possibility that the backup database will be destroyed due to runaway of the central processing unit of the main digital controller. In other words, since the memory is large, there is a possibility that the backup database will be corrupted.

In view of the above points, the present invention has been made to solve such problems and eliminate such drawbacks.The purpose of the present invention is to guarantee the validity of the backup database no matter how abnormal the main digital controller becomes. An object of the present invention is to provide a process control system equipped with a backup controller that obtains the desired results.

In order to achieve such an object, the present invention provides a buffer memory on the main digital controller side, and also includes a control means on the input side of the buffer memory for inhibiting data writing by a keyword signal indicating that the diagnosis result is normal. The random access memory in the switching device copies the contents of the buffer memory based on the keyword signal indicating that the diagnosis result is normal, and if an abnormal diagnosis result is found, writing from the buffer memory to the random access memory is prohibited. With,
The database in the random access memory is transferred and stored in the memory of the backup controller in response to a switching request signal from the main digital controller.Embodiments of the present invention will be described in detail below with reference to the drawings. .

FIG. 1 is a block diagram showing an embodiment of a process control system equipped with a backup controller according to the present invention, and only the parts necessary for explanation are shown. Here, MDC is the main digital controller, and one backup digital controller BUDC is generally prepared for each of the main digital controllers MDC # ₁ to _#o , and in that case, the switching device SW is also # ₁ ~# _o and n
Each will be prepared. For convenience of explanation, the embodiment shown in FIG. 1 is based on the main digital controller MDC1.
This assumes that there is one backup digital controller per unit. Therefore, the switching device
There is also one SW. In this case, the configuration is completely symmetrical, making it unnecessary to distinguish between main and backup.

In this figure 1, CPU _M is a central processing unit that collects various information from bus BH _M , and MEM _M is a bus
A memory that inputs information from _BHM and outputs information to bus _BHM , I/O _M is an input/output circuit connected to bus _BHM , _BMM is a buffer memory, RG _M is a register, and OR _M is based on diagnostics. The switching request signal DS is generated by inputting the switching request signal COS and the output signal WDO-OUT from a watchdog timer (not shown).
These constitute the main digital controller MDC connected to the data highway.

I/Fa and I/Fb are interfaces for transmitting information between the main digital controller MDC and backup digital controller BUDC, respectively, RAM is random access memory, and CPUs
is a central control unit that is connected to the main digital controller MDC and the backup digital controller BUDC, and responds to a failure of the main digital controller MDC by switching the main digital controller MDC's memory MEM _M
Digital controller for backup
It constitutes a switching device SW for transferring the database to memory MEM _B of BUDC.

CPU _B is a central processing unit that collects various information from bus BH _B , memory that inputs information from MEM _B and outputs information to bus BH _B , and I/O _B is a bus
The input/output circuit connected to BH _B , BM _B is a buffer memory, RG _B is a register, and OR _B is a switching request signal that receives a diagnostic switching request signal COS and an output signal WDT-OUT from a watchdog timer (not shown). The OR gate outputs the signal DS to the switching device SW, and these constitute a backup digital controller BUDC connected to the data highway.

FIG. 2 is a block diagram showing the main parts of the embodiment shown in FIG. 1. In Fig. 2, the same reference numerals as in Fig. 1 indicate corresponding parts, CONT is a control circuit, a signal (keyword signal) indicating that the diagnosis result is normal is inputted to the set terminal S, and Q output is an operation request signal. Output as OMS, and also
It is constituted by a flip-flop to which the operation end signal OES is input to the reset terminal R. G
inputs the data from the bus _BHM shown in Figure 1, and the signal from the control circuit CONT is the enable terminal.
A gate circuit that is controlled by applying voltage to ENL, and this gate circuit G is controlled by the above control circuit.
Together with CONT, it constitutes a control means for prohibiting data writing to the input side of the buffer memory _BMM by a keyword signal KWS indicating that the diagnosis result is normal.

A buffer memory whose input is the output of the B _M circuit G. This buffer memory B _M and the gate circuit G
and control circuit CONT are provided within the main digital controller MDC.

The RAM is a random access memory that inputs the output from the buffer memory BM _M , and this random access memory RAM is a switching device.
It is in SW. In addition, in Figure 2,
, corresponds to , in FIG.

Next, the operation of the embodiment shown in FIGS. 1 and 2 will be explained with reference to FIG. 3.

First, during normal operation, the main digital controller MDC repeats the operations a, b, c, d, a, . . . shown in FIG. That is, a is the control operation period including some self-diagnosis operations, and b is the memory
It is the transfer period of the database of MEM _M to the buffer memory BM _M , c is the self-diagnosis period, and d
is a transfer permission signal, and upon receiving this signal, the central processing unit CPU _S of the switching device SW transfers the buffer memory BM _M
Copy the contents of to random access memory RAM. In addition, in this Figure 3, T
indicates the period of one cycle.

This operation allows the program and data database in the random access memory RAM of the switching device SW to be transferred to the main digital controller.
MDC memory MEM _M database is always the same. That is, a complete copy is provided.
At this time, the input gate (gate circuit) G of the buffer memory B _M shown in FIG. 2 is closed due to the generation of the keyword signal KWS, which is a signal indicating that the diagnosis result is normal, and the input gate (gate circuit) _{G of the buffer memory B M shown} in FIG. Since the transfer is interrupted, a failure occurs in the main digital controller MDC during transfer from the buffer memory B _M to the random access memory RAM of the switching device SW, and the base
Even if the data transferred from _BHM to buffer memory BM _M becomes abnormal, the buffer memory
The data stored in _BMM does not become abnormal data.

Now, if an abnormality is detected during the period a shown in Fig. 3, the keyword signal KWS indicating normality is not output, so the input gate (gate circuit) G of the buffer memory B _M shown in Fig. 2 is opened, and the buffer memory BM _M will be abnormal data, but buffer memory
Since no operation request signal is issued from _BMM to the random access memory RAM of the switching device SW, the data in the random access memory RAM remains as normal data, and under this condition,
A switching request signal DS is given to the switching device SW via the OR gate OR _M , and during normal operation, a random signal of the switching device SW, which is a complete copy of the database in the memory _MEMM of the main digital controller MDC, is sent to the switching device SW.
The access memory RAM database is the memory of the backup digital controller BUDC.
Stored in MEM _B , the backup digital controller BUDC takes over the work in place of the failed main digital controller MDC.

Next, periods a and b shown in FIG. 3 proceed normally, and when an abnormality is detected in the self-diagnosis period shown in c, the above-mentioned operations are performed in the same way.

Note that when the main digital controller MDC has a failure that prevents the self-diagnosis function from being executed, the watchdog timer outputs the watchdog timer output signal WDT-OUT, and the output is sent to the switching device via the OR gate _ORM . The contents of the random access memory RAM of the switching device SW are transferred to the memory MEM _B of the backup digital controller BUDC.
BUDC inherits control.

A conceptual timing diagram of these operations is shown in FIG. 4. In FIG. 4, a indicates the control operation period, A in the dashed line indicates the normal state, and B indicates the time point at which an abnormality is detected. b indicates a switching request, and the backup digital controller
The input/output connection to the RAM→MEM _B transfer controller is switched to BUDC, that is, the connection between the detection end and the operation end is switched. e indicates a self-diagnosis period, and d indicates a switching request, that is, switching of the self-diagnosis period. Further, C indicates the time point at which an abnormality is detected. e is watch dog timer output signal WDT-
OUT and f indicate switching requests, and these indicate switching of the self-diagnosis period. And, D indicates the timeout point of the timer.

As is clear from the foregoing, the present invention provides a buffer memory B _M on the side of the main digital controller MDC, and uses a keyword signal KWS indicating normality of the diagnosis result to cause random access control of the switching device SW from the buffer memory B _M.
transfer to memory RAM (the central processing unit CPU of the switching device SW performs its random access
This allows data to be written to the memory RAM) and prohibits data from being written to the buffer memory _BMM . In addition, when an abnormality is detected, the keyword signal KWS is not output, writing from the buffer memory _BMM to the random access memory RAM is prohibited, and the switching request signal DS from the main digital controller MDC is sent to the backup digital controller.
Switching to BUDC is performed, the database is transferred and stored from the random access memory RAM of the switching device SW to the memory _MEMB of the backup digital controller BUDC, and the backup preparation is completed.

In this way, no matter how abnormal the main digital controller becomes, the validity of the error-free backup database can be guaranteed.

As explained above, according to the present invention, the validity of an error-free backup database can be guaranteed no matter how abnormal the main digital controller becomes, so the practical effects are extremely large. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a process control system equipped with a backup controller according to the present invention, FIG. 2 is a block diagram showing an extracted main part of the embodiment shown in FIG. 1, and FIG. Figure and 4th
The figure is a time chart for explaining the operation of the embodiment shown in FIGS. 1 and 2. MDC...Main digital controller,
BUDC...Digital controller for backup, SW...Switching device, MEM _M , MEM _B ...Memory, BM _M ...Buffer memory, CONT...Control circuit, G...Gate circuit, RAM...Random access memory.

Claims (1)

[Claims] 1 at least one main digital controller, a backup controller, and both said main digital and backup controllers connected to a data highway, in response to a failure of said main digital controller; In the process control system, a switching device is provided for transferring a database from the main digital controller to the memory of a backup controller, and a buffer memory is provided on the side of the main digital controller, and data is transferred to the input side of the buffer memory by a keyword signal indicating that the diagnosis result is normal. A control means for inhibiting writing is provided, and a random write operation is performed in the switching device based on a keyword signal indicating normality of the diagnosis result.
The access memory copies the contents of the buffer memory, and when an abnormality is found in the diagnosis result, the random access memory is copied from the buffer memory.
Writing to the memory is prohibited, and the database in the random access memory is transferred to and stored in the memory of the backup controller in response to a switching request signal from the main digital controller. A process control system equipped with an up-controller.