JPH03198136A - Check system for dma transfer data - Google Patents

Abstract

PURPOSE:To automatically check the data errors produced during the transfer of DMA data via hardware by providing a comparator which performs the comparison between the read and write data. CONSTITUTION:A write data temporary holding circuit 7 is provided together with a monitor starting switch 9, a writing action monitoring circuit 11 which monitors directly the transfer of data in response to the set output signal of the switch 9 and then outputs an end signal of the monitoring, and an address setting circuit 13 which sets the write address of the data that is directly transferred. Furthermore a read request circuit 15 is added to order a direct memory access controller 3 to read data out of a 2nd data storing device 5 in response to the end signal together with a comparator 17 which compares the data read out of the device 5 with the write data and checks the errors of the write data. In such a constitution, the errors of data can be automatically checked via hardware during the transfer of DMA data.

Description

[Detailed Description of the Invention] [Summary] Regarding a DMA transfer data check method that detects errors in DMA transfer data using hardware, the present invention aims to automatically perform error checking of data during DMA data transfer using hardware. , a digital processing system that directly transfers data from a first data storage device to a second data storage device under control of a direct memory access controller, a write data temporary holding circuit, a supervisory activation switch, and a supervisory activation switch. A write operation monitoring circuit that monitors direct transfer in response to a setting output signal and outputs a termination signal, a read request circuit that outputs a read request signal in response to the termination signal, an address set circuit, and a termination signal. a read request circuit that causes a memory access controller to directly start reading data from a storage location of a second data storage device specified by the address of the address set circuit; and data that is directly transferred to the second data storage device. An address set circuit for setting a write address of the second data storage device and a comparison circuit are provided, and the comparison circuit sets the data read from the storage location of the second data storage device
The configuration is such that the written data is checked for errors by comparing it with the written data.

[Industrial application field]

The present invention provides a DMA system that automatically detects errors in data written to memory during DMA data transfer using hardware.
Concerning a transfer data check method.

In addition to the internal memory of a computer system, digital exchange, etc., the system is sometimes configured by providing an external storage device with a larger capacity than the internal memory. Therefore, it is necessarily necessary to transfer data between the internal memory and the external storage device.

As a data transfer method between the two, DMA (Dir
ect Memory Access) data transfer method is often used. This is used because of the requirement for high speed digital transfer. In this data transfer, as in other data transfers, it is inevitable that errors will occur in the transferred data. Therefore, in the past, transferred data is checked to ensure that there are no problems with data processing. Such data checks are necessary both during system development and after the system is put into operation.

[Conventional technology]

As mentioned above, as the access forms to memory in systems that adopt the MA data transfer method become more diverse and complicated, memory depacking becomes complicated when a memory failure occurs, and data recovery becomes difficult. Extremely difficult. In particular, when a failure such as data destruction occurs due to fluctuations in the memory drive timing caused by various operational factors in the electronic circuit during a write operation to the memory, the subsequent write operation is It is possible to identify in which data write a data error has occurred, such as when the data continues, which makes depacking very difficult.

For this reason, as a transfer data check means in the DMA data transfer method, every time one access unit, for example, one word, is written to the memory, a read operation of the write data is caused to read the write data and the read data. A method has been adopted in which the transferred data is checked by comparing it with the data.

This transfer data checking method is currently carried out using a program specially prepared for depacking that reads one word after writing one word.

[Problem to be solved by the invention]

As is clear from the foregoing, due to the nature of the check procedure used in the transfer data check method, a program must be provided for each data check environment that requires checking the transfer data.

In other words, in the case of a failure that occurs only when a specific application program is executed, unless a program for checking the transferred data as described above is placed in the application program, the check for the failure cannot be performed. It is not possible to do this.

Therefore, not only does it take a lot of time to create a dehacking environment, but the transferred data cannot be checked unless you have special knowledge of the program target into which the program for checking the transferred data is installed. .

The present invention was created in view of such problems, and
It is an object of the present invention to provide a DMA transfer data checking method that can automatically perform data error checking in MA data transfer using hardware, regardless of who is the transfer entity of the data, subject to instructions.

[Means to solve the problem]

FIG. 1 shows a block diagram of the principle of the present invention. As shown in this figure, the present invention provides a digital processing system that directly transfers data in a first data storage device 1 via a direct memory access controller 3 to a second data storage device 5 via a data transfer path 4. The following components shall be provided. Its components include a write data temporary holding circuit 7 connected to the data transfer path 4 and holding write data to be written to the second data storage device 5; a monitoring start switch 9; a write operation monitoring circuit 11 that is connected and monitors the direct transfer and outputs an end signal thereof in response to the setting output signal of the monitoring start switch 9;
an address set circuit 13 connected to the data transfer path 4 and configured to set a write address for write data to be directly transferred to the second data storage device 5; a read operation request circuit 15 that causes the direct memory access controller 3 to start reading data from the storage location of the second data storage device 5 specified by the address;
This is a comparison circuit 17. The comparison circuit 17 compares the data read from the storage location of the second data storage device 5 specified by the write address of the address set circuit 15 under the control of the direct memory access controller 3, and The present invention is configured such that the comparator circuit 17 compares the write data held in the write data temporary holding circuit 7 to check for errors in the write data.

19 is a CPU.

[For production]

Prior to the start of direct data transfer from the second data storage device 1 to the second data storage device 5 by program execution in the CPU 19, the monitoring activation switch 9 is activated.
is set. When the direct transfer is started, the write address is set in the address set circuit 15, and the write data is held in the write data temporary holding circuit 7. The write operation monitoring circuit 11 that monitors the completion of this write outputs a completion signal when the direct transfer ends in response to the setting output signal from the monitoring start switch 9.

The read operation request circuit 13 in response to the end signal directly controls the memory access controller 3 to cause data to be read from the storage location of the second data storage device 5 specified by the address set in the address set circuit 15. .

The data read from the second data storage device 5 and the write data held in the write data temporary holding circuit 7 are compared by the comparison circuit 17 to check for errors in the write data.

Therefore, in DMA data transfer, the transfer data can be automatically checked by hardware. It is no longer necessary to prepare a dedicated program, which contributes to reducing the burden of creating an environment for its use.

〔Example〕

FIG. 2 shows an embodiment of the invention. This example is an example of a computer system. In Figure 2,
Memory 20 is connected to bus 22. Bus 22 has 1
Alternatively, a plurality of peripheral devices 24 and CPUI 9 are connected. Direct memory access controller 3, which controls DMA data transfers between memory 20 and peripherals 24, receives read/write (R/*W) command signals on bus 22 on line 23. This line 23 is in a high impedance state unless it is being used for writing or reading. As shown in FIG. 3, the read/write (R/*W) command signal has a relationship in which the *W command signal and the R command signal are inverted from each other. The direct memory access controller 3 inputs an address to the memory 20, RAS (Raw Address S tr
obe) signal, CA S (ColumnAddress
s Strobe ) signal and R/*W command signal.

The output of the switch 26 is connected to the write operation monitoring circuit 11 and the comparison circuit 27. The write operation monitoring circuit 11 has an input for receiving the R/*W command signal via the line 23 and also receives the DAC signal from the bus arbitration circuit 28.
It has inputs for receiving the KE signal and the DACKI signal, while having an output for sending the DREQI signal to the bus arbitration circuit 28, an output for sending the read operation activation signal to the read operation request circuit 15, and the direct memory access controller 3.
It has an output for sending an R command signal to. Said D
The ACKE signal is a response signal to the DREQE signal received from the CPU 19 via the bus 22, and is output in a suspended manner when there is a DREQI signal, which will be described later. As a response signal to the signal, the bus arbitration circuit 28 outputs a DACKI signal to the write operation monitoring circuit 11. The read operation request circuit 15
(Address 5trobe Internal
) signal to the latch 32 and the direct memory access controller 3. An address signal from bus 22 is applied to the input of latch 32 . This address signal, latch 3
The output of 2 is also fed to the address input of the direct memory access controller 3. Further, the ASI signal is transmitted through the ASE (Address Strobe) of the bus 22.
External) signal is directly supplied to the address strobe input of the memory access controller 3.

The data on bus 22 is also applied to the set inputs of latch 34 and latch 36, and the set inputs of latch 34 and latch 36 are input to corresponding inputs of comparator circuit 27. The error output of the comparison circuit 27 is sent to the CPU 19 as data on the bus 22.

In FIGS. 1 and 2, the memory of the peripheral device 24 is
Corresponding to the first data storage device 1 of FIG.
corresponds to the second data storage device 5 in FIG. The latch 34 is the write data temporary holding circuit ll17 in FIG.
The latch 32 corresponds to the address set circuit 13 in FIG. The switch 26 corresponds to the monitoring activation switch 9 in FIG. Comparison circuit 27 and latch 36 correspond to the comparison circuit shown in FIG. Furthermore, the write operation monitoring circuit 11 shown in FIG. 1 may be constructed by including the bus arbitration circuit 28 in the write operation monitoring circuit 11.

The transfer data check operation according to the present invention in the computer system configured as described above will be explained below.

In this system, the switch 26 is set before the CPU 19 starts controlling the DMA data transfer between the memory 20 and the peripheral device 24 (see ■ in FIG. 3). Following this, DREQE from CPU19
A signal (see ■ in FIG. 3) is transferred to the bus arbitration circuit 28 via the bus 22. As shown in FIG. 3 from the bus arbitration circuit 28, if the DREQI signal, which will be described later, is not received (if it is received, it is suspended), the DACK
The E signal is returned to the CPU 19 via the bus 22, and in response, an R/*W command signal (see ■ in FIG. 3) is sent from the CPU 9 via the bus 22 to the write operation monitoring circuit 1.
1 and the direct memory access controller 3, at the time when data is desired to be written to the memory 20,
The ASE signal (see ■ in FIG. 3) is sent directly to the memory access controller 3 via the bus 22, and the address signal (see ■ in FIG. 3) is sent to the latch 32 via the bus 22.
and is directly sent to the memory access controller 3. The R/*W command signal sent from the CPU 19 at a predetermined timing changes from its "H+t level to L".
1 level (see W shown in ■ in FIG. 3). At the time when this W command signal is given to the direct memory access controller 3, write data is also transferred from the CPU 19 to the direct memory access controller 3 via the bus 22 (see ■ in FIG. 3).
. The write data is latched in the latch 34 (see ■ in FIG. 3), and a write address signal, RAS signal, CAS signal, and W command signal are also sent to the memory 20 from the direct memory access controller 3. Therefore, the write data transferred to the memory 20 is written to the address of the memory 20 specified by the write address signal.

In parallel with this write operation, the write operation monitoring circuit 11, which is in the state of receiving each signal as described above,
* Sends the DREQI signal (see ■ in FIG. 3) to the bus arbitration circuit 28 in response to the level transition that occurs in the W command signal. The bus arbitration circuit 28 includes the write operation monitoring circuit 1
DACK for 1! A signal is sent back (see [Phase] in Figure 3).

Write operation monitoring circuit 1 in response to the 0DACKI signal
1 is a read operation request circuit 1 that reads a read operation start signal.
Send to 5. The read operation request circuit 15 receives the ASI signal (
0 in FIG. 3) to the latch 32 and direct memory access controller 3, and sends an R command signal to the line 23 which is in a high impedance state after the write operation is completed. The latch 32 latches the write address that has come to its input as a read address (see ■ in Figure 3), and its read address is:
Instead of the ASE signal, the ASI signal is applied to the address input of the supplied direct memory access controller 3. At the time when the read address and ASI signal are supplied, the R/*W command signal has been switched to the R command signal, so the read address, RAS signal, and
When the CAS signal and the R command signal are supplied, the data written in the command is read out from the memory 20 according to the read address, and is sent to the latch 3 via the bus 22.
6 and set there (see @ in Figure 3).

The read data set in the latch 36 is supplied to the comparator circuit 27 together with the write data previously set in the latch 34, and the comparator circuit 27 determines whether or not they match. If there is a mismatch, an error signal (ERROR) (see @ in FIG. 3) is transferred to the CPU 19 via the bus 22 and used for error processing.

In addition, although the above-mentioned embodiment was an example of data transfer from the peripheral device 24 to the memory 20 in a computer system, the case may be transferred in the opposite direction, and the present invention also applies to data transfer in a digital exchange etc. The implementation is not hindered in any way.

The above embodiment may be implemented in such a way that use of the bus 22 by other programs is prohibited during the DMA data transfer, without making the use of the bus 22 an essential requirement of the present invention.

Further, the set of switches 26 may be configured to notify the switch 26 that the above-mentioned check is required in various setting means, for example, program control.

〔Effect of the invention〕

As is clear from the above description, according to the present invention,
Debugging of data errors and failures occurring during DMA data transfer can be automatically performed by hardware without using a dedicated program. By providing a means for activating the method of the present invention for a program that performs data transfer, such as debugging a data error failure occurring during DMA data transfer, the effects of the present invention can be enjoyed by itself. Therefore, it contributes to the reduction of human labor, time, and expenses required for creating an environment for debugging and the like.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a diagram showing an embodiment of the present invention, and FIG. 3 is a timing chart of the embodiment of the present invention. 1 and 2, 1 is a first data storage device (memory of peripheral device 24), 3 is a direct memory access controller, 5 is a second data storage device (memory 20), and 7 is a Write data temporary holding circuit (latch 34), 9 is a monitoring start switch (switch 26), 11 is a write operation monitoring circuit, 13 is an address set circuit (latch 32), 5 is a read operation request circuit, 7 is a comparison circuit (comparison) circuit 27, latch 36). Unbearable 5 Rivers 1 (Boot '7 F Diagram 1■ On Immortality θ 8 Actual Field Series Timing Chart Ichito Diagram

Claims (1)

[Claims] (1) A digital device that directly transfers data from a first data storage device (1) to a second data storage device (5) via a data transfer path (4) under the control of a direct memory access controller (3). The processing system includes: a write data temporary holding circuit (7) connected to the data transfer path (4) and holding write data to be written to the second data storage device (5); and a monitoring activation switch (9). , a write operation monitoring circuit (1) connected to the data transfer path (4), which monitors the direct transfer and outputs a termination signal thereof in response to a setting output signal of the monitoring start switch (9);
1); an address set circuit (13) connected to the data transfer path (4) and configured to set a write address for data to be directly transferred to the second data storage device (5); and in response to the termination signal. and the address set circuit (13
) the second data storage device specified by the address of (
A read operation request circuit (15) for causing the direct memory access controller (5) to start reading data from the storage location of 5) and a comparison circuit (17) are provided, and the comparison circuit (17) The address set circuit (1) is operated under the control of the access controller (3).
5) Compare the data read from the storage location of the second data storage device (5) specified by the write address with the write data held in the write data temporary holding circuit (7). A DMA transfer data check method, characterized in that the write data is checked for errors.