JPS6230105Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application] The present invention relates to a parity check circuit during memory access in a microcomputer.

[Conventional technology]

A microcomputer (hereinafter referred to as the CPU) executes various processes while reading and writing instructions and various data stored in the memory (hereinafter referred to as the MEM), but when the CPU accesses the MEM, the data is If a failure occurs, there is a problem in that normal commands or processing cannot be executed.

FIG. 1 is a block diagram showing a conventional example.
When the CPU executes instructions and processes, it accesses the MEM to read and write. In Figure 1,
The CPU specifies which word of the MEM to read using address buses ABo, AB1, ..., ABj.
When MEM writes to the contents of the word specified by this address bus, a write instruction is specified by the CPU, and at the same time, the data bus DBo,
Write the contents specified in DB1,...,DBn. or,
When reading, a read instruction is specified by the CPU. When a read instruction is specified, the MEM sends the contents specified by the address bus to the data buses DBo, DB1, . . . , DBn and sends them to the CPU.

When the CPU reads and writes to MEM,
The MEM uses a ready information signal (RDY
It's called a signal. ), and when this RDY signal is sent from the MEM to the CPU, a read or write operation is performed.

[Problem that the invention attempts to solve]

As described above, when executing CPU commands and processing, the contents of the data bus are read and written. However, if the contents of the data bus become impaired (bit failure in MEM, bit failure on the bus, or bit change due to noise) etc.), in the conventional system like this example, no measures are taken to prevent bit changes; for example, if the content of the data bus is a command, it can be changed to a command or another command. It becomes impossible to execute the program, and the program runs out of control or stops. Furthermore, if the contents of the data bus are data, the arithmetic processing related to the data becomes chaotic, the arithmetic processing function is stopped, and the computer cannot function as a computer.

The purpose of this invention is to immediately detect a functional stoppage due to a data bus bit failure, take action to deal with the failure, notify maintenance personnel of the failure display, and have them repair the failure. An object of the present invention is to provide a parity check circuit capable of relieving abnormal operation.

[Means for solving problems]

The parity check circuit of the present invention is connected to the data bus in a data processing device in which a central processing unit composed of a microcomputer writes and reads data to and from the check circuit device via the data bus, and when the central processing unit writes the data to the storage device, a predetermined parity bit is generated according to the parity of the data written under the control of the central processing unit, and the central processing unit writes the data to the storage device. a parity bit generation circuit that outputs the parity bit so that the parity bit can be written together with the data into the device; and a parity bit generating circuit that is connected to the data bus and when the central processing unit reads the data from the storage device. The parity of the data read out together with the data from the storage device is verified under the control of the central processor, and when the parity of the data read out is normal as a result of the verification, the central processing A parity normal signal is output to the peripheral device ready information signal terminal of the microcomputer constituting the device so that the central processing unit continues normal processing operation, and when an abnormality occurs, the parity normal signal is output to the peripheral device ready information signal terminal of the microcomputer constituting the device. The present invention is characterized in that it includes a parity check circuit that outputs a parity abnormality signal to either the initial setting information signal terminal or the interrupt information signal terminal so that the central processing unit starts an abnormality processing operation.

〔Example〕

Next, the present invention will be explained with reference to the drawings.
FIG. 2 is a block diagram showing one embodiment of the present invention. When the CPU writes to the MEM, a parity bit information signal (hereinafter referred to as P signal) is generated from the contents of the data bus in a parity bit generation circuit (hereinafter referred to as PG), and is written into the MEM each time the data is written. (The parity check method is a well-known method and includes an even parity check method and an odd parity check method.The even parity check method is based on the sum of the 1s of the data bit logic 1 and 0 and the sum of the 1s of the logic 1 and 0 of the parity bits. The parity bit is set so that the total is an even number. In the odd parity check method, the parity bit is set so that the sum of the logic 1s and 0s of the data bits and the sum of the logic 1s and 1s of the parity bits is an odd number. If there is a promise like this, for example, if a bit change occurs when the contents of the data bus are read, it is possible to determine whether the parity is normal or abnormal by comparing the parity bit with the parity bit of the data bus contents.)CPU
After writing data to MEM (the program is
Since it is initially written in MEM as ROM, the CPU
There is no addition of parity bits as writes from. ) When reading data later (programs are read as instructions), the CPU checks the contents on the data bus and the contents of the parity bits using a parity check circuit (hereinafter referred to as PC) to determine whether the parity is normal or abnormal. judge. If normal, the CPU
Since the RDY signal is sent to the CPU from the OK terminal of the PC, the CPU executes normal processing because the reading is normal. Also, in case of abnormality
No output appears at the OK terminal of the PC, but information appears at the ERR terminal, and this information enters the CPU as the CPU's initial setting information signal (hereinafter referred to as the RST signal), and the CPU inputs from the RST terminal, which causes a parity error. Knowing this, you can handle future failures.

In the above description of an abnormality, the RST terminal of the CPU was used to notify the CPU of the abnormality, but it is also possible to use an interrupt information signal (hereinafter referred to as the INT signal) instead of the RST signal for interrupt operation. However, in this state, it depends on how the program is assembled.
Since the CPU may not be able to accept interrupts, the INT signal may not be able to notify the CPU of an abnormality at any time.

The above explanation will be explained in more detail with reference to FIG. When writing, the CPU uses address buses ABo, AB1, ..., to specify the word to be written.
Specify the write address in ABj. data bus
The contents of the write are sent to DBo, DB1,..., DBn, and the contents are sent to the data bus connected to PG.
A parity bit is created from the data on DBo, DB1, . When reading, the CPU uses address buses ABo and AB to specify the word to be read again.
Specify the read address in 1, ..., ABj. Data in the MEM appears on the data buses DBo, DB1,..., DBn, and the PC compares this with the P signal read out from the MEM under the control of the CPU's read information signal (hereinafter referred to as the R signal). If this verification is correct, the PC outputs a parity normal signal (hereinafter referred to as OK signal) to the CPU. This passes through the OR gate circuit OR and reaches the RDY terminal of the CPU, and it can be determined that the MEM is ready for reading, that is, the parity is normal. When an error occurs, the PC outputs an output to the ERR terminal because the result of comparing the information on the previous data buses DBo, DB1, ..., DBn with the P signal is abnormal, and this is output as the CPU's RST signal or INT signal.
The CPU is notified, the CPU detects that a parity error has occurred, and can execute appropriate subsequent processing. In addition, the RDY signal from the MEM is used to notify the CPU that the MEM is ready for writing when writing to the MEM.

[Effect of idea]

By carrying out the present invention and performing a parity check at the time of reading, it is possible to avoid failures such as program runaway and stoppage due to changes in execution instructions, and situations such as inability to process data due to changes in data. As in this circuit, the CPU's peripheral device readiness information signal, or RDY signal, is used to determine whether parity is normal, or the initial setting information signal, or RST signal, or the interrupt information signal, or INT signal, is used in the event of an abnormality. Alternatively, data can be prevented from being taken in by the CPU, and appropriate failure handling can be performed. For example, if the occurrence of parity error is due to noise, etc., the CPU repeats reading data from the MEM several times, thereby preventing noise-induced disturbances (bit changes, etc.). Furthermore, in the event that an actual hardware failure occurs, it is possible to discover the failure location at that time and prevent the failure from becoming latent and expanding, making it possible to understand that the present invention is extremely effective. Moreover, as shown in the embodiment of the present invention, the present invention simply connects the parity check circuit to the data bus and notifies the parity check result as a CPU peripheral device readiness information signal, initial setting information signal, or interrupt information signal. The present invention provides a parity check circuit which is characterized by being able to discover faults using a very simple and economical method that requires a small amount of hardware.

[Brief explanation of the drawing]

Figure 1 is a block diagram of an example of a conventional method; Figure 2 is a block diagram of an example of a conventional method;
The figure is a block diagram of one embodiment of the parity check circuit of the present invention. CPU: Microcomputer, MEM: Memory, PC: Parity check circuit, PG: Parity bit generation circuit, OR: OR gate circuit, AND: AND gate circuit, ABo, AB1,
…, ABj……address bus, DBo, DB1, …,
DBn...data bus, Ao, A1,..., Aj...address bus information terminal, Do, D1,..., Dn...data bus information terminal, W...write information signal terminal,
R...Read information signal terminal, RDY...Peripheral device ready information signal terminal, RST...Initial setting information signal terminal, INT...Interrupt information signal terminal, P...
Parity bit information signal terminal, OK... Parity normal signal terminal, ERR... Parity abnormal signal terminal.

Claims (1)

[Claims for Utility Model Registration] A data processing device in which a central processing unit composed of a microcomputer writes and reads data to and from a storage device via a data bus, and When the central processing unit writes the data to the storage device,
Generating a predetermined parity bit according to the parity of the data written under the control of the central processing unit, and outputting the parity bit so that the central processing unit can write the parity bit together with the data in the storage device. a parity bit generation circuit connected to the data bus and read out together with the data from the storage device under control of the central processing unit when the central processing unit reads the data from the storage device; The parity of the data read out according to the above is verified, and if the parity of the data successively read out is normal as a result of the verification, the central A parity normal signal is outputted so that the processing unit continues normal processing operation, and when an abnormality occurs, a parity normal signal is output to either the initial setting information signal terminal or the interrupt information signal terminal of the microcomputer constituting the central processing unit. A parity check circuit comprising: a parity check circuit that outputs a parity abnormality signal so that a parity error signal starts an abnormality processing operation;