JP3350069B2 - Bus line monitoring method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus line monitoring system used in a computer system for performing high-speed data transfer with an external device using a CPU, a DMA, and the like. The present invention relates to a bus line monitoring system improved from the above.

[0002]

2. Description of the Related Art FIG.
The bus line 2 derived from the CPU 1 has D
An MA (direct memory acces) 3, a memory 4, a peripheral I / O 5, an input / output interface 6, and the like are connected, and a communication control device 9 as an external device is connected to the bus line 2 via a communication control interface 7. I have. The CPU 1 controls all the components based on a predetermined program.
1 has a function of transferring data of memory information between the memory 4 and the communication control device 9 without using the CPU 1 while sharing the bus line 2. 8 is RAS (reliability: reli
ability, Availability: availability, Serviceability: serviceabi
lity) unit, which has a function of diagnosing a hardware error such as a memory parity error and stores an error address and the like.

Therefore, in the computer system described above, the CPU 1 manages the communication control interface 7 based on a program, and also manages data tracing and the like in the same manner. The memory information is transmitted in response to a data request from the communication control device 9.

That is, when obtaining memory information from an external device, for example, the communication control device 9, the CPU 1 controls the communication control interface 7 and connects the communication control device 9 to the communication control interface 7. From outside via the communication control interface 7 and the bus line 2. Also, regarding the memory information stored in the memory 4 or the like inside the system,
The CPU 1 reads out memory information from the memory 4 and transmits it to the communication control device 9 via the bus line 2 and the communication control interface 7.

[0005]

However, in the above-described computer system, since the CPU 1 has all control functions, the communication control interface 7 is controlled, for example, when the CPU 1 is in a failure or abnormal state. This makes it impossible to obtain memory information from the outside. If the CPU 1 stops while occupying the bus line 2, other necessary constituent functions cannot access the bus line 2.

[0006] The present invention has been made in view of the above circumstances, and even when the CPU is down , the memory information can be easily read from an external device.
It is an object of the present invention to provide a bus line monitoring method capable of acquiring information .

Still another object of the present invention is to provide a bus line monitoring system capable of releasing the occupation of the bus line by the CPU and the DMA and easily acquiring memory information from an external device from a memory connected to the bus line. Is to provide.

[0008]

Means for Solving the Problems First, in order invention corresponding to claim 1 to solve the above problems, DMA and a communication control interface is connected to the bus line that will be derived from the CPU, external to the communication control interface In a computer system connected to devices, at least between the bus line and the communication control interface.
Bus monitoring means having a memory for tracing is also provided,
During the operation of the CPU, the bus monitoring means transmits the trace information from the external device to the bus line via the bus line.
When it is determined that the data input / output instruction of U is executed, the data is written into the trace memory,

When the CPU is down, the external device
A bus line monitoring method for reading trace information stored in the trace memory via the communication control interface and the bus monitoring means.

Next, a second aspect of the invention provides a bus release control means newly added to the first aspect of the invention.
When the bus release control means matches the address set by the external device with the address of the CPU, it stops the operation of the CPU and the DMA to release the bus line, and the external device transmits the bus line via the bus monitoring means. This is a bus line monitoring method for accessing information such as memories and I / O connected to the bus line.

[0011]

Therefore, according to the invention corresponding to claim 1, by taking the above means, when the trace information including the trace memory address is transmitted from the external device,
The bus monitoring means monitors the address and data of the CPU on the bus line, and when it is detected that the CPU is executing the data input / output instruction when the address of the CPU is the same as the memory address for tracing, the trace information is read. The external device reads the trace information stored in the trace memory via the communication control interface and the bus monitoring means, thereby saving the external device via the CPU when the CPU goes down. The trace information can be extracted without the need.

Next, in the invention corresponding to claim 2, the bus release control means controls the address and CP set by an external device.
The bus line is released by stopping the operation of the CPU and the DMA while observing the address of U, so that information such as memory and I / O connected to the bus line from the external device via the bus monitoring means can be obtained. Can be accessed.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIG. Incidentally, a detailed description thereof will be denoted by the same reference numerals with a conventional computer <br/> system (FIG. 3) in the figure is omitted.

That is, this computer system includes:
A bus monitoring interface 11 and a trace control means 12 are newly provided between the bus line 2 and the communication control interface 7. This bus monitoring interface 1
Numeral 1 determines whether the instruction is a command fetch cycle of the CPU 1 or an instruction to input / output data to / from the memory 4 or the I / O, and when the data input / output instruction is executed, sends an instruction to write trace information from an external device as described later. On the other hand, the trace control means 12 has a function of controlling the communication control interface 7 and the like and setting trace information from the communication control device 9 in the trace information setting section 13.

Further, the system is provided with trace information for setting trace information such as R / W data and the number of times for a specific memory address, and further, trace information such as DMA trace information and I / O input / output information. Address conversion means 14 for efficiently converting trace information into an address signal for writing trace information without using the CPU 1, DMA3 or I / O address other than the setting unit 13.
And a trace memory 15 such as a RAM, an IC card or another hard disk for storing trace information under the address signal from the address conversion means 14.

Next, the operation of the above system will be described. Here, an example of tracing memory data and the number of executions when input / output is performed at a specific address will be described.

First, when condition setting data such as a memory address, memory data, and the number of times of execution are input from an external communication control device 9 or the like, the communication control interface 7 performs a transmission error check on the condition setting data and then performs necessary error checking. The condition setting data is extracted and sent to the trace control means 12. Here, the trace control means 1
2, converts the condition setting data from the communication control interface 7 to the trace information necessary to set the trace information setting unit 13.

In the bus monitoring interface 11, when the trace information is set in the trace information setting unit 13, the address of the CPU 1 on the bus line and the input / output command data of the bus line 2 are monitored. When the input / output instruction is executed at the same address as the address set in the address 13, the fact is sent to the address conversion means 14 via the trace information setting unit 13. Here, the address conversion means 14 converts the address set in the trace information setting section 13 into a trace memory address, writes the trace information into the trace memory 15 using the converted address, and further writes the trace information into the trace memory 15. “1” is added and the execution count data is saved.

On the other hand, when the external communication control device 9 reads out the trace information, the communication control device 9 sends out transmission data for data reading including address data. Here, when the communication control interface 7 receives the transmission data and passes it to the trace control means 12, the trace control means 12 reads out the trace information from the trace memory 15 under the address, and via the communication control interface 7, The data is transmitted to the external communication control device 9 by data transmission.

Therefore, according to the method of the above-described embodiment, when the CPU 1 goes down due to an abnormality, the trace control means 12 receives the transmission data of the data read including the address data from the external communication control device 9, and Necessary data such as a trace of the input / output data and the number of input / output times for the memory 4, a trace of the input / output data and the number of input / output times for the I / O, a trace of the instruction execution, and the like can be easily read from the trace memory 15. further,
Since the communication control device 9 does not pass through the CPU 1, the data from the DMA 2 can be easily traced using the bus line 2.

FIG. 2 is a diagram showing a hardware configuration of a computer system to which another embodiment of the present invention is applied. In this system, since the CPU 1 or the DMA 3 may occupy the bus line 2 in the event of its own failure, the bus release interface 2 is used to forcibly release the bus.
1 and a bus release control means 22. That is, when the CPU 1 cannot operate due to a watchdog timer error or a memory parity error, the bus release control means 22 compares the address set from the communication control device 9 with the address of the CPU 1 stored in the RAS unit 23. If these addresses match, the CPU 1 or D
The operation of MA3 is stopped to release bus line 2. As a result, the communication control device 9 can access information such as the memories 4 and I / O connected to the bus line 2 via the bus release control means 22 and the bus monitoring interface 11.

Further, the bus release unit 22, it is possible to hold the CPU1 through the bus open interface 21 based on the detection signal from the sheet ring Le step detector per instruction trace information setting unit 13, whereby The operation of the CPU 1 can be executed for each single step.

[0023]

As described above, according to the present invention, the following effects can be obtained. In the invention of claim 1, C
Even when the PU is down, the information of the trace memory can be easily obtained from the external device.

Next, in claim 2, the CPU and the DMA
, The information on the devices connected to the bus line can be easily obtained from the external device.

[Brief description of the drawings]

FIG. 1 is a hardware configuration diagram showing one embodiment of a computer system to which a bus line monitoring system according to the present invention is applied.

FIG. 2 is a hardware configuration diagram showing another embodiment of the computer system to which the bus line monitoring system according to the present invention is applied.

FIG. 3 is a hardware configuration diagram of a computer system to which a conventional method is applied.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... CPU, 2 ... bus line, 3 ... DMA, 4 ... memory, 7 ... communication control interface, 9 ... communication control device (external device), 11 ... bus monitoring interface, 12 ...
Trace control means, 13: Trace information setting unit, 14 ...
Address conversion means, 15: trace memory, 21: bus release interface, 22: bus release control means.

Claims (2)

(57) [Claims] [Claim 1] DM to the bus line that will be derived from the CPU
A and a communication control interface are connected, and in a computer system in which an external device is connected to the communication control interface , between the bus line and the communication control interface
Bus monitoring means having at least a trace memory is provided.
During the operation of the CPU, the bus monitoring means sends a CP from the bus line to trace information from the external device.
When it is determined that the data input / output instruction of U is to be executed, the data is written into the trace memory. When the CPU is down, the external device stores the data in the trace memory via the communication control interface and the bus monitoring means. A bus line monitoring system characterized by reading trace information stored in the bus line. 2. The bus line monitoring system according to claim 1 ,
In the above, a bus release control means is added between the bus monitoring means and the CPU and the DMA, and the bus release control means makes an address set by the external device and a CPU address. when matched, of stopping the operation of the the CPU DMA
The bus line is opened to allow access from the external device to information such as memory and I / O connected to the bus line via the bus monitoring means.