JPH01232454A - Test system for address bus - Google Patents

Abstract

PURPOSE:To quickly test an address bus by setting a register on an address bus of a conventional circuit and executing an address bus test program with addition of a small number of circuits including a gate circuit, etc. CONSTITUTION:A register 4 has its output connected an input/output controller 3 and its input connected to an address bus line 10 respectively. An output line 22 is added to the controller 3 to transmit a turn-on signal when the 1st specific data is sent to the controller 3 and to turn off said turn-on signal when the 2nd specific data is sent to the controller 3. Then the gate circuits 23 and 25 latch the contents of the line 10 supplied to the register 4 by the memory read signal that is transmitted only when data are read out of a memory at output of a turn-on signal through the line 22. A CPU 1 latches the signals having all bits '0' and '1' sent to the line 10 via the register 4 and reads these signals out of the register 4 via the controller 3 to check the coincidence between this latched signal with the signal sent previously to the line 10.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an address bus testing method, and more particularly to an address bus testing method for microcomputers.

[Conventional technology]

Conventionally, this type of address bus test method uses a microcomputer.1. ``The system consists of a central processing unit that executes programs, memory that stores the programs, and various input/output control devices.There is no dedicated circuit for testing the address bus, and there is no program runaway check or memory It also serves as an address bus test by performing a memory test in which a certain value is written and read to check whether the data is the same.

[Problem to be solved by the invention]

In the conventional AT/S bus test mentioned above, when an error or runaway occurs, the error location is located in the memory.

It is not easy to determine whether it is a data bus or an address bus. Especially when the work area is at an older address than the program area, or when the work area address uses an address that is not used in the program area, there is a problem that the program appears to operate normally even if this address is abnormal. .

For example, 1000 from address O of the program (IIEX)
address (address bus 212 bits only “1”), work area is 1001 ()IEX) address (address bus 2
t 2.2o bit “'1”) to 3000()IE
X) address (address bus 213.') 12 bits "1"
In the program (2), when the address bus 213 bits are stuck at 0, the 213 bits in the program area remain 0 and operate normally, but the program reads the contents of address 3000 (HEX) in the work area. Since 213 bits are stacked at 0, the contents of address 1000 (IIEX') are read and the program is executed using the abnormal data.

[Means to solve the problem]

The address bus test method of the present invention is applicable to a microcomputer system in which a central processing unit, a memory that stores a program, and an input/output control device are connected to a common address bus line and a common data bus line. and a register whose output is connected to the address bus line and whose input is connected to the address bus line, outputs an on signal when the first specific data is transferred to the input/output control device, and outputs an on signal when the second specific data is transferred to the input/output control device. An output line provided to the input/output control device that turns off the on signal, and a memory read signal that is sent only when reading data from the memory when the on signal is output from this output line are input to the register. A gate circuit is provided to latch the contents of the address bus line, and the central processing unit causes the register to latch the signals of all bits °°0'' and all pins '1°'' sent to the address bus line, and It is constructed by reading the signal latched in the register via the output control device and checking whether this signal matches the signal previously sent to the address bus line.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

This embodiment includes a central processing unit 1 for executing programs, a memory 2 for storing programs, an input/output control device 3 for controlling various input/output devices, a register 4 for storing address bus data, and a control signal for creating various control signals. Generation circuit 5
, a flip-flop 6 for gate control, an AND circuit 7, a signal inversion circuit 8.9, an address bus line 10, a data bus line 11, a memory request line 12. IO request line 13, read line 14, write line 15, first machine cycle line 16, memory read line 17, memory write line 18
, ■0 lead line 19, IO write line 20, register content output line 21, tarok line 22, gate line 23, 25 . It is composed of a data set signal line 24.

FIG. 2 is a flowchart of a program stored in the memory 2 for the address bus test of the present invention, and the operation of FIG. 1 will be explained below with reference to FIG. First, the central processing unit 1 writes an address A to an internal register.
Set LL "0" (step ■).

Next, an ON signal is sent from the gate line 23 from the input/output control device 3 (step 2). This procedure is performed as follows. First, central processing unit 1 sends the contents of the program counter to address line 10 at the timing of machine cycle M1 shown in FIG. Next, the central processing unit 1 sends signals to the memory request line 12, the lead line 14, and the first machine cycle line 16. Memory request line 1
2. The signal on the lead wire 14 is input to the control signal generation circuit 5, converted into a memory read signal, and input to the memory 2 via the memory lead wire 17. When memory 2 receives this signal, it sends the contents of memory 2 to data bus line 11. The central processing unit 1 receives this content and knows that it is an output command, and since it is an output command, the address bus line 1 is read in order to read the address of the output device from the memory 2.
Add 1 to the program counter to 0 and send the address.
A signal is sent to the memory request line 12 and the lead line 14 (at this time, no signal is sent to the first machine cycle line 16. The signal on the first machine cycle line 16 is sent only when reading the instruction code). . These signals are converted into memory read signals by the control signal generation circuit 5 and input to the memory 2 via the memory lead line 17, and the memory contents (address of the output device) are sent from the memory 2 to the data bus line 11. , the central processing unit 1 receives this content. When the central processing unit 1 knows the address of the output device, it sends the address of the output device received from the memory 2 to the address bus line 10 at the timing of machine cycle M3 shown in FIG. , and sends signals to the IO request line 13 and write line 15. This signal is converted into an IO write signal by the control signal generation circuit 5, and the IO write line 2
0 to the input/output control device 3. Therefore, the input/output control device 3 latches the first specific data on the data bus line 11 at the same time as receiving the ■○ write signal, and sends an on signal to the gate line 23 in accordance with this data. Note that this on signal turns on the gate of the AND circuit 7, and turns on the gate of the AND circuit 7.
Release the reset of the I block flop 6 (■○ The timing of the write signal and the ON signal of the gate line 23 is the machine cycle M3 of the output command as shown in FIG. 3.) Next, the address set in step ■ Read the memory contents (step ■). In this case, the central processing unit 1 reads the instruction code from the memory 2, determines that it is an instruction to read the contents of the internal register set in step ①, and addresses it in the next machine cycle M2 (M2 of the read instruction in Figure 3). ALL "O" is sent to the bus line 10, and signals are sent to the memory request line 12 and lead line 14. These signals are converted into memory read signals by the control signal generation circuit 5, and are input to the memory 2 via the memory lead line 17, and simultaneously input to the AND circuit 7. Memory 2 is 0
The content of the address is sent to the data bus line 11 and received by the central processing unit 1, but this content is unnecessary for the address bus test and is therefore invalidated in the program. Also, since it only reads memory, it does not affect the program in any way. On the other hand, the reset of the flip-flop 6 has already been canceled by the ON signal of the gate line 23 from the input/output control device 3.
Since the output signal of the flip-flop 6 opens the gate of the AND circuit 7 via the gate line 25, the memory read signal input to the AND circuit 7 is output from the AND circuit 7, and this signal is sent to the signal inversion circuit. 9 and input to the register 4 as a latch signal of the input signal of the register 4.

At this time, the address of address 0 is still being output to the address bus line 10, and ALL "°0" is latched in the register 4. Further, the flip-flop 6 is reset by the inverted signal of the memory read signal output from the signal inverting circuit 9, and the gate of the AND circuit 7 is closed.

Next, the central processing unit 1 turns off the on signal of the gate line 23 from the input/output control unit 3 (step 2). This procedure is the same as step (2), except that instead of sending the first specific data to the input/output control device 3 in step (2), second specific data is sent. gate line 23
Since the off signal is output from , the gate of the AND circuit 7 remains closed and the gate line 25 of the output of the flip-flop 6 is turned on, but no new data is latched into the register 4. It disappears.

Next, the central processing unit 1 reads the contents of the register 4 via the input/output control unit 3 (step 2). This procedure is performed by regarding the register 4 as one input/output device connected to the input/output control device 3.

Next, the central processing unit 1 checks whether the read contents of the register 4 match the contents of the internal address set in step (2) (step (2)). As a result, check whether the contents of the internal address are ALL “0°” (step ■
), if ALL is “0”, the contents of the internal address are all
Set it to “1” (step ■). Next, return to step ■.

If they do not match in step ■, an error is displayed as an error (step ■). Also, in step ■ ALL”O
” otherwise it will end.

Through the above processing, the central processing unit
It is possible to check whether the data is output without error by sending ALL "0" and ALL "1'° to the address bus line, and a stack failure in any bit line of the address bus line can be detected.

〔Effect of the invention〕

As explained above, the present invention can quickly test the address bus by providing a register in the address bus line of the conventional circuit, adding a few circuits such as gate circuits, and running the address bus test program. effective.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a flow chart of an address bus test program of the present invention, and FIG. 3 is a time chart of the main signals in FIG. l... Central processing unit, 2... Memory, 3... Input/output control device, 4... Register, 5... Control signal generation circuit, 6... Flip-flop, 10... Address Bus line, 11...data bus line.

Claims (1)

[Claims] In a microcomputer system in which a central processing unit, a memory for storing programs, and an input/output control unit are connected to a common address bus line and a common data bus line,
a register having an output connected to the input/output control device and an input connected to the address bus line; and a register that outputs an on signal when first specific data is transferred to the input/output control device and transmits second specific data. an output line provided in the input/output control device that turns off this on signal when the on signal is transferred, and a memory read signal that is sent only when reading data from the memory when the on signal is output from this output line. A gate circuit is provided to latch the contents of the address bus line input to the register, and the central processing unit latches all bits "0" and all bits "0" sent to the address bus line.
1'' signal is latched in the register, the signal latched in the register is read through the input/output control device, and it is checked whether this signal matches the signal previously sent to the address bus line. Address bus test method.