JPS6339050A - Address bus test circuit - Google Patents

Abstract

PURPOSE:To quickly carry out tests for the abnormal working of a program and an address bus by setting an address where all address buses are set at '1' as well as a 0 address to an address bus and securing an exclusive OR between a signal line led from an input/output controller and said address bus. CONSTITUTION:A 0 address is set to an address bus line 12 and the comparison data is set at '0'. Then an exclusive OR is secured by an exclusive OR circuit 4 and therefore a stack '1' of the line 12 is known. Then an address FFFF is set to the line 12, the comparison data set at '1' respectively and an exclusive OR is secured by the circuit 4. Thus a stack '0' of the line 12 is obtained. In other words, if a signal adverse to an input signal is supplied to a part of the line 12, the exclusive logic element of that area has discordance of input. Then '1' is outputted from the logic element and an NOK signal is outputted to an output line 28.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an address bus test circuit, and more particularly to an address bus test circuit in a computer.

[Conventional technology]

Conventionally, in computers equipped with a central processing unit that executes programs, memory that stores programs, and various input/output control devices, a fault in the address bus causes a 0" or °"1"
It is not tested in terms of hardware that the value is fixed to the value (hereinafter referred to as stack), but it is written to the memory and then checked to see if the value read out is the same as the written value. The address bus was tested by

[Problem that the invention seeks to solve]

In the conventional address bus testing method described above, when an error occurs, it is not possible to determine whether the error location is in the memory, data bus, or address bus.Especially when the work area is older than the program area If an address bit that is not used in the program area is used in the work area address, there is a drawback that the program will apparently operate normally even if this bit is abnormal.

For example, the program area is from address 0 to 1000 (1-1
) address (only address bus 212 bits are “1 pass”), work area is 1001 (H) address (address bus 12
12.2° bit is 1”) to 3000 (l() address (
When address bus 1213.212 bits are stuck at "0" in an 11 program, the 213 bits remain at "0" in the program area and operate normally, but when the program area is moved from the work area 3000 ()! >When the contents of the address are read, 213 bits are stacked at 0'', so the contents of the address 10oo (H) are read and the operation is performed using the abnormal data.

[Means for Solving the Problems] The address bus test circuit of the present invention includes a central processing unit that executes a program, a memory that stores the program, various input/output control devices, and an address bus test circuit from the central processing unit. and a signal line from the input/output control device; a flip-flop that latches the result of the exclusive OR circuit; and various timing circuits for performing this latching. and test the address bus by setting an address where the O address and the address bus are all "1" on the address bus, and performing an exclusive OR of the signal line from the input/output control device and the address bus. are doing.

〔Example] Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, this embodiment shows a central processing unit 1, a memory 2. Input/output control device 3. Exclusive OR circuit 4. Control signal generation circuit5. Flip-flop 6.7. AND circuit 8. Inverter 9, 10.11, address bus line 12. Data bus line 13. Memory request line 14. Input/output request line 15, lead line 16. Light line 17. Memory lead wire 1
8. Memory write line 19. Input/output lead wire 20, input/output lead wire 21. Machine cycle 1 line 22, result output line 2
3,28. Comparison data line 24° gate line 25, 27. A resultant latch line 26 is provided.

FIG. 4 is a program flow diagram for operating the embodiment shown in FIG. 1, and is stored in the memory 2. As shown in FIG. Further, FIG. 3 is a timing chart showing the operation timing in FIG. 1.

Next, the operation of the present invention will be explained.

The central processing unit 1 sequentially loads the programs shown in FIG. 4 from the memory 2 and executes them. The program \40 sets an address in a register within the central processing unit 1.

In the program 41, in order to load the instruction food from the memory 2, the central processing unit 1 is connected to the address bus so that the contents of the program counter in the central processing unit 1 are output at the timing of the instruction fetch cycle M1 shown in FIG. Sends the contents of the program counter on line 12. Next, the central processing unit 1 requests memory request vi1 in order to read the memory contents indicated by the program counter.
4. Lead wire 16. A signal is sent to the machine cycle 1 line 22. Memory riff varnish 1 to line 14. The signal on the lead wire 16 is input to the control signal generation circuit 5, converted into a memory read signal, and input to the memory 2 through the memory lead wire 18. When the memory 2 receives this signal, it sends the contents of the memory (instruction code) to the data bus line 13, and the central processing unit 1 receives this instruction code and knows that it is an output instruction.

Next, the central processing unit 1 sends the address of 10 gram counter + 1 to the address bus line 12 in order to read the address of the output device from the memory 2, and then immediately sends the address of the 10 gram counter +1 to the memory request line 1.1. When a signal is sent to the lead wire 16, no signal is sent to the machine cycle 1 line 22.

This signal on the machine cycle 1 line 22 is a signal sent only when reading an instruction code). These signals are converted into memory read signals by the control signal generation circuit 5 and input to the memory 2 through the memory lead wire 18.
The contents of the memory (the address of the output device) are sent to the data bus line 13, and the central processing unit 1 reads them. When the central processing unit 1 knows the address of the output device, the central processing unit 1 sends the address of the output device that has already been read out to the address line 12 in order to send the data at the timing of machine cycle M3 shown in FIG. Then, the comparison data ``0'' and gate-on data shown in the program 41 are sent to the data bus line 13, and the input/output request line 15. A signal is sent to the light line 17. This signal is converted into an input/output collider signal by the control signal generating circuit 5 and input to the input/output control device 3 through the input/output collider line 21. The input/output control device 3 has an address match with the output device address that has already been sent to the address bus line 13, and at the same time it receives the input/output signal, it latches the data on the data bus line 13 and transfers it to the comparison data line 24.
Set 0゛, turn on line 25 to game l, and circuit 8
Turn on the gate 1~ of the flip-flop 6.7 to release the reset 1~ of the flip-flop 6.7 (the timing of the input/output signal, comparison data, and gate signal is turned on at the input/output cycle M3 of the output command as shown in Figure 3). become).

Next, the program 42 reads the address O, so the central processing unit 1 reads the instruction code and disconnects the instruction to read the contents of the address by 1'Il as described above.
Next memory read cycle M2 (M of read command in Figure 3)
2> sends address 0 to the address bus line 12. next,
In order to read the contents of address 0, the central processing unit 1 sends a signal to the memory request line 14 and the lead wire 16, and the signal is converted into a memory read signal by the control signal generation circuit 5, passes through the memory lead wire 18, and is sent to the memory 2. At the same time, it is also input to the AND circuit 8.

The memory 2 sends the contents of address 0 to the data bus 13 and is read by the central processing unit 1, but this content is invalidated in the program. Also, only reading memory has no effect on the program. On the other hand, the memory read signal input to the AND circuit 8 releases the reset of the flip-flop 7 due to data 1 to ON already set in the input/output control device 3, and the output signal of the flip-flop 7 is transferred to the gate line 27. Since the gate of the AND circuit 8 is turned on through the inverter 11, the output of the AND circuit 8 is output to the result latch line 26 (see result latch line 26 in FIG. 3).
. At this time, the address O has already been output to the address bus line 12, and this address 0 is the exclusive OR circuit 4.
is also input, and the signal 0 passing through the comparison data line 24
If it is OK, it is “0”, N
If OK, '1' is input to the flip-flop 6 via the result output line 28, and this signal is sent to the result latch line 26.
The output signal is set in the flip-flop 6 and is input to the input/output control device 3 through the result output line 23 (see the word output line 23 in FIG. 3). On the other hand, the signal passing through the result latch line 26 passes through the inverter 10 and operates the flip-flop 7. The output signal of this flip-flop 7 is transmitted to the gate line 27. AND circuit 8 through inverter 11
(If the gate of the AND circuit 8 is not turned off by this flip-flop 7, as can be seen in FIG. 3, after the gate I is turned on, the memory lead line 18 and the machine cycle 1 line 22 are turned on in the memory read cycle M2. Signal +
There are several places where f'f- matches. By turning off the gate, it is possible to open the gate only at the first detection and output a signal to the output line 26).

Next, in order to read the result in the program 43, the central processing unit 1 reads the instruction code from the memory 2 as described above, determines it to be an input instruction, further reads the contents of the memory 2, learns the input device address, and as shown in FIG. The input device address is sent to the address bus line 12 at the timing of the instruction and input/output cycle M3, and then the input device address is sent to the input/output request line 15. A signal is sent to the lead wire 16. This signal is generated by the signal generation circuit 5
The signal is converted into an input/output lead signal, outputted to the input/output lead wire 20, and inputted to the input/output control device 3. The input/output control device 3 that has found an address match with the input device address output to the address bus line 12 outputs the data from the result output line 23 to the data bus line 13 in response to the input/output read signal, and uses this result for central processing. Device 1 reads (
(Refer to the timing of the input/output lead wire 20 in FIG. 3).

Next, the program 44 judges the result, and if there is an error, the error processing of the program 52 is executed. Also O
If K, then the program 45 turns off the gate in the same manner as the program 41 described above, and the input/output control device 3
gate line 25 is turned off, AND circuit 8 is gated off,
The flip-flops 6.7 are reset and the circuit becomes operational.

Through the above processing, the address bus line 12 is set to address 0, the comparison data is set to "O", and the exclusive OR is performed to determine whether the address bus line 12 is stacked at "1".

Next, the operations of programs 46 to 51 are performed in the same manner as the above programs 40 to 45, and by setting the address FFFF on the address bus line 12, setting the comparison data to °1'', and taking the exclusive OR, , address bus line 12°
I understand the °0 path strike.

FIG. 2 is a circuit diagram showing an example of the exclusive OR circuit in FIG. 1. In the figure, address bus lines 12 (in this embodiment, 16 address bus lines from address 0 to FFFF)
(H) (up to the address can be specified) and the same signal is also input to the comparison data line 24, the inputs of the exclusive logic elements 30 and 31 match, and the inputs of the exclusive logic elements 30.
31 outputs "0", which is aggregated by the OR element 32 and outputs °0'' to the result output line 28, indicating an OK signal.If the signal input to a part of the address bus line 12 is the opposite When input, the exclusive logic element at that location has an input mismatch, and °°1'' is output from that element, resulting in output line 2.
“1°” is output to 8 to indicate the NOK signal.

〔Effect of the invention〕

As explained above, the present invention adds an exclusive OR circuit, a flop-flop, and a timing circuit to the conventional circuit,
By simply adding a program for determining the address bus test results as an extension of the conventional function, abnormal program operations and address buses can be quickly tested.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of the exclusive OR circuit in FIG. 1,
FIG. 3 is a time chart showing the operation timing in FIG. 1, and FIG. 4 is a program flow diagram for operating the embodiment shown in FIG. DESCRIPTION OF SYMBOLS 1... Central processing unit, 2... Memory, 3... Input/output control device, 4... Exclusive OR circuit, 5... Control signal generation circuit, 6.7... Flip-flop , 8...
・AND circuit, 9, 10.11... Inverter, 12
...Address bus line, 13...Data bus line, 14
...Memory request line, 15...I/O request line, 16...Read line, 17-...Write line, 18
...Memory lead wire, 19...Memory lead I line,
20... Input/output lead wire, 21... Input/output callide wire, 22... Machine cycle 1 line, 23.28... Result output line, 24... Comparison data line, 25.27...
Gate line, 26...Result latch line, 30.31...
Exclusive logic element, 32... OR element, 40. ~52・
...Program, Ml...Ins I-action fetch cycle, M2...Memory read cycle, M3
...I/O cycle. ,＼ Agent Patent Attorney Uchihara Otodai 2I! I early 4TM

Claims (1)

[Claims] A central processing unit that executes a program, a memory that stores a program, various input/output control devices, an exclusive OR that takes an exclusive OR of an address bus from the central processing unit, and a signal line from the input/output control device. It is equipped with an exclusive OR circuit, a flip-flop that latches the result of the exclusive OR circuit, and various timing circuits for performing this latch, and the address 0 and the address bus are all "1" in the address bus. An address bus test circuit characterized in that an address is set and an exclusive OR is performed between a signal line from the input/output control device and the address bus.