JPS59211123A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To improve the efficiency of a working test by obtaining a device which delivers the data on an internal bus to an output port in a test mode with a simple constitution. CONSTITUTION:The logic level of a test input signal TEST is set at 1 and therefore the output of an OR circuit 21 is set at 1 regardless of PAout. Then the data on an internal bus 18 is read into a flip-flop 19 with the cycle of a clock signal and delivered to a port PA. Thus it is possible to monitor an optional internal bus from outside. This improves the test efficiency.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having a data bus for transferring data in parallel and a port for inputting and outputting data on the data bus.

Conventionally, when manufacturing a semiconductor integrated circuit that has a memory section, arithmetic section, data bus, input/output board, etc.

We are conducting tests to confirm that it works correctly.

For example, program memory, data memory, general-purpose registers, accumulators, arithmetic and logic units, input/output ports,
In the operation test of a single-chip microcomputer equipped with a data bus and the like on the same semiconductor substrate, it has conventionally been necessary to execute an instruction to output the result to the board after each instruction is executed in order to detect whether the operation is good or bad. For this reason,
If you try to improve the detection rate of operational tests, the test time will increase,
Also, there was a drawback of increasing the pattern memory required by the tester. Let's explain this using drawings.

FIG. 1 is a block diagram in bold part of an example of a conventional si/gle step micro combinator.

Although not shown, the operation timing of each circuit inside the micro combinator is determined by a basic clock. Further, each instruction is basically executed on the basis of a machine cycle generated by a basic clock and a control circuit, and one or more machine cycles are required to execute one instruction.

Regarding the execution process of an instruction to perform an arithmetic operation on the contents of the data memory 6 addressed by the general-purpose register 4 and the accumulator 8 whose contents have already been determined, and to store the result in the data memory in the micro combinator shown in Fig. 1. explain.

In the first machine cycle, the contents of program memory 5 are read and set into instruction register 10.

This is coded by an instruction decoder 11 to generate various control signals according to the instruction. In the second machine cycle, the contents of data memory 6 addressed by general register 4 are read and set into temporary storage register 7. In the third machine cycle.

The arithmetic logic operation unit 9 performs a synergistic emulator 8. Performs arithmetic operations with temporary storage registers. The calculation result is written to the data memory 6 in the fourth machine cycle. During the execution of an instruction,
Data transfer between each block is performed via an internal data bus 18, and the program memory 3 is counted up according to each instruction.

When the above instruction is executed and it is confirmed that this instruction has been executed normally, in the conventional configuration, the contents of the data memory 6 must be output to the port 12 or 13 by a program after this, and for this purpose, two It was not possible to check the operation of an instruction without executing one instruction.

When checking the operation of each command, reading from the siprogram memory 5 is prohibited by an external control signal.

Give any instruction code and data to the test program via the data bus port 16, and send the result to the test program (baud) 1
It is possible to configure the output to 2 or 13. However, even if this means is used, if the detection rate is to be improved, the number of test program steps will inevitably increase significantly due to the addition of an output command to the baud 12 or 13. This means a significant increase in test time and pattern memory required in the tester.

Furthermore, due to configuration limitations, when reading the contents of the program memory 5 sequentially to check the operation of each instruction, if no output instruction to the boat appears on the program, the operation of the previous instructions will not be checked. . Therefore, even if a defect is detected, it is not only difficult to confirm the location of the defect, but also has the drawback of causing a decrease in the detection rate of defective operations.

The present invention eliminates the above-mentioned drawbacks and provides a semiconductor integrated circuit in which data on an internal bus is output to a board during testing by adding a small number of circuits, thereby increasing the efficiency of operational testing.

The semiconductor integrated circuit of the present invention has a data bus for transferring n-bit data in parallel, and outputs a logical sum of a first control signal generated by an output command and a test input signal input from the outside. an AND circuit that outputs the AND of the output of the OR circuit and a clock signal as a second control signal.

the second control signal; and the test input signal is the first control signal.
When the test input signal is at a second logic level, the data of each bit of the data bus is output as a baud HC according to the logic level of the first control signal, and when the test input signal is at a second logic level, the first control signal and a flip-flop that outputs the data of each pit of the data bus to the boat at the cycle of the clock signal, regardless of the control signal of the data bus.

Next, embodiments of the present invention will be described using the drawings.

FIG. 2 is a block diagram of one embodiment of the present invention.

In FIG. 2, only one bit outputted to the conversion capo) FA corresponding to the conversion capo) 12 in FIG. 1 is representatively shown. This embodiment is based on the logic of a data bus 18 for transferring n-bit data in parallel, a first control signal PAout generated by an output command, and a test input signal 'l'est input from the outside. OR times that output the sum 12!21
Logic of the output of the OR circuit 21 and the clock signal φ Yokokura Second control 6- The AND circuit 20 outputs as a signal, and this second control signal is input, and the test input signal Te5t is (When it is at the logic level, the data in each pit of the data bus 18 is baud according to the logic level of the first control signal PAout.)
When the test input signal Test is at the second logic level, the data of each bit of the data bus 18 is output to the boat at the cycle of the clock signal φ, regardless of the first control signal PAout. It is configured to include a flip-flop 19.

Next, the operation of this embodiment will be explained.

If the logic level of the test input signal Te5t is tlO'', the first control signal PAout is set to 11 by the output command.
", then the output of the OR circuit 21 is 61". When the clock signal φ becomes 11", the data on the internal data bus is read into the flip 70 block 19 and output to the boat PA. The output data is held until the next output command. Next, if the logic level of the test input signal Te5t is "t", the output of the OR circuit 21 is 11'' regardless of PA 011 during this time, and the clock signal φ The data on the internal data bus 18 is read into the 7-lip flop 19 and output to the port PA at the cycle of .
By doing so, data can be outputted to the outside at the cycle of the clock signal φ, and the internal data bus can be arbitrarily monitored from the outside.

For each instruction, all data transfer between various memories, registers, ports, etc. is performed via the data bus, so by monitoring the data bus, the detection rate of the operation of each instruction can be greatly improved.

Furthermore, since there is no need to issue an output command to the boat required to improve the detection rate, the number of test programs can be significantly reduced. Therefore, it is possible to shorten the test time in a tester or the like and reduce the required pattern memory.

The boat controlled by the test input signal Te5t is:

The port 12 is not limited to the output port 12 shown in FIG. 1, and may be an input/output port 13.

As described above in detail, the present invention enables defect detection in semiconductor integrated circuit testing by simply adding a test input signal and making slight changes to the board circuit without adding a complicated control circuit. This has the effect of making it possible to significantly improve the rate.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a main part of an example of a conventional single-chip microcomputer, and FIG. 2 is a circuit diagram of an embodiment of the present invention. l...Oscillating unit, 2...Control unit, 3...
...Program counter, 4...General-purpose register, 5...Program memory, 6...
・Data memory, 7...Temporary storage register, 8
...Akinimulator, 9...Arithmetic logic operation unit, 10...Instruction register, 11...
...Instruction decoder, 12...Output port, 13
...Input/output port, 14...Input boat% 15...Address output port, 16
...Data bus port, 17...Internal address bus, 18...Internal data bus, 19
...Flip-flop% 20...AND circuit, 21...OR circuit, PA...
- Boat, 9-PA□ut...First control signal. Te5t...
...Test input signal. io-

Claims (1)

[Claims] a data bus for transferring n-bit data in parallel;
An OR circuit that outputs the logical sum of a first control signal frequently generated by an output command and a test input signal input from the outside, and a second control signal that outputs a logical product of the output of the OR circuit and a clock signal. and an AND circuit that inputs the second control signal, and when the test input signal is at a first logic level, outputs each bit of the data bus according to the logic level of the first control signal. outputting data to a boat, and when the test input signal is at a second logic level, outputting data of each bit of the data bus to the boat at a cycle of the clock signal, regardless of the first control signal; A semiconductor integrated circuit comprising: a slip 70 tab.