JPH0635760A - Buffer device with tracing function - Google Patents

Abstract

PURPOSE:To provide a buffer device with a tracing function capable of executing the analysis of a bug without newly adding a hardware and applicable even to a multi-CPU or the like by utilizing a bus buffer normally existing. CONSTITUTION:This device is connected between a CPU and a multi-bus in a computer, saves access generated from the CPU in a trace memory as history and starting and stopping controls the saving to the trace memory 23 by trace logic 21 so that the bug generated after the development of an user system can be analyzed by reading the history of the access saved in the trace memory 23. Further, the bug analysis is enabled without newly adding hardware by utilizing the bus buffer normally existing. Also, by using a large-scale ASIC, the device can be applied even to the multi-CPU or the like.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a buffer with a trace function which is applied for examining RAS (reliability: reliability, availability: serviceability: serviceability) for a personal computer or a control computer using a microprocessor. Regarding the device.

[0002]

2. Description of the Prior Art Microprocessors have 8 bits, 16
There are 32 bits and 32 bits. Program debugging and bug investigation are being conducted on these microprocessors.

In this investigation, execution results of instructions issued from the CPU and access results such as read / write to the memory are accumulated in the trace memory in real time, and the access results of the CPU accumulated in the trace memory after the trigger is established. By reading.

As a development support tool for such debugging, for example, an in-circuit emulator (in cir
cuit emulator: ICE) is used. This IC
In E, the CPU on the ICE side is operated inside the user system, and the execution contents of the CPU are sequentially tracked and monitored by the software of the ICE. In addition, this ICE controls the CPU execution under certain conditions, changes the memory contents, I / O execution, etc. by intervening ICE software, and the circuit conditions are normal under conditions similar to those of the actual machine. It has a function of grasping whether there is any and whether the function is sufficiently satisfied.

When this ICE is actually used, as shown in FIG. 2, the adapter 2 of the ICE main body 1 is connected to the CPU socket 4 of the processor 3 equipped with a CPU, and the ICE
An analyzer 5 such as a probe box, a memory, or a personal computer is connected to the main body 1. The ICE may be, for example, Intel 386D.
X, 486DX and Motorola 68000 series are available for each function.

[0006] These ICEs provide abundant functions, language processing such as a compiler and assembler, and an integrated development environment such as a man-machine interface, and are very useful for software developers.

However, bugs that occur after the development of the user system, such as insufficient read margin of the hardware, errors that rarely occur due to processing timing, and discrepancies in stack push and pop operations, etc. are actually the behavior of the user system. Often happens inside. For this reason,
It is difficult to analyze such a bug with the ICE attached. Further, in order to analyze a bug for multi CPU, DMA, etc., ICE must be connected to each CPU. Moreover, ICE is expensive.

[0008]

As described above, it is difficult to analyze a bug that occurs after the development of the user system in the state where the ICE is attached as described above. Also, in the case of multi-CPU etc. ICE must be connected.

Therefore, the present invention makes it possible to analyze a bug that occurs after the development of the user system by utilizing a bus buffer that normally exists without adding new hardware, and also for a multi-CPU or the like. It is an object to provide a buffer device with a trace function that can be applied.

[0010]

The present invention provides a buffer device connected between a CPU and a multi-bus in a computer.

A trace memory and a trace control means for saving at least access issued from the CPU as a history in the trace memory and controlling start and stop of saving of the history are traced to achieve the above object. It is a buffer device with a function.

[0012]

By providing such means, it is connected between the CPU and the multi-bus in the computer,
The access issued from the CPU is saved as a history in the trace memory. In this case, the saving of the access of the CPU to the trace memory is controlled by the trace control means to start and stop.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a buffer device 10 with a trace function. The buffer device 10 functions as a bus buffer and has a bus arbitration logic and a bus buffer. That is, for example, Intel 38
In the 6DX and 486DX classes, a multibus and a common memory are often used, which requires an arbitration logic and a bus buffer.

The buffer device 10 uses such a bus buffer, and is composed of an ASIC (application specific integrated circuit), for example, a gate array. The buffer device 10 is a C in a computer.
It is connected between the PU and the multi-bus, I / O bus, system bus, and shared memory bus. In the figure, CP
It is connected between U and the multibus.

The buffer device 10 includes an address bus 11 and a status bus 12 each having a serial port.
And a data bus 13 are provided, and these buses 11 to 1
Of the three, the address bus 11 is connected to the address bus 14 from the CPU, the status bus 12 is connected to the status bus 15 from the CPU, and the data bus 13 is connected to the data bus 16 from the CPU.

A unidirectional buffer 17 is connected to the address bus 11, a bidirectional buffer 18 is connected to the data bus 13, and they are connected to an address bus 19 and a data bus 20 on the multibus side, respectively. Also, trace logic 21 and register 2 are connected to these buses 11, 12 and 13.
2 and the trace memory 23 are connected. Of these, the trace logic 21 has the following functions.

That is, an interface function for setting the start / stop trigger conditions for saving the history in the trace memory 23 and the conditions for reading the history contents in the register 22.

According to the condition set in the register 22, the access issued from the CPU, for example, the instruction execution cycle, the code fetch, the memory read / write, etc. are saved as a history in the trace memory 23, and the trigger condition is met. Sometimes it has a trace control function to stop saving history.

With such a configuration, when a start / stop trigger condition for saving the access history and a condition for reading the history content are issued from the CPU, these conditions are set in the register 22 by the trace logic 21.

When the CPU issues an access to this state, for example, a code fetch, a memory, an I / O read / write, etc., these accesses are input to the trace logic 21 through the status bus 15. The trace logic 21 sequentially executes these accesses to the trace memory 2
3 and the addresses and data on the address bus 14 and the data bus 16 at this time are monitored and stored in the trace memory 23. The address and the data are transmitted to the multi-bus side through the unidirectional buffer 17 and the bidirectional buffer 18, respectively.

When the access from the CPU is accumulated in the trace memory 23 in this way, for example, when the program execution state matches the stop trigger condition set in the register 22, the trace logic 21 determines that the access history Stop the trace.

When a history content read command is issued from the CPU, this command is input to the trace memory 23 through the trace logic 21 and the CPU is placed in this state.
Reads the history contents from the trace logic 21.

As described above, in the above embodiment, the connection between the CPU and the multi-bus in the computer is made,
Since the access issued from the CPU is saved in the trace memory 23 as a history and the saving to the trace memory 23 is controlled by the trace logic 21 to start and stop, the access history saved in the trace memory 23 is read. By doing so, it is possible to analyze bugs that occur after the development of the user system. Moreover, the analysis of this bug can be done using the existing bus buffers without adding additional hardware. Also, by using a large-scale ASIC, it can be applied to a multi-CPU and the like. And multi-CP
Since each U CPU can be provided with a trace function of access history, if there is a common factor, each CPU
It becomes easy to obtain the sample data of. Further, the trigger condition set in the register 22 can be changed, and the history of the trace memory 23 can be arbitrarily read by the CPU. The present invention is not limited to the above-mentioned embodiment, and may be modified within the scope of the invention.

[0025]

As described above in detail, according to the present invention, it is possible to analyze a bug that occurs after the development of a user system by using a bus buffer that normally exists without adding new hardware. Moreover, it is possible to provide a buffer device with a trace function that can be applied to a multi-CPU or the like.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a buffer device with a trace function according to the present invention.

FIG. 2 is a configuration diagram of a conventional device.

[Explanation of symbols]

10 ... Buffer device with trace function, 17 ... One-way buffer, 18 ... Bidirectional buffer, 21 ... Trace logic, 22 ... Register, 23 ... Trace memory.

Claims (1)

[Claims] 1. A buffer device connected between a CPU and a multi-bus or the like in a computer, wherein a trace memory and at least an access issued from the CPU are saved as a history in the trace memory, and the history is saved. And a trace control means for controlling start and stop of the buffer function.