JP2520158B2 - Debugging method of digital signal processor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] A debug method by an in-circuit emulator of a digital signal processor in which an input side transfers data from a first-in first-out memory to an internal memory for processing, and a data is transferred to a first-in first-out memory on an output side. When a first-in, first-out memory is empty or full and a halt request occurs,
For the purpose of providing a debug method of a DSP which makes it possible to access each part in the DSP by invalidating those status signals, a digital signal processor includes a microprocessor and an empty signal or a full signal from each of the first-in first-out memory and a digital signal processor. A transfer instruction circuit for generating a ready signal for receiving a write signal or a read signal from the microprocessor is provided, and a control input means for enabling or disabling an empty signal or a full signal is provided. When the ready signal cannot be generated in response to the halt request by the in-circuit emulator, the empty signal or the full signal is invalidated when a control input is received from the control input means, and a ready signal is generated, and the digital signal processor receives the ready signal. Processing It is configured to perform the control for permitting the halt request.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a debugging method of a digital signal processor capable of controlling a halt permission for a halt request from an in-circuit emulator.

In recent years, workstations that perform display-related image processing (coordinate conversion, clipping, etc.) such as design support and structural analysis have come into use.

A digital signal processor (abbreviated as DSP) is used as a processing device for performing such image processing,
The data is processed by the microprogram.

Conventionally, the data to be processed is first-in first-out memory (first-in first-out memory: called FIFO).
Is read out from and transferred to the RAM of DSP, and the processed data is transferred to the write-in first-out memory on the output side.

A program is developed for each DSP according to the processing function, and debugging is performed to confirm the normality of the program. Conventionally, in DSP debugging, a program is executed by an in-circuit emulator (abbreviated as ICE), a halt request is issued if necessary, and when the halt permission is obtained, the data at that time and the state of the microprocessor are read and analyzed. It is carried out.

In that case, the data to be processed is the FIFO on the input side (previous stage).
It is read from and transferred to the RAM of the processor, and after being processed by the processor, transferred to the output side (post-stage) FIFO and written. However, the first stage FIFO
If the data is empty (empty), or the latter FIFO
Is full, the processor cannot execute the instruction in the waiting state.

When debugging, it is necessary to detect the data of each part of the DSP in such a standby state, but there was a problem that it could not be done.

[Prior Art] FIG. 6 is a block diagram of a conventional example.

In FIG. 6, 60 is a first-in-first-out memory on the input side (represented by FIFO), 61 is a digital signal processor (represented by DSP), 62 is a microprocessor (represented by MPU), 620 is a program address bus, and 621 is Program data bus, 6
3 is RAM, 64 is ROM, 65 is output FIFO, 66 is in-circuit emulator (displayed by ICE), 67 is instruction memory holding proxy instructions, 68 is control unit, 69 is personal computer (abbreviation of personal computer) Is displayed).

Explaining the debug operation of the conventional DSP61, the MPU originally
62 operates according to the program stored in ROM 64,
ROM64 is created after programming, debugging and bug elimination. Therefore, when debugging, ROM64
If the program to be debugged is held in the instruction memory 67 of this in-circuit emulator 66 and the program is read and accessed by the MPU62 of the DSP61, the program is read from the instruction memory 67 and executed. It

The program address 620 is used as the address bus of the instruction memory in the ICE66 before the halt enable signal is transmitted, and is set in the direction from the DSP61 to the ICE66. After the halt enable signal is sent, the ICE66 is set in the DSP direction to access the RAM63 in the DSP61 and the registers in the MPU62.

Further, the program data bus 621 is used for the data of the instruction memory 67 in the ICE 66 before the halt enable signal is transmitted, and is set in the direction from the ICE 66 to the DSP 61. After the halt enable signal is sent, the data direction is set by the read / write signal from the ICE66.

MP at some stage of the program when debugging
When it is desired to stop the operation of U62, the control unit 68 of the ICE 66 outputs the halt request signal 680. On the other hand, when the MPU 62 finishes the instruction being executed, the halt enable signal 681 is output to the ICE 66. When this is received, the ICE66 outputs the address of the register in the MPU62 that wants to access the program address bus 620 and the address in the RAM63, and the address setting signal 683
Outputs a timing signal for validating an address on the bus. Also, at this time, the read / write signal 682 from the ICE
To read the data from the addressed location or write the data to that location. Thus, the operation of reading the data in the addressed register or memory location of the MPU 62 or RAM 63 or writing another data there is performed. At that time, PC 69
Is used as a means for displaying the read data and inputting the data to be written.

The data processed by DSP61 is F
The data supplied from the IFO60 and stored in the FIFO60 is read out in the first-in first-out format, and the program data bus 621
Is transferred to the RAM 63 via. The data stored in the RAM 63 is subjected to arithmetic processing by a program, and the processing result is output to the FIFO 65 on the output side via the program data bus 621.
Transferred to.

When the MPU62 finishes processing the data being executed and transfers it to the FIFO65, the read control signal (inverted) is sent to the FIFO60.
"0" is output as (displayed by R1). In contrast, FIFO60
When the data to be read is stored in, the empty flag (inversion EF1) becomes "1". Then, the input side ready signal RDY1 with the output of the AND circuit 613 becomes “1”, and the NOR (NO
The R) circuit 614 outputs the inverted ready (inverted RDY1) signal “0”, and the MPU 62 can execute the read instruction.
The data is read from and transferred to the RAM 63 through the program data bus 621. FIG. 7 is a read flow chart of the conventional example described above. MDO in FIG. 7 represents the output data stored in the FIFO 60.

Returning to FIG. 6, to explain the writing, RAM63
After performing arithmetic processing on the data transferred to the MPU62
When transferring data from the FIFO to the FIFO 65, "0" is generated as the write control signal (displayed by W1 inversion). FIFO at this time
65 full flag (inverted if there is room to store data from
"1" is output as FF1). In this case, the output ready signal RDYO1 which is the output of the AND circuit 612 becomes “1”,
When the inverted ready (inverted RDY1) signal from the NOR circuit 614 becomes “0”, the MPU62 can execute the write instruction and the RAM
Transfers 63 data to FIFO65. FIG. 8 shows a writing flow chart of the conventional example described above. In Figure 8 MDI
Is the input data written to the FIFO65.

When there is no data in the FIFO60 and the empty flag (inverted EF1) is "0" during the program operation, or F
When all the data is stored in the IFO65 and there is no room for new writing and the full flag (inversion FF1) becomes "0", the output of the AND circuit 612 or 613 becomes "0" and the NOR circuit 61.
The inverted ready (inverted RDY1) signal from 4 becomes "1". In this state, the MPU 62 waits for the ready signal to be generated (inversion RDY1 is "0"), and instruction execution is not performed.

[Problems to be Solved by the Invention] In the above conventional debug operation, when a halt request signal is sent from the ICE66, when the data in the FIFO60 is empty (empty), or when the FIFO65 is full (full),
Waiting for a read or write instruction to execute
In response to the halt request signal, the halt enable signal is not responded within the specified time because the instruction execution is not completed. Therefore, a time-out error occurs, and the RAM63 of DSP61, MPU62
There was a problem that it was not possible to read or write to the registers inside. That is, in the case of an empty state or a full state, knowing various kinds of data such as what program processing and what kind of data processing has performed such a state, and input data for coping with it. You will not be able to do things.

INDUSTRIAL APPLICABILITY The present invention provides a DSP debugging method in which, when a first-in first-out memory is empty or full, a halt request is issued when the DSP is debugged, these status signals are invalidated and each part in the DSP can be accessed. The purpose is to do.

[Means for Solving the Problems] FIG. 1 shows a basic configuration of the present invention.

In FIG. 1, 10 is control input means, 11 is first-in first-out memory (FIFO) on the input side, 12 is a digital signal processor (DSP), 121 is a transfer instruction circuit, 122 is a microprocessor (MPU), 123 is RAM, and 124 is ROM, 13 is a light-in first-out memory (FIFO) on the output side, and 14 is an in-circuit emulator (ICE).

The present invention, when reading data from the input side FIFO in the DSP, or writing data to the output side FIFO, when the input side FIFO empty state or the output side FIFO full state occurs, the transfer A transfer instruction circuit for instructing execution can generate an execution instruction by a control input for invalidating an empty signal or a full signal so that a halt permission can be generated for a halt request at the time of debugging.

[Operation] The data supplied from the previous stage is stored in the input side FIFO 11 of FIG. 1, and the data is transferred to the RAM 123 by the MPU 122 of the DSP 12 and R
After being processed by the program stored in the RAM 141 of the ICE in the AM 123, the data in the RAM 123 is transferred to the output FIFO 13.

The transfer instruction circuit 121 of the DSP 12 receives each of the read control signal R and the write control signal W from the MPU 122,
At that time, the states of the empty flag E and the full flag F from the input side FIFO 11 or the output side FIFO 13 are discriminated, and if the conditions are satisfied, a ready (RDY) signal is output to the MPU 122. In this case, when there is data in the input side FIFO 11 (when not in the empty state), the RDY signal is generated in response to the read control signal R and reading is executed. Similarly, if there is an area for storing data in the output side FIFO 13 ( When not in the full state) The RDY signal is generated in response to the write control signal W and writing is executed.

When read or write control is performed when the input side FIFO 11 is in the empty state and the output side FIFO 13 is in the full state, the transfer instruction circuit 121 cannot normally generate the RDY signal, so a halt request is issued for debugging. Even if it occurs from ICE14, the halt permission cannot be output. Therefore, the control signal WAITO on the input side or the control signal WAITI on the output side is input from the control input means 10. By this input, the transfer instruction circuit invalidates the empty flag E or the full flag F at that time and outputs the RDY signal. When the RPU signal causes the MPU 122 to execute the read or write command and end, the MPU 122 receives the halt request from the ICE 14 and outputs the halt permission. Then, from ICE14 to DSP12
Data in the MPU122 or RAM123 can be addressed and read.

[Embodiment] FIG. 2 shows a block diagram of an embodiment of the present invention.

20 to 29 of FIG. 2 are 60 to 60 in the configuration of the conventional example of FIG.
Corresponding to 69, 20 is input FIFO, 21 is DSP, 22 is MUP,
220 is a program address bus, 221 is a program data bus, 23 is RAM, 24 is ROM, 25 is an output FIFO, 26 is an IC
E and 27 are instruction memories holding proxy instructions, 28 is a control unit, 2
9 indicates a personal computer.

In the configuration of the embodiment, the normal debugging operation is the same as the operation described for the configuration of the conventional example (FIG. 6), and therefore will be omitted. A specific configuration example of the transfer instruction circuit 121 in FIG. 1 is the circuits 210 to 216 in the DSP 21, and the control input means in FIG. 1 is not shown, but a well-known switch circuit (switched manually or by software). Control signals WAITO1 and WA generated from the switch.
ITI1 is supplied from the signal lines 200 and 201, respectively.

A block diagram of the transfer instruction circuit of FIG. 2 is shown in FIG. 3 (a), and a diagram showing its truth value is shown in FIG. 3 (b).

FIG. 3 (a) a. EF is the input FIFO20
This is the inverted signal of the empty flag (Fig. 2), and the FIFO
This signal is "0" when 20 is empty and "1" when it is not empty. R is a signal obtained by further inverting R1 which is a read control signal from the MPU 22 in the inverter circuit 210, and becomes "1" when reading is performed.

In addition, FIG. FF is the output FI
This is the inverted signal of the full flag of FO25 (Fig. 2), and FIFO25
This signal becomes "0" when is in the full state, and becomes "1" when not in the full state. W is a signal obtained by further inverting the inversion W1 which is the write control signal from the MPU 22 in the inverter circuit 211, and becomes "1" when writing is performed.

FIG. 3 (a) a. And b. RD for control signals WAITI and WAITO “1” and “0” for each combination of R / W control signals and each state of inverted EF / inverted FF signals
Outputs of YI (read execution ready signal) and DYO (write execution ready signal) are shown in FIG. 3 (b).

According to this, by setting WAITI or WAITO to "0", reading (R = "1") or writing (Empty FE = "0") or full (Inversion FF = "0") or write ( For W = "1", the ready output (RDYI, RDYO) becomes "1", the instruction can be executed, and the empty flag and full flag are invalidated.

That is, when reading (R = “1”), the FIFO 20 is empty (inversion EF =
In case of "0"), the control signal is WAITI = "0", that is, no WAI
By setting it to T, RDYI = "1" (ready state), and the MPU22 can execute (read) instructions. In this case, the FIFO20 does not contain any data, but it will be read.However, if the halt request signal 280 is output from the ICE26 before that, the MPU22 will grant the halt request to that halt request immediately after the execution of that instruction. Signal 281 is output and ICE
From 26, it is possible to access each part of the DSP 21 and obtain data of each part for knowing the situation when the FIFO 20 becomes empty.

If WAITI = "1", that is, WAIT is set, inversion EF
RDYI becomes "1" only when = 1 (not empty) and read (R = "1"), and the status signal (inversion EF) is validated.

Similarly, if WAITO = "0", immediately set to no WAIT,
Even if the write (W = "1") is in the full state (reverse FF = "0"), RDY = "1" (ready state), and the MPU22 can execute the instruction.

In this case, when the halt request signal 280 is output from the ICE26, transfer to the FIFO25 (writing data in the full state) is performed, but after that, the halt enable signal 281 is input and the DSP21 is You can access each part.

If WAITO = "1", that is, WAIT is set,
Inversion FF = "1" and write (when W = "1", RDY = "1", enabling the status signal).

FIG. 4 shows a block diagram of another embodiment 1 of the present invention, and FIG.
FIG. 9 shows a block diagram of another embodiment 2 of the present invention.

In both cases of FIG. 4 and FIG. 5, FIFO-DSP-FIFO
-DSP-FIFO has multiple stages of digital signal processor (DSP) to process input data sequentially. Then, the control signals WAITI and WAITO according to the present invention are supplied to the DSP1 and the DSP2, respectively.
When the halt permission is obtained from the MPU in response to the halt request from CE1 and ICE2, the corresponding DSP1 or DSP2 can be accessed.

In the configuration shown in FIG. 4, a personal computer, which is a means for inputting / outputting data and programs when executing debugging,
Each in-circuit emulator ICE1 and ICE2 is provided separately and operated individually. On the other hand, in the configuration shown in FIG. 5, a single personal computer is shared by the in-circuit emulators ICE1 and ICE2 for operation.

[Effects of the Invention] According to the present invention, at the time of debugging a digital signal processor, it is possible to perform debugging by reading and writing registers and the like in the digital signal processor even when the write-in first-out memory is empty or full. Is possible.

In particular, it is possible to debug under the following conditions.

When a break command (a halt request) is executed while the MPU is waiting from the FIFO and the halt enable signal is not responded within the specified time to the output of the halt request signal, resulting in a timeout error.

When the break command is executed when the input FIFO is empty or the output FIFO is full and the MPU is waiting due to a DSP program creation error, and the following occurs.

When multiple ICEs are connected and a halt request is issued to multiple units, and a halt request is applied in the empty or full state, and the same as the following cases.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a basic configuration diagram of the present invention, FIG. 2 is a configuration diagram of an embodiment of the present invention, FIG. 3 (a) is a configuration diagram of a transfer instruction unit, and FIG. 3 (b). Shows a motion truth value, and FIG. 4 shows 1 of another embodiment.
5 is a block diagram of another embodiment 2, FIG. 6 is a block diagram of a conventional example, FIG. 7 is a read flow chart of the conventional example, and FIG.
The figure is a conventional writing flow chart. In FIG. 1, 10: control input means 11, 13: first-in first-out memory (FIFO) 12: digital signal processor (DSP) 121: transfer instruction circuit 122: microprocessor (MPU) 123: RAM 124: ROM 14: in-circuit emulator (ICE)

Claims (1)

(57) [Claims] 1. A debugging method by an in-circuit emulator of a digital signal processor for transferring data from a first-in first-out memory on an input side to an internal memory for processing and transferring the data to a first-in first-out memory on an output side, wherein the digital signal processor is a microprocessor. And a transfer instruction circuit that generates an empty signal or a full signal from each of the first-in first-out memory and a ready signal for performing a transfer in response to a write signal or a read signal from the microprocessor, and the empty signal or the full signal is enabled. Control input means for enabling or disabling is provided, and the transfer instruction circuit receives the control input from the control input means when a ready signal cannot be generated in response to a halt request by the in-circuit emulator. The ready signal is generated to disable the Petit signal or full signal, wherein the digital signal processor debugging system of the digital signal processor and performing control to permit the halt request executes processing by the ready signal.