JPS6316350A - Microprocessor control system - Google Patents

Abstract

PURPOSE:To simplify the constitutions of peripheral circuits and to perform the parallel reading jobs and individual debug jobs, by dividing a cache memory into each function. CONSTITUTION:A cache memory contains an instruction cache memory 7 and an operand cache memory 8. When the memory 7 received an access with the signal supplied from an address generating circuit 10, an access is given to a ROM 9 via a register 13 or 14, a selection circuit 48, an FIFO buffer 15 or 16, a selection circuit 47 and a register 38. Thus the microinstruction read out in such a way produces various control signals through a cache memory control circuit 12 and therefore reads the data serving as an operand out of the memory 8. Thus two types of data are stored for each function and the parallel and simultaneous accesses are possible to both memories. Then the next instruction can be read out simultaneously with a data reading action.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a microprocessor control system, and particularly relates to a microprocessor control system that incorporates multiple cache memories suitable for increasing the functionality and speed of a cache memory, and speeding up software debugging. This paper relates to a microprocessor control system.

[Conventional technology]

For example, MC68020 32-bit Microprocessor User's Manual, Prentice-Hall, 1984, Chapter 7 (MC6802032-bit
Microprocessor 'User's
Manual.

Prentice-Hall, 1984, 5ecjio
32-bit microprocessor M described in
C68020, or IE Micro, December 1985, pages 23-36 (Eng.
EE MICRODEC, 198S, pp, 23-3
The 32-bit microprocessor 280000 described in 6) has a single cache memory built-in on the chip. The cache memories of these microprocessors are controlled by microinstructions and only one bit on an external terminal that determines whether or not all contents of the memory are to be invalidated.

[Problem that the invention seeks to solve]

Since cache memory is on-chip, it is forced to have a small capacity and is required to be high speed.

Cache memory stores a set of addresses and data that have been accessed once, and when an attempt is made to access the same address again, the data corresponding to that address is stored in the cache memory before accessing the outside of the chip, that is, the main memory. Check whether it is held in .

If the desired data exists in the cache memory, there is no need to access the outside of the chip, and processing speed increases accordingly. In this case, it is necessary to quickly determine whether the desired data exists in the cache memory.

The associative memory is realized by a circuit that implements this determination in hardware, and is capable of high-speed processing. However, since the associative memory has a more complex circuit configuration than a simple memory, it is difficult to increase the capacity. In addition, search data must be given to all comparators corresponding to the data to be associated, so the larger the memory capacity, the more
It becomes difficult to increase the speed.

Another problem is the difficulty of debugging. °In other words, if there is memory inside the processor that captures instructions prior to execution, such as a cache memory or a brief fetch register, it is possible to determine what kind of instruction the processor is executing from outside the chip. This becomes extremely difficult. In such a state, it is difficult to check the operating state of the chip during software debugging.

Conventionally, this has been dealt with by prohibiting access to the cache memory and setting it in trace mode. In that state, prefetched instructions are always invalidated, and each time one instruction is executed, an access is made to the outside of the chip to fetch the next instruction. In this way, by accessing the external, ie main memory, the address bus is passed, so by monitoring it, it is possible to detect the boundaries of each instruction, and when debugging, it is possible to detect the boundaries of each instruction. You can stop it and check its operating status.

Typically, an in-circuit simulator is used for such checks on the operating state of the chip. This is a device that emulates the operation of a chip using software. This device is generally capable of detecting access to a particular address. However, when operating in trace mode as in the above method, there is a problem in processing speed because the internal state of the chip is saved to external memory for all executed instructions, which is a wasteful process.

One way to solve this problem is to set the trace mode immediately before the instruction you want to check, but in that case, the software that is the target of debugging would have to be changed, which is inconvenient. Furthermore, the software must be modified every time the instruction to be checked changes, reducing debugging efficiency.

An object of the present invention is to improve these conventional problems, expand the functions of cache memory, speed up the operation, and improve the efficiency of debugging a system having multiple cache memories. The objective is to provide a control method.

[Means for Solving the Problems] In order to achieve the above object, the microprocessor control system according to the present invention incorporates a plurality of physically divided cache memories, and each cache memory is configured to operate independently and in parallel. It is characterized by processing.

[For production]

In the present invention, by functionally dividing the cache memory, the capacity of each cache memory can be reduced, the peripheral circuitry can be simplified, and new functions can be added to each memory. It becomes possible. Furthermore, by performing processing on the divided cache memories in parallel, it is possible to speed up the processing. In addition, a cache memory selection line and a signal line for specifying processing are provided on the chip's external terminals to enable direct control from outside the chip, and a flip-flop is provided.
High-speed debugging using an in-circuit emulator makes it possible to execute each instruction individually.

Since the divided memories can be physically distributed and placed, they can be placed close to the devices that process the data held by the individual memories, allowing for a larger layout margin in terms of processing speed.

〔Example〕

FIG. 1 is a block diagram of a microprocessor showing an embodiment of the present invention. Here, the configuration of a microprocessor 1 that controls two cache memories 7.8 by a microprogram is shown. Both cache memories 7 and 8 use associative memories, one being an instruction cache (for example, memory 7) and the other being an operand cache (for example, memory 8). In this case, the cache memory control circuit 12, register 38, selection circuit 22, etc. shown in FIG. 1 correspond to the control section of the cache memory 7.8. The control information inputted to the control circuit from outside the chip includes one bit (purge information P tT RGE shown in FIG. 3) indicating whether or not to invalidate the contents of the two cache memories 7 and 8, and one bit indicating whether or not to invalidate the contents of the two cache memories 7 and 8. This is 2 bits of control information (D7, 06 in FIG. 3) for selecting the appropriate cache. States other than invalidation, ie, data writing, reading, and state maintenance, are controlled by microinstructions.

In FIG. 1, 1 is a microprocessor, 5 is a main storage device, LSI, L64 is the aforementioned external terminal,
Also, input terminal L41. to the purge control circuit 6. L49 is connected to the output terminal from the cache memory control circuit 12. Processor 1 and main memory 5 are coupled through address lines, data lines, and two control lines.

2 is an interface unit, 3 is an instruction control unit, 4 is an instruction execution unit, 6 is a purge control circuit, and 9 is a control storage RO that stores microinstructions.
M, 10 is an address generation circuit, 11 is a decoder, 12 is a cache memory control circuit, 13, 14 is a register for setting the instruction read from the cache memory 7, 15, 16, and 17 are first-in, first-out FIF○ buffers. It has a function of sequentially moving bit strings as they are input.

47.48 is a selection circuit, and 38.40 is a register.

It is assumed that the cache memory 7 stores instructions and the cache memory 8 stores data.

When the cache memory 7 is accessed with the address generated by the address generation circuit 10, the previous instruction is prefetched from the cache memory 7, and the register 13
．． or set to 14. The signal is sent from the register 13 to the register 40 via the selection circuit 48 or stored in the FIFO buffer 15 or 16. & After the first stored instruction in the FIFO buffer 15 is taken out and input to the decoder and analyzed there, the selection circuit 47,
The ROM 9 is accessed via the register 38. The thus read microinstruction reads data as an operand from the cache memory 8 by generating various control signals in the cache memory control circuit 12. Selection circuit 22 sends out a selection control signal to specify which cache memory is to be accessed.

This microprocessor 1 processes instructions in a pipeline.

FIG. 5 is a sequence chart of the pipeline processing in FIG. 1. First, after only the instruction is read, the instruction is decoded, and the microcontroller instruction is thereby read. Control is performed according to the contents of the microinstruction, and operand data for the operation is read.

Control is also performed while reading data.

As shown in FIG. 1, instructions are stored in the cache memory 7.
Since the data is stored separately in the cache memory 8, the memory can be accessed simultaneously in parallel. Therefore, as shown in FIG. This has already been done.In this way, the processing speed can be increased.

FIG. 2 is a detailed configuration diagram of the purge control circuit in FIG. 1. When the purge control circuit 6 receives a purge signal from the line L61, it outputs a purge command signal to the line L62.
It also outputs a purge command to line L63. That is, even if the purge signal (LSI) remains at a high level, the purge control circuit 6 alternately performs purge processing and executes one instruction. It has a function to make it easier to use.

When a purge signal is input from line L61 (external terminal), A
The D terminal of the flip-flop 65 is set to high level via the ND circuit 64. When the next command request signal is input via 1L41, the input of the D terminal of the flip-flop 65 is latched at that timing, and the purge command signal on the line L62 is turned on. Therefore, the contents of the register 66, which previously stored the purge command, are latched via the line L64 into the register 38 via the line L63 (see FIG. 1). At this time, the flip-flop 62 is also set. When the purge command is executed by the command execution unit 4, first, a purge clear signal is output to the line L49.

This resets the flip-flop 62.

The D input of the flip-flop 65 is set to low level via the delay circuit 63 and the A N D circuit 64.

When the execution of the purge command is completed, the next command request signal on line L41 is turned on. As a result, the flip-flop 62
is set, and at the same time flip-flop 65 is reset. The output of the flip-flop 62 is sent to a delay circuit 63.
is input. During this time, the register 38 selects the selection circuit 4.
The instruction decode result from 7 will be latched.

Thereafter, the output from the delay circuit 63 becomes high level.

At this time, if the line L61 is still outputting the purge signal, the D input of the flip-flop 65 is at a high level. Therefore, when the next command request signal is input,
A purge command signal is output again to line L62.

An address conversion circuit (not shown) can be connected to lines L61 and L63. The address conversion circuit is
Addresses used within processor 1 and processor 1
The addresses given to external devices are those used by different systems.

Alternately latching purge commands into registers 38.

Let processor 1 execute normal instructions one step at a time,
Programs can be checked. - FIG. 3 is a timing chart of the purge operation in the microprocessor of FIG. 1. Here, the operation when purge (invalidation) of both cache memories is continuously specified is shown.

A31:01 (OQ) is the address signal, AS.

1, 3:0 is an address strobe signal indicating that an address is being output, and DO7:06 is a control code, which is part of the data line corresponding to external terminal L64.

PURGE is a purge signal, and purge signal L61
(low level if the LSI is high level). These signals are all from external terminals of the chip.

The control information for the cache memories 7.8 is captured at the end of the instruction and both cache memories 7.8 are invalidated.

Then the next instruction to be executed (operation word)
is imported from outside the chip and executes only one instruction. At this time, the address (ADDRESS) of the next instruction appears on the external terminal. When performing in-circuit emulation, it is possible to apply a break using this address.

In FIG. 3, the first part BG of address A31 is
This signal indicates the start of purge processing, and the next three address pulses indicate memory access during execution of one instruction. The next signal indicates the start of the next purge process.

Further, the value of the first code signal of data code DO7:06 is input from external terminal L64. The next three signals are opcodes. In this case, one instruction having three addresses (here, 32 bits each) is shown. In this way, even if the control signal continues to be asserted seven times from the external terminal L64, memory flushing is performed on the main storage device 5 under the control of the flip-flop purge control circuit 6.

FIG. 4 is a flowchart of the purge operation in FIG. 1. In normal operation, a next instruction request is output every time one instruction is executed (step 101), and the register 38 is
A microinstruction is read out based on the contents (micro ROM address). However, if the next instruction request is output,
If the purge signal is output (step 102), purge processing is performed (step 103 onwards). In the purge process, the D input of the flip-flop 65 becomes high level, outputs the purge command signal (L62), and latches the contents of the register 66 (L63) into the register 38. Furthermore, a code BG indicating the start of purge processing is output to the address line (step 103).

Next, in the instruction execution unit 4, after the purge instruction is executed, the flip-flop 62 is reset by outputting a purge clear signal (L49), and the D input of the flip-flop 65 is set to a low level (step 1
04). Next, the next instruction request (L41) is output (step 105), thereby causing the D
The input becomes low level, flip-flop 62 is set, and flip-flop 65 is reset. The instruction decode result from the selection circuit 47 is latched into the register 38 (step 106). Then, one instruction is executed by reading the microinstruction from the ROM 9.

In this manner, when the execution of the purge instruction is completed, the next instruction request is output, and the next instruction is then operated normally, that is, the instruction decoding result is latched in the register 38, and only one instruction is executed based on it.

As described above, in this embodiment, by dividing the cache memory into a plurality of parts, (a) parallel access is possible. (b) Functionally divided. (c) The associative memory can be placed near the device that uses it.

〔Effect of the invention〕

As described above, according to the present invention, by dividing the cache memory, the peripheral circuits of each cache memory can be simplified, and the functions of the cache memory can be enhanced. In addition, it is possible to write the same data into multiple memories and to read data from multiple memories in parallel, resulting in faster processing.

Furthermore, since each cache memory can be placed near the circuits that process individual data, a large layout margin can be secured. Furthermore, since we have prepared a way to directly control the cache memory from outside the chip, the state of any cache memory can be dynamically changed. This makes it possible to debug any cache memory. Furthermore, by providing flip-flops that alternately execute instructions and purge sequences, it is possible to execute every l instruction during debugging, thereby increasing debugging efficiency.

[Brief explanation of the drawing]

1 is a block configuration diagram of a microprocessor showing an embodiment of the present invention, FIG. 2 is a detailed circuit diagram of the purge control circuit in FIG. 1, and FIG. 3 is a block diagram of the purge control circuit in FIG. 4 is a flowchart of the purge operation shown in FIG. 1, and FIG. 5 is a sequence chart showing the pipeline processing of the microprocessor shown in FIG. 1. microprocessor, 2: interface unit, 3: instruction control unit, 4: instruction execution unit, 5:
Main storage device, 6: Purge control circuit, 7, 8: Cache memory, 9: Control storage ROM, 10 Near address generation circuit, 11: Decoder, 12: Key reed memory + jJ circuit, 13, 14: Instruction register, 15 ．．
i 6 , 17: FIFO buffer, 22, 47,
48: Selection circuit, 38.40: Register, G 2.6
5: Flip-flop, 63: Delay circuit, 64. :A
ND circuit, 66: register. Patent applicant: Hitachi, Ltd. (1 idiot) -vt+

Claims (1)

[Claims] 1. A microprocessor that is connected to a main storage device and has a built-in cache memory that stores a copy of data stored in the main storage device, which includes a plurality of physically divided cache memories. A microprocessor control method characterized in that each cache memory performs processing independently and in parallel. 2. In a one-chip microprocessor that is connected to a main storage device and has a built-in cache memory that stores a copy of data stored in the main storage device, a plurality of physically divided cache memories and each cache memory are used. It has a built-in purge control means for writing, reading, invalidating, and retaining data in the chip, and the cache memory can be specified from outside the chip via the purge control means, and the cache memory can be A microprocessor control method characterized by instructing a specified process to be performed. 3. The microprocessor control according to claim 2, wherein the purge control means has a flip-flop for causing the cache memory to alternately perform specified processing and execution of one instruction. method.